OV - exec - Loop 216

	Loop Id: 216	Module: exec	Source: build_field.cpp:119-128 [...]	Coverage: 0.04%

0x41edcc MOVPRFX	Z20, Z0

0x41edd0 SDIV	Z20.D, P0/M, Z20.D, Z2.D

0x41edd4 MOVPRFX	Z21, Z0

0x41edd8 MLS	Z21.D, P0/M, Z20.D, Z2.D

0x41eddc SXTW	Z21.D, P0/M, Z21.D

0x41ede0 ADD	Z0.D, Z0.D, Z1.D

0x41ede4 SUBS	X23, X23, X7

0x41ede8 SXTW	Z20.D, P0/M, Z20.D

0x41edec MOVPRFX	Z22, Z21

0x41edf0 MLA	Z22.D, P0/M, Z20.D, Z3.D

0x41edf4 ST1D	{Z18.D}, P0, [X9, Z22.D,LSL #3]    [5]

0x41edf8 MOVPRFX	Z22, Z21

0x41edfc MLA	Z22.D, P0/M, Z20.D, Z4.D

0x41ee00 ST1D	{Z18.D}, P0, [X11, Z22.D,LSL #3]    [2]

0x41ee04 MOVPRFX	Z22, Z21

0x41ee08 MLA	Z22.D, P0/M, Z20.D, Z5.D

0x41ee0c ST1D	{Z18.D}, P0, [X13, Z22.D,LSL #3]    [4]

0x41ee10 MOVPRFX	Z22, Z21

0x41ee14 MLA	Z22.D, P0/M, Z20.D, Z6.D

0x41ee18 ST1D	{Z18.D}, P0, [X15, Z22.D,LSL #3]    [8]

0x41ee1c MOVPRFX	Z22, Z21

0x41ee20 MLA	Z22.D, P0/M, Z20.D, Z7.D

0x41ee24 ST1D	{Z18.D}, P0, [X17, Z22.D,LSL #3]    [1]

0x41ee28 MOVPRFX	Z22, Z21

0x41ee2c MLA	Z22.D, P0/M, Z20.D, Z16.D

0x41ee30 ST1D	{Z18.D}, P0, [X2, Z22.D,LSL #3]    [7]

0x41ee34 MOVPRFX	Z22, Z21

0x41ee38 MLA	Z22.D, P0/M, Z20.D, Z17.D

0x41ee3c ST1D	{Z18.D}, P0, [X0, Z22.D,LSL #3]    [6]

0x41ee40 MAD	Z20.D, P0/M, Z19.D, Z21.D

0x41ee44 ST1D	{Z18.D}, P0, [X4, Z20.D,LSL #3]    [3]

0x41ee48 B.NE	41edcc

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/build_field.cpp: 119 - 128

--------------------------------------------------------------------------------

119:     for (int j = (0); j < (yrange); j++) {

120:       for (int i = (0); i < (xrange); i++) {

121:         field.density0(i, j) = 0.0;

122:         field.density1(i, j) = 0.0;

123:         field.energy0(i, j) = 0.0;

124:         field.energy1(i, j) = 0.0;

125:         field.pressure(i, j) = 0.0;

126:         field.viscosity(i, j) = 0.0;

127:         field.soundspeed(i, j) = 0.0;

128:         field.volume(i, j) = 0.0;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.75
Bottlenecks	P6, P7,
Function	.omp_outlined..2#0x41ecb0
Source	context.h:69-69,build_field.cpp:119-128
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	11.00
CQA cycles if fully vectorized	11.00
Front-end cycles	4.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	11.00
P6 cycles	11.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	32.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.27
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	256.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	67.74
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	90.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	18.18
Vector-efficiency ratio all	97.58
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	92.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.75
Bottlenecks	P6, P7,
Function	.omp_outlined..2#0x41ecb0
Source	context.h:69-69,build_field.cpp:119-128
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	11.00
CQA cycles if fully vectorized	11.00
Front-end cycles	4.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	11.00
P6 cycles	11.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	32.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.27
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	256.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	67.74
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	90.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	18.18
Vector-efficiency ratio all	97.58
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	92.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..2#0x41ecb0
Source file and lines	build_field.cpp:119-128
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/build_field.cpp:119-128

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

67% of VPU instructions are used in vector version (process two or more data elements in vector registers):

90% of VPU addition or subtraction instructions are used in vector version.
18% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 256 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	11.00	11.00	4.00	4.00	4.00	4.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	11.00	11.00	4.00	4.00	4.00	4.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	4.00
Data deps.	2.00
Overall L1	11.00

Vectorization ratios

all	67%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	90%
fma	100%
div/sqrt	100%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

48% of peak store performance is reached (23.27 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41edcc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z20, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z20.D, P0/M, Z20.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z21, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z21.D, P0/M, Z20.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
SXTW Z21.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X23, X23, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
SXTW Z20.D, P0/M, Z20.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z20.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z18.D}, P0, [X9, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z20.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z18.D}, P0, [X11, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z20.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z18.D}, P0, [X13, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z20.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z18.D}, P0, [X15, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z20.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z18.D}, P0, [X17, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z20.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z18.D}, P0, [X2, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z20.D, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z18.D}, P0, [X0, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MAD Z20.D, P0/M, Z19.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z18.D}, P0, [X4, Z20.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41edcc <.omp_outlined..2+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..2#0x41ecb0
Source file and lines	build_field.cpp:119-128
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/build_field.cpp:119-128

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

67% of VPU instructions are used in vector version (process two or more data elements in vector registers):

90% of VPU addition or subtraction instructions are used in vector version.
18% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 256 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	11.00	11.00	4.00	4.00	4.00	4.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	11.00	11.00	4.00	4.00	4.00	4.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	4.00
Data deps.	2.00
Overall L1	11.00

Vectorization ratios

all	67%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	90%
fma	100%
div/sqrt	100%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

48% of peak store performance is reached (23.27 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41edcc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z20, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z20.D, P0/M, Z20.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z21, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z21.D, P0/M, Z20.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
SXTW Z21.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X23, X23, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
SXTW Z20.D, P0/M, Z20.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z20.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z18.D}, P0, [X9, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z20.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z18.D}, P0, [X11, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z20.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z18.D}, P0, [X13, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z20.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z18.D}, P0, [X15, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z20.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z18.D}, P0, [X17, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z20.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z18.D}, P0, [X2, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z22, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z22.D, P0/M, Z20.D, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z18.D}, P0, [X0, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MAD Z20.D, P0/M, Z19.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z18.D}, P0, [X4, Z20.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41edcc <.omp_outlined..2+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code