OV - exec - Loop 214

	Loop Id: 214	Module: exec	Source: generate_chunk.cpp:85-98 [...]	Coverage: 0.07%

0x422c80 MOVPRFX	Z21, Z0

0x422c84 SDIV	Z21.D, P0/M, Z21.D, Z2.D

0x422c88 MOVPRFX	Z22, Z0

0x422c8c MLS	Z22.D, P0/M, Z21.D, Z2.D

0x422c90 LSL	Z25.D, Z22.D, #32

0x422c94 ADD	X11, X20, X21,LSL #3

0x422c98 LD1RD	{Z24.D}, P0/Z, [X8]    [10]

0x422c9c ADD	Z0.D, Z0.D, Z1.D

0x422ca0 ADD	Z25.D, Z25.D, Z7.D

0x422ca4 LD1RD	{Z23.D}, P0/Z, [X11]    [14]

0x422ca8 LSL	Z26.D, Z21.D, #32

0x422cac ADD	Z26.D, Z26.D, Z7.D

0x422cb0 ASR	Z25.D, Z25.D, #-28

0x422cb4 ASR	Z26.D, Z26.D, #-28

0x422cb8 LD1D	{Z25.D}, P0/Z, [X2, Z25.D,LSL #3]    [27]

0x422cbc FCMGE	P1.D, P0/Z, Z25.D, Z23.D

0x422cc0 LD1D	{Z23.D}, P1/Z, [X2, Z22.D,SXTW #3]    [6]

0x422cc4 LD1D	{Z25.D}, P1/Z, [X5, Z17.D,LSL #3]    [1]

0x422cc8 SXTW	Z22.D, P0/M, Z22.D

0x422ccc FCMGT	P1.D, P1/Z, Z25.D, Z23.D

0x422cd0 MOVPRFX	Z25, Z21

0x422cd4 SXTW	Z25.D, P0/M, Z21.D

0x422cd8 LD1D	{Z23.D}, P1/Z, [X3, Z26.D,LSL #3]    [16]

0x422cdc FCMGE	P1.D, P1/Z, Z23.D, Z24.D

0x422ce0 LD1D	{Z23.D}, P1/Z, [X3, Z21.D,SXTW #3]    [13]

0x422ce4 LD1D	{Z24.D}, P1/Z, [X6, Z17.D,LSL #3]    [29]

0x422ce8 MSB	Z21.D, P0/M, Z2.D, Z19.D

0x422cec ADD	Z19.D, Z19.D, Z1.D

0x422cf0 FCMGT	P1.D, P1/Z, Z24.D, Z23.D

0x422cf4 MOVPRFX	Z24, Z22

0x422cf8 MLA	Z24.D, P0/M, Z25.D, Z3.D

0x422cfc LD1D	{Z23.D}, P1/Z, [X9, Z17.D,LSL #3]    [7]

0x422d00 ST1D	{Z23.D}, P1, [X10, Z24.D,LSL #3]    [20]

0x422d04 MOVPRFX	Z24, Z22

0x422d08 MLA	Z24.D, P0/M, Z25.D, Z4.D

0x422d0c LD1D	{Z23.D}, P1/Z, [X12, Z17.D,LSL #3]    [30]

0x422d10 ST1D	{Z23.D}, P1, [X13, Z24.D,LSL #3]    [18]

0x422d14 MOVPRFX	Z23, Z25

0x422d18 MUL	Z23.D, P0/M, Z23.D, Z5.D

0x422d1c ADR	Z23.D, [Z18, Z23.D,LSL #3]    [31]

0x422d20 MOVPRFX	Z24, Z25

0x422d24 MUL	Z24.D, P0/M, Z24.D, Z6.D

0x422d28 ADR	Z24.D, [Z20, Z24.D,LSL #3]    [8]

0x422d2c LD1D	{Z26.D}, P1/Z, [X15, Z17.D,LSL #3]    [17]

0x422d30 ADR	Z27.D, [Z23, Z21.D,SXTW #3]    [21]

0x422d34 ADR	Z28.D, [Z24, Z21.D,SXTW #3]    [25]

0x422d38 ST1D	{Z26.D}, P1, [V27.D]    [9]

0x422d3c MOVPRFX	Z26, Z21

0x422d40 SXTW	Z26.D, P0/M, Z21.D

0x422d44 CMPGE	P2.D, P1/Z, Z22.D, Z26.D

0x422d48 ADR	Z26.D, [Z16, Z21.D,SXTW #3]    [5]

0x422d4c SUBS	X25, X25, X23

0x422d50 LD1D	{Z27.D}, P1/Z, [X18, Z17.D,LSL #3]    [22]

0x422d54 ADD	Z23.D, Z23.D, Z26.D

0x422d58 ST1D	{Z27.D}, P1, [V28.D]    [28]

0x422d5c LD1D	{Z22.D}, P2/Z, [X15, Z17.D,LSL #3]    [17]

0x422d60 ST1D	{Z22.D}, P2, [V23.D]    [3]

0x422d64 ADD	Z23.D, Z24.D, Z26.D

0x422d68 LD1D	{Z22.D}, P2/Z, [X18, Z17.D,LSL #3]    [22]

0x422d6c ST1D	{Z22.D}, P2, [V23.D]    [4]

0x422d70 MOVPRFX	Z22, Z25

0x422d74 ADD	Z22.D, Z22.D, #1

0x422d78 MOVPRFX	Z23, Z22

0x422d7c MUL	Z23.D, P0/M, Z23.D, Z5.D

0x422d80 LD1D	{Z24.D}, P1/Z, [X15, Z17.D,LSL #3]    [17]

0x422d84 MUL	Z22.D, P0/M, Z22.D, Z6.D

0x422d88 ADR	Z23.D, [Z18, Z23.D,LSL #3]    [11]

0x422d8c ADR	Z25.D, [Z23, Z21.D,SXTW #3]    [19]

0x422d90 ADD	Z23.D, Z23.D, Z26.D

0x422d94 ST1D	{Z24.D}, P1, [V25.D]    [15]

0x422d98 LD1D	{Z24.D}, P1/Z, [X18, Z17.D,LSL #3]    [22]

0x422d9c ADR	Z22.D, [Z20, Z22.D,LSL #3]    [24]

0x422da0 ADR	Z21.D, [Z22, Z21.D,SXTW #3]    [26]

0x422da4 ADD	Z22.D, Z22.D, Z26.D

0x422da8 ST1D	{Z24.D}, P1, [V21.D]    [23]

0x422dac LD1D	{Z21.D}, P2/Z, [X15, Z17.D,LSL #3]    [17]

0x422db0 ST1D	{Z21.D}, P2, [V23.D]    [12]

0x422db4 LD1D	{Z21.D}, P2/Z, [X18, Z17.D,LSL #3]    [22]

0x422db8 ST1D	{Z21.D}, P2, [V22.D]    [2]

0x422dbc B.NE	422c80

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp: 85 - 98

--------------------------------------------------------------------------------

85: #pragma omp parallel for simd collapse(2)

86:     for (int j = (0); j < (yrange); j++) {

87:       for (int i = (0); i < (xrange); i++) {

88:         double x_cent = state_xmin[state];

89:         double y_cent = state_ymin[state];

90:         if (state_geometry[state] == g_rect) {

91:           if (field.vertexx[i + 1] >= state_xmin[state] && field.vertexx[i] < state_xmax[state]) {

92:             if (field.vertexy[j + 1] >= state_ymin[state] && field.vertexy[j] < state_ymax[state]) {

93:               field.energy0(i, j) = state_energy[state];

94:               field.density0(i, j) = state_density[state];

95:               for (int kt = j; kt <= j + 1; ++kt) {

96:                 for (int jt = i; jt <= i + 1; ++jt) {

97:                   field.xvel0(jt, kt) = state_xvel[state];

98:                   field.yvel0(jt, kt) = state_yvel[state];

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.16
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.75
Bottlenecks	P6, P7,
Function	.omp_outlined..2#0x422ac0
Source	context.h:69-69,generate_chunk.cpp:85-98
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	24.50
CQA cycles if no scalar integer	24.50
CQA cycles if FP arith vectorized	24.50
CQA cycles if fully vectorized	21.13
Front-end cycles	10.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	1.00
P4 cycles	0.50
P5 cycles	24.50
P6 cycles	24.50
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	14.00
P10 cycles	14.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	80.00
Nb uops	80.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	34.61
Bytes prefetched	0.00
Bytes loaded	528.00
Bytes stored	320.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	71.79
Vectorization ratio load	59.26
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	54.55
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	54.55
Vector-efficiency ratio all	88.46
Vector-efficiency ratio load	69.44
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	65.91
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.16
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.75
Bottlenecks	P6, P7,
Function	.omp_outlined..2#0x422ac0
Source	context.h:69-69,generate_chunk.cpp:85-98
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	24.50
CQA cycles if no scalar integer	24.50
CQA cycles if FP arith vectorized	24.50
CQA cycles if fully vectorized	21.13
Front-end cycles	10.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	1.00
P4 cycles	0.50
P5 cycles	24.50
P6 cycles	24.50
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	14.00
P10 cycles	14.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	80.00
Nb uops	80.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	34.61
Bytes prefetched	0.00
Bytes loaded	528.00
Bytes stored	320.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	71.79
Vectorization ratio load	59.26
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	54.55
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	54.55
Vector-efficiency ratio all	88.46
Vector-efficiency ratio load	69.44
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	65.91
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..2#0x422ac0
Source file and lines	generate_chunk.cpp:85-98
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp:85-98

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 88% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 24.50 to 21.12 cycles (1.16x speedup).

Details

71% of VPU instructions are used in vector version (process two or more data elements in vector registers):

59% of VPU loads are used in vector version.
54% of VPU addition or subtraction instructions are used in vector version.
54% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 528 bytes. The binary loop is storing 320 bytes.

General properties

nb instructions	80
loop length	320
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	1.00	0.50	24.50	24.50	5.00	5.00	14.00	14.00	0.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	1.00	0.50	24.50	24.50	5.00	5.00	14.00	14.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	10.00
Data deps.	2.00
Overall L1	24.50

Vectorization ratios

INT

all	70%
load	59%
store	100%
mul	100%
add-sub	54%
fma	100%
other	47%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	71%
load	59%
store	100%
mul	100%
add-sub	54%
fma	100%
div/sqrt	100%
other	54%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.50 cycles. At this rate:

22% of peak load performance is reached (21.55 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.06 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 422c80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z21, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z21.D, P0/M, Z21.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z22, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z22.D, P0/M, Z21.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LSL Z25.D, Z22.D, #32	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD X11, X20, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1RD {Z24.D}, P0/Z, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z25.D, Z25.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z23.D}, P0/Z, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LSL Z26.D, Z21.D, #32	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD Z26.D, Z26.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ASR Z25.D, Z25.D, #-28	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ASR Z26.D, Z26.D, #-28	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
LD1D {Z25.D}, P0/Z, [X2, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FCMGE P1.D, P0/Z, Z25.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
LD1D {Z23.D}, P1/Z, [X2, Z22.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P1/Z, [X5, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SXTW Z22.D, P0/M, Z22.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
FCMGT P1.D, P1/Z, Z25.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z25, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z25.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
LD1D {Z23.D}, P1/Z, [X3, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FCMGE P1.D, P1/Z, Z23.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
LD1D {Z23.D}, P1/Z, [X3, Z21.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P1/Z, [X6, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MSB Z21.D, P0/M, Z2.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z19.D, Z19.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P1.D, P1/Z, Z24.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z24, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z25.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z23.D}, P1/Z, [X9, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z23.D}, P1, [X10, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z24, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z25.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z23.D}, P1/Z, [X12, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z23.D}, P1, [X13, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z23, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z23.D, P0/M, Z23.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z23.D, [Z18, Z23.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z24, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z24.D, P0/M, Z24.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z24.D, [Z20, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z26.D}, P1/Z, [X15, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z27.D, [Z23, Z21.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z28.D, [Z24, Z21.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z26.D}, P1, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2
MOVPRFX Z26, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z26.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
CMPGE P2.D, P1/Z, Z22.D, Z26.D	1	0	0	0	0	1	0	1	0	0	0	0	0	4	1
ADR Z26.D, [Z16, Z21.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X25, X25, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
LD1D {Z27.D}, P1/Z, [X18, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD Z23.D, Z23.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z27.D}, P1, [V28.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2
LD1D {Z22.D}, P2/Z, [X15, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z22.D}, P2, [V23.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2
ADD Z23.D, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z22.D}, P2/Z, [X18, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z22.D}, P2, [V23.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2
MOVPRFX Z22, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z22.D, Z22.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z23, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z23.D, P0/M, Z23.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z24.D}, P1/Z, [X15, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MUL Z22.D, P0/M, Z22.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z23.D, [Z18, Z23.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z25.D, [Z23, Z21.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z23.D, Z23.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z24.D}, P1, [V25.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2
LD1D {Z24.D}, P1/Z, [X18, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z22.D, [Z20, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z21.D, [Z22, Z21.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z22.D, Z22.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z24.D}, P1, [V21.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2
LD1D {Z21.D}, P2/Z, [X15, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z21.D}, P2, [V23.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2
LD1D {Z21.D}, P2/Z, [X18, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z21.D}, P2, [V22.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2
B.NE 422c80 <.omp_outlined..2+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..2#0x422ac0
Source file and lines	generate_chunk.cpp:85-98
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp:85-98

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

71% of VPU instructions are used in vector version (process two or more data elements in vector registers):

59% of VPU loads are used in vector version.
54% of VPU addition or subtraction instructions are used in vector version.
54% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 528 bytes. The binary loop is storing 320 bytes.

General properties

nb instructions	80
loop length	320
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	1.00	0.50	24.50	24.50	5.00	5.00	14.00	14.00	0.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	1.00	0.50	24.50	24.50	5.00	5.00	14.00	14.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	10.00
Data deps.	2.00
Overall L1	24.50

Vectorization ratios

INT

all	70%
load	59%
store	100%
mul	100%
add-sub	54%
fma	100%
other	47%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	71%
load	59%
store	100%
mul	100%
add-sub	54%
fma	100%
div/sqrt	100%
other	54%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.50 cycles. At this rate:

22% of peak load performance is reached (21.55 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.06 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 422c80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z21, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z21.D, P0/M, Z21.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z22, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z22.D, P0/M, Z21.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LSL Z25.D, Z22.D, #32	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD X11, X20, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1RD {Z24.D}, P0/Z, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z25.D, Z25.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z23.D}, P0/Z, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LSL Z26.D, Z21.D, #32	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD Z26.D, Z26.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ASR Z25.D, Z25.D, #-28	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ASR Z26.D, Z26.D, #-28	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
LD1D {Z25.D}, P0/Z, [X2, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FCMGE P1.D, P0/Z, Z25.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
LD1D {Z23.D}, P1/Z, [X2, Z22.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P1/Z, [X5, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SXTW Z22.D, P0/M, Z22.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
FCMGT P1.D, P1/Z, Z25.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z25, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z25.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
LD1D {Z23.D}, P1/Z, [X3, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FCMGE P1.D, P1/Z, Z23.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
LD1D {Z23.D}, P1/Z, [X3, Z21.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P1/Z, [X6, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MSB Z21.D, P0/M, Z2.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z19.D, Z19.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P1.D, P1/Z, Z24.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z24, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z25.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z23.D}, P1/Z, [X9, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z23.D}, P1, [X10, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z24, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z25.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z23.D}, P1/Z, [X12, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z23.D}, P1, [X13, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z23, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z23.D, P0/M, Z23.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z23.D, [Z18, Z23.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z24, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z24.D, P0/M, Z24.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z24.D, [Z20, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z26.D}, P1/Z, [X15, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z27.D, [Z23, Z21.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z28.D, [Z24, Z21.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z26.D}, P1, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2
MOVPRFX Z26, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z26.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
CMPGE P2.D, P1/Z, Z22.D, Z26.D	1	0	0	0	0	1	0	1	0	0	0	0	0	4	1
ADR Z26.D, [Z16, Z21.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X25, X25, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
LD1D {Z27.D}, P1/Z, [X18, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD Z23.D, Z23.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z27.D}, P1, [V28.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2
LD1D {Z22.D}, P2/Z, [X15, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z22.D}, P2, [V23.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2
ADD Z23.D, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z22.D}, P2/Z, [X18, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z22.D}, P2, [V23.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2
MOVPRFX Z22, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z22.D, Z22.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z23, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z23.D, P0/M, Z23.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z24.D}, P1/Z, [X15, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MUL Z22.D, P0/M, Z22.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z23.D, [Z18, Z23.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z25.D, [Z23, Z21.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z23.D, Z23.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z24.D}, P1, [V25.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2
LD1D {Z24.D}, P1/Z, [X18, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z22.D, [Z20, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z21.D, [Z22, Z21.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z22.D, Z22.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z24.D}, P1, [V21.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2
LD1D {Z21.D}, P2/Z, [X15, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z21.D}, P2, [V23.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2
LD1D {Z21.D}, P2/Z, [X18, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z21.D}, P2, [V22.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2
B.NE 422c80 <.omp_outlined..2+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code