OV - exec - Loop 202

	Loop Id: 202	Module: exec	Source: PdV.cpp:69-83 [...]	Coverage: 5.97%

0x4280c0 SUB	X18, X29, #64

0x4280c4 MOVPRFX	Z31, Z0

0x4280c8 SDIV	Z31.D, P0/M, Z31.D, Z2.D

0x4280cc MOVPRFX	Z8, Z0

0x4280d0 MLS	Z8.D, P0/M, Z31.D, Z2.D

0x4280d4 SUBS	X13, X13, X11

0x4280d8 LDR	Z1, [X18, #510, MUL VL]    [14]

0x4280dc SUB	X18, X29, #64

0x4280e0 ADD	Z29.D, Z1.D, Z31.D

0x4280e4 LDR	Z1, [X18, #509, MUL VL]    [39]

0x4280e8 ADD	Z31.D, Z26.D, Z31.D

0x4280ec SUB	X18, X29, #64

0x4280f0 SXTW	Z29.D, P0/M, Z29.D

0x4280f4 MOVPRFX	Z10, Z5

0x4280f8 MUL	Z10.D, P0/M, Z10.D, Z29.D

0x4280fc MOVPRFX	Z12, Z6

0x428100 MUL	Z12.D, P0/M, Z12.D, Z29.D

0x428104 SXTW	Z31.D, P0/M, Z31.D

0x428108 MOVPRFX	Z14, Z6

0x42810c MUL	Z14.D, P0/M, Z14.D, Z31.D

0x428110 ADD	Z9.D, Z1.D, Z8.D

0x428114 MOVPRFX	Z1, Z7

0x428118 MUL	Z1.D, P0/M, Z1.D, Z31.D

0x42811c ADD	Z8.D, Z28.D, Z8.D

0x428120 MOVPRFX	Z30, Z9

0x428124 SXTW	Z30.D, P0/M, Z9.D

0x428128 ADR	Z11.D, [Z10, Z9.D,SXTW]    [26]

0x42812c ADR	Z13.D, [Z12, Z9.D,SXTW]    [12]

0x428130 ADR	Z15.D, [Z14, Z9.D,SXTW]    [40]

0x428134 ADR	Z3.D, [Z1, Z9.D,SXTW]    [35]

0x428138 ADR	Z1.D, [Z1, Z8.D,SXTW]    [48]

0x42813c LD1D	{Z11.D}, P0/Z, [X23, Z11.D,LSL #3]    [22]

0x428140 LD1D	{Z13.D}, P0/Z, [X25, Z13.D,LSL #3]    [44]

0x428144 LD1D	{Z15.D}, P0/Z, [X25, Z15.D,LSL #3]    [47]

0x428148 FADD	Z13.D, Z15.D, Z13.D

0x42814c MOVPRFX	Z15, Z7

0x428150 MUL	Z15.D, P0/M, Z15.D, Z29.D

0x428154 ADR	Z27.D, [Z15, Z9.D,SXTW]    [6]

0x428158 LD1D	{Z27.D}, P0/Z, [X27, Z27.D,LSL #3]    [49]

0x42815c LD1D	{Z3.D}, P0/Z, [X27, Z3.D,LSL #3]    [4]

0x428160 LDR	D4, [X6]    [27]

0x428164 FADD	Z3.D, Z27.D, Z3.D

0x428168 ADR	Z27.D, [Z10, Z8.D,SXTW]    [38]

0x42816c ADR	Z10.D, [Z12, Z8.D,SXTW]    [21]

0x428170 ADR	Z12.D, [Z14, Z8.D,SXTW]    [7]

0x428174 LD1D	{Z27.D}, P0/Z, [X23, Z27.D,LSL #3]    [2]

0x428178 LD1D	{Z10.D}, P0/Z, [X25, Z10.D,LSL #3]    [25]

0x42817c LD1D	{Z12.D}, P0/Z, [X25, Z12.D,LSL #3]    [10]

0x428180 FADD	Z3.D, Z13.D, Z3.D

0x428184 MOVPRFX	Z13, Z17

0x428188 MUL	Z13.D, P0/M, Z13.D, Z29.D

0x42818c ADR	Z14.D, [Z13, Z9.D,SXTW]    [9]

0x428190 ADR	Z13.D, [Z13, Z8.D,SXTW]    [19]

0x428194 FMUL	Z3.D, Z3.D, Z11.D

0x428198 FADD	Z10.D, Z12.D, Z10.D

0x42819c ADR	Z12.D, [Z15, Z8.D,SXTW]    [16]

0x4281a0 LD1D	{Z12.D}, P0/Z, [X27, Z12.D,LSL #3]    [32]

0x4281a4 LD1D	{Z1.D}, P0/Z, [X27, Z1.D,LSL #3]    [5]

0x4281a8 FADD	Z1.D, Z12.D, Z1.D

0x4281ac MOVPRFX	Z12, Z30

0x4281b0 MLA	Z12.D, P0/M, Z16.D, Z29.D

0x4281b4 LD1D	{Z12.D}, P0/Z, [X19, Z12.D,LSL #3]    [30]

0x4281b8 LD1D	{Z14.D}, P0/Z, [X20, Z14.D,LSL #3]    [23]

0x4281bc FADD	Z1.D, Z10.D, Z1.D

0x4281c0 LD1D	{Z10.D}, P0/Z, [X20, Z13.D,LSL #3]    [3]

0x4281c4 MOVPRFX	Z13, Z18

0x4281c8 MUL	Z13.D, P0/M, Z13.D, Z29.D

0x4281cc FMUL	Z1.D, Z1.D, Z27.D

0x4281d0 FADD	Z10.D, Z10.D, Z14.D

0x4281d4 ADR	Z14.D, [Z13, Z9.D,SXTW]    [13]

0x4281d8 ADR	Z13.D, [Z13, Z8.D,SXTW]    [24]

0x4281dc LD1D	{Z14.D}, P0/Z, [X24, Z14.D,LSL #3]    [8]

0x4281e0 LD1D	{Z13.D}, P0/Z, [X24, Z13.D,LSL #3]    [29]

0x4281e4 FADD	Z13.D, Z14.D, Z13.D

0x4281e8 MOVPRFX	Z14, Z30

0x4281ec MLA	Z14.D, P0/M, Z16.D, Z31.D

0x4281f0 LD1D	{Z27.D}, P0/Z, [X19, Z14.D,LSL #3]    [37]

0x4281f4 MOVPRFX	Z14, Z17

0x4281f8 MUL	Z14.D, P0/M, Z14.D, Z31.D

0x4281fc MUL	Z31.D, P0/M, Z31.D, Z18.D

0x428200 ADR	Z15.D, [Z14, Z9.D,SXTW]    [33]

0x428204 ADR	Z14.D, [Z14, Z8.D,SXTW]    [46]

0x428208 LD1D	{Z15.D}, P0/Z, [X20, Z15.D,LSL #3]    [1]

0x42820c LD1D	{Z14.D}, P0/Z, [X20, Z14.D,LSL #3]    [42]

0x428210 FADD	Z10.D, Z10.D, Z13.D

0x428214 FMLA	Z3.D, P0/M, Z10.D, Z12.D

0x428218 ADR	Z9.D, [Z31, Z9.D,SXTW]    [17]

0x42821c ADR	Z31.D, [Z31, Z8.D,SXTW]    [28]

0x428220 FADD	Z14.D, Z14.D, Z15.D

0x428224 LD1D	{Z8.D}, P0/Z, [X24, Z9.D,LSL #3]    [15]

0x428228 LD1D	{Z31.D}, P0/Z, [X24, Z31.D,LSL #3]    [43]

0x42822c MOVPRFX	Z9, Z30

0x428230 MLA	Z9.D, P0/M, Z22.D, Z29.D

0x428234 FADD	Z31.D, Z8.D, Z31.D

0x428238 FADD	Z31.D, Z14.D, Z31.D

0x42823c FMLA	Z1.D, P0/M, Z31.D, Z27.D

0x428240 FMOV	D27, #0.2500000

0x428244 MOVPRFX	Z31, Z30

0x428248 MLA	Z31.D, P0/M, Z21.D, Z29.D

0x42824c FMUL	D4, D4, D27

0x428250 MOVPRFX	Z27, Z30

0x428254 MLA	Z27.D, P0/M, Z20.D, Z29.D

0x428258 FSUB	Z1.D, Z1.D, Z3.D

0x42825c DUP	Z3.D, Z4.D[0]

0x428260 MOVPRFX	Z4, Z30

0x428264 MLA	Z4.D, P0/M, Z19.D, Z29.D

0x428268 LD1D	{Z4.D}, P0/Z, [X8, Z4.D,LSL #3]    [36]

0x42826c LD1D	{Z27.D}, P0/Z, [X9, Z27.D,LSL #3]    [18]

0x428270 LD1D	{Z8.D}, P0/Z, [X26, Z31.D,LSL #3]    [45]

0x428274 LD1D	{Z9.D}, P0/Z, [X14, Z9.D,LSL #3]    [20]

0x428278 FMUL	Z1.D, Z3.D, Z1.D

0x42827c FADD	Z3.D, Z9.D, Z27.D

0x428280 FMUL	Z27.D, Z8.D, Z4.D

0x428284 FMUL	Z3.D, Z3.D, Z1.D

0x428288 FADD	Z1.D, Z1.D, Z4.D

0x42828c FDIV	Z3.D, P0/M, Z3.D, Z27.D

0x428290 MOVPRFX	Z27, Z30

0x428294 MLA	Z27.D, P0/M, Z23.D, Z29.D

0x428298 LD1D	{Z27.D}, P0/Z, [X16, Z27.D,LSL #3]    [31]

0x42829c FSUB	Z3.D, Z27.D, Z3.D

0x4282a0 MOVPRFX	Z27, Z30

0x4282a4 MLA	Z27.D, P0/M, Z24.D, Z29.D

0x4282a8 ST1D	{Z3.D}, P0, [X15, Z27.D,LSL #3]    [34]

0x4282ac LD1D	{Z3.D}, P0/Z, [X26, Z31.D,LSL #3]    [45]

0x4282b0 FMUL	Z3.D, Z3.D, Z4.D

0x4282b4 LDR	Z4, [X18, #511, MUL VL]    [11]

0x4282b8 FDIVR	Z1.D, P0/M, Z1.D, Z3.D

0x4282bc MOVPRFX	Z3, Z30

0x4282c0 MLA	Z3.D, P0/M, Z25.D, Z29.D

0x4282c4 ADD	Z0.D, Z0.D, Z4.D

0x4282c8 ST1D	{Z1.D}, P0, [X17, Z3.D,LSL #3]    [41]

0x4282cc B.NE	4280c0

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp: 69 - 83

--------------------------------------------------------------------------------

69: #pragma omp parallel for simd collapse(2)

70:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

71:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

72:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1))) * 0.25 * dt;

73:         double right_flux =

74:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel1(i + 1, j + 0) + xvel1(i + 1, j + 1))) * 0.25 * dt;

75:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0))) * 0.25 * dt;

76:         double top_flux =

77:             (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel1(i + 0, j + 1) + yvel1(i + 1, j + 1))) * 0.25 * dt;

78:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

79:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

80:         double recip_volume = 1.0 / volume(i, j);

81:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

82:         energy1(i, j) = energy0(i, j) - energy_change;

83:         density1(i, j) = density0(i, j) * volume_change_s;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.17
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.82
Bottlenecks	P6, P7,
Function	.omp_outlined..2#0x427e60
Source	context.h:69-69,PdV.cpp:69-83
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	46.50
CQA cycles if no scalar integer	46.50
CQA cycles if FP arith vectorized	46.50
CQA cycles if fully vectorized	39.75
Front-end cycles	16.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	46.50
P6 cycles	46.50
P7 cycles	12.25
P8 cycles	12.25
P9 cycles	15.50
P10 cycles	15.50
P11 cycles	1.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	3.00 - 1.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	132.00
Nb uops	132.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.43
Nb FLOP add-sub	64.00
Nb FLOP mul	25.00
Nb FLOP fma	8.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.51
Bytes prefetched	0.00
Bytes loaded	936.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	68.25
Vectorization ratio load	60.42
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	62.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	16.67
Vector-efficiency ratio all	88.10
Vector-efficiency ratio load	70.31
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	71.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.17
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.82
Bottlenecks	P6, P7,
Function	.omp_outlined..2#0x427e60
Source	context.h:69-69,PdV.cpp:69-83
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	46.50
CQA cycles if no scalar integer	46.50
CQA cycles if FP arith vectorized	46.50
CQA cycles if fully vectorized	39.75
Front-end cycles	16.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	46.50
P6 cycles	46.50
P7 cycles	12.25
P8 cycles	12.25
P9 cycles	15.50
P10 cycles	15.50
P11 cycles	1.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	3.00 - 1.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	132.00
Nb uops	132.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.43
Nb FLOP add-sub	64.00
Nb FLOP mul	25.00
Nb FLOP fma	8.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.51
Bytes prefetched	0.00
Bytes loaded	936.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	68.25
Vectorization ratio load	60.42
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	62.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	16.67
Vector-efficiency ratio all	88.10
Vector-efficiency ratio load	70.31
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	71.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..2#0x427e60
Source file and lines	PdV.cpp:69-83
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:69-83

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 88% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 46.50 to 39.75 cycles (1.17x speedup).

Details

68% of VPU instructions are used in vector version (process two or more data elements in vector registers):

60% of VPU loads are used in vector version.
62% of VPU addition or subtraction instructions are used in vector version.
16% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 113 FP arithmetical operations:

72: addition or subtraction (8 inside FMA instructions)
33: multiply (8 inside FMA instructions)
8: divide

The binary loop is loading 936 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	132
loop length	528
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

16.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.00	1.00	1.00	1.00	46.50	46.50	2.00	2.00	15.50	15.50	1.00	0.00	0.00
cycles	0.50	0.50	1.00	1.00	1.00	1.00	46.50	46.50	12.25	12.25	15.50	15.50	1.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	3.00-1.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	16.50
Data deps.	2.00
Overall L1	46.50

Vectorization ratios

INT

all	60%
load	60%
store	100%
mul	100%
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	68%
load	60%
store	100%
mul	100%
add-sub	62%
fma	100%
div/sqrt	100%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 46.50 cycles. At this rate:

20% of peak load performance is reached (20.13 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.38 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4280c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
SUB X18, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVPRFX Z31, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SDIV Z31.D, P0/M, Z31.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z8, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLS Z8.D, P0/M, Z31.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
SUBS X13, X13, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDR Z1, [X18, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
SUB X18, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD Z29.D, Z1.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LDR Z1, [X18, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD Z31.D, Z26.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SUB X18, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SXTW Z29.D, P0/M, Z29.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z10, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z10.D, P0/M, Z10.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
MOVPRFX Z12, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z12.D, P0/M, Z12.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
SXTW Z31.D, P0/M, Z31.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z14, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z14.D, P0/M, Z14.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADD Z9.D, Z1.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z1, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z1.D, P0/M, Z1.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADD Z8.D, Z28.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z30, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SXTW Z30.D, P0/M, Z9.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
ADR Z11.D, [Z10, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z13.D, [Z12, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z15.D, [Z14, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z3.D, [Z1, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z1.D, [Z1, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z11.D}, P0/Z, [X23, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z13.D}, P0/Z, [X25, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z15.D}, P0/Z, [X25, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z13.D, Z15.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z15, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z15.D, P0/M, Z15.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADR Z27.D, [Z15, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z27.D}, P0/Z, [X27, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z3.D}, P0/Z, [X27, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LDR D4, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD Z3.D, Z27.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z27.D, [Z10, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z10.D, [Z12, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z12.D, [Z14, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z27.D}, P0/Z, [X23, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z10.D}, P0/Z, [X25, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z12.D}, P0/Z, [X25, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z3.D, Z13.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z13, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z13.D, P0/M, Z13.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADR Z14.D, [Z13, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z13.D, [Z13, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z3.D, Z3.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FADD Z10.D, Z12.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z12.D, [Z15, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z12.D}, P0/Z, [X27, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z1.D}, P0/Z, [X27, Z1.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z1.D, Z12.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z12, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z12.D, P0/M, Z16.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z12.D}, P0/Z, [X19, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z14.D}, P0/Z, [X20, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z1.D, Z10.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z10.D}, P0/Z, [X20, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
MOVPRFX Z13, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z13.D, P0/M, Z13.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
FMUL Z1.D, Z1.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FADD Z10.D, Z10.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z14.D, [Z13, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z13.D, [Z13, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z14.D}, P0/Z, [X24, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z13.D}, P0/Z, [X24, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z13.D, Z14.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z14, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z14.D, P0/M, Z16.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z27.D}, P0/Z, [X19, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
MOVPRFX Z14, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z14.D, P0/M, Z14.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
MUL Z31.D, P0/M, Z31.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADR Z15.D, [Z14, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z14.D, [Z14, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z15.D}, P0/Z, [X20, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z14.D}, P0/Z, [X20, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z10.D, Z10.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMLA Z3.D, P0/M, Z10.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
ADR Z9.D, [Z31, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z31.D, [Z31, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FADD Z14.D, Z14.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z8.D}, P0/Z, [X24, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z31.D}, P0/Z, [X24, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
MOVPRFX Z9, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z9.D, P0/M, Z22.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
FADD Z31.D, Z8.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FADD Z31.D, Z14.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMLA Z1.D, P0/M, Z31.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FMOV D27, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
MOVPRFX Z31, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z31.D, P0/M, Z21.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
FMUL D4, D4, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
MOVPRFX Z27, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z27.D, P0/M, Z20.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
FSUB Z1.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
DUP Z3.D, Z4.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z4, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z4.D, P0/M, Z19.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z4.D}, P0/Z, [X8, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z27.D}, P0/Z, [X9, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z8.D}, P0/Z, [X26, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z9.D}, P0/Z, [X14, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FMUL Z1.D, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FADD Z3.D, Z9.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z27.D, Z8.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z3.D, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FADD Z1.D, Z1.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FDIV Z3.D, P0/M, Z3.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z27, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z27.D, P0/M, Z23.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z27.D}, P0/Z, [X16, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FSUB Z3.D, Z27.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z27, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z27.D, P0/M, Z24.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ST1D {Z3.D}, P0, [X15, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
LD1D {Z3.D}, P0/Z, [X26, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FMUL Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
LDR Z4, [X18, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FDIVR Z1.D, P0/M, Z1.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z3, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z3.D, P0/M, Z25.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADD Z0.D, Z0.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ST1D {Z1.D}, P0, [X17, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
B.NE 4280c0 <.omp_outlined..2+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..2#0x427e60
Source file and lines	PdV.cpp:69-83
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:69-83

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

68% of VPU instructions are used in vector version (process two or more data elements in vector registers):

60% of VPU loads are used in vector version.
62% of VPU addition or subtraction instructions are used in vector version.
16% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 113 FP arithmetical operations:

72: addition or subtraction (8 inside FMA instructions)
33: multiply (8 inside FMA instructions)
8: divide

The binary loop is loading 936 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	132
loop length	528
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

16.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.00	1.00	1.00	1.00	46.50	46.50	2.00	2.00	15.50	15.50	1.00	0.00	0.00
cycles	0.50	0.50	1.00	1.00	1.00	1.00	46.50	46.50	12.25	12.25	15.50	15.50	1.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	3.00-1.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	16.50
Data deps.	2.00
Overall L1	46.50

Vectorization ratios

INT

all	60%
load	60%
store	100%
mul	100%
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	68%
load	60%
store	100%
mul	100%
add-sub	62%
fma	100%
div/sqrt	100%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 46.50 cycles. At this rate:

20% of peak load performance is reached (20.13 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.38 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4280c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
SUB X18, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVPRFX Z31, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SDIV Z31.D, P0/M, Z31.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z8, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLS Z8.D, P0/M, Z31.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
SUBS X13, X13, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDR Z1, [X18, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
SUB X18, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD Z29.D, Z1.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LDR Z1, [X18, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
ADD Z31.D, Z26.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SUB X18, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SXTW Z29.D, P0/M, Z29.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z10, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z10.D, P0/M, Z10.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
MOVPRFX Z12, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z12.D, P0/M, Z12.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
SXTW Z31.D, P0/M, Z31.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z14, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z14.D, P0/M, Z14.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADD Z9.D, Z1.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z1, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z1.D, P0/M, Z1.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADD Z8.D, Z28.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z30, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SXTW Z30.D, P0/M, Z9.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
ADR Z11.D, [Z10, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z13.D, [Z12, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z15.D, [Z14, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z3.D, [Z1, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z1.D, [Z1, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z11.D}, P0/Z, [X23, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z13.D}, P0/Z, [X25, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z15.D}, P0/Z, [X25, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z13.D, Z15.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z15, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z15.D, P0/M, Z15.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADR Z27.D, [Z15, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z27.D}, P0/Z, [X27, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z3.D}, P0/Z, [X27, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LDR D4, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD Z3.D, Z27.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z27.D, [Z10, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z10.D, [Z12, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z12.D, [Z14, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z27.D}, P0/Z, [X23, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z10.D}, P0/Z, [X25, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z12.D}, P0/Z, [X25, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z3.D, Z13.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z13, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z13.D, P0/M, Z13.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADR Z14.D, [Z13, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z13.D, [Z13, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z3.D, Z3.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FADD Z10.D, Z12.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z12.D, [Z15, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z12.D}, P0/Z, [X27, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z1.D}, P0/Z, [X27, Z1.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z1.D, Z12.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z12, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z12.D, P0/M, Z16.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z12.D}, P0/Z, [X19, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z14.D}, P0/Z, [X20, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z1.D, Z10.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z10.D}, P0/Z, [X20, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
MOVPRFX Z13, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z13.D, P0/M, Z13.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
FMUL Z1.D, Z1.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FADD Z10.D, Z10.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z14.D, [Z13, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z13.D, [Z13, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z14.D}, P0/Z, [X24, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z13.D}, P0/Z, [X24, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z13.D, Z14.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z14, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z14.D, P0/M, Z16.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z27.D}, P0/Z, [X19, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
MOVPRFX Z14, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z14.D, P0/M, Z14.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
MUL Z31.D, P0/M, Z31.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADR Z15.D, [Z14, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z14.D, [Z14, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z15.D}, P0/Z, [X20, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z14.D}, P0/Z, [X20, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z10.D, Z10.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMLA Z3.D, P0/M, Z10.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
ADR Z9.D, [Z31, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z31.D, [Z31, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FADD Z14.D, Z14.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LD1D {Z8.D}, P0/Z, [X24, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z31.D}, P0/Z, [X24, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
MOVPRFX Z9, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z9.D, P0/M, Z22.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
FADD Z31.D, Z8.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FADD Z31.D, Z14.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMLA Z1.D, P0/M, Z31.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FMOV D27, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
MOVPRFX Z31, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z31.D, P0/M, Z21.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
FMUL D4, D4, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
MOVPRFX Z27, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z27.D, P0/M, Z20.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
FSUB Z1.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
DUP Z3.D, Z4.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z4, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z4.D, P0/M, Z19.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z4.D}, P0/Z, [X8, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z27.D}, P0/Z, [X9, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z8.D}, P0/Z, [X26, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z9.D}, P0/Z, [X14, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FMUL Z1.D, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FADD Z3.D, Z9.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z27.D, Z8.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z3.D, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FADD Z1.D, Z1.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FDIV Z3.D, P0/M, Z3.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z27, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z27.D, P0/M, Z23.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z27.D}, P0/Z, [X16, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FSUB Z3.D, Z27.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z27, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z27.D, P0/M, Z24.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ST1D {Z3.D}, P0, [X15, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
LD1D {Z3.D}, P0/Z, [X26, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FMUL Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
LDR Z4, [X18, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FDIVR Z1.D, P0/M, Z1.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z3, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z3.D, P0/M, Z25.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADD Z0.D, Z0.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ST1D {Z1.D}, P0, [X17, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
B.NE 4280c0 <.omp_outlined..2+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code