OV - exec - Loop 200

0x428c8c MOVPRFX	Z17, Z0

0x428c90 SDIV	Z17.D, P0/M, Z17.D, Z2.D

0x428c94 ADD	Z18.D, Z3.D, Z17.D

0x428c98 MSB	Z17.D, P0/M, Z2.D, Z0.D

0x428c9c ADD	Z0.D, Z0.D, Z1.D

0x428ca0 SUBS	X12, X12, X10

0x428ca4 SXTW	Z18.D, P0/M, Z18.D

0x428ca8 ADD	Z17.D, Z4.D, Z17.D

0x428cac SXTW	Z17.D, P0/M, Z17.D

0x428cb0 MOVPRFX	Z19, Z17

0x428cb4 MLA	Z19.D, P0/M, Z5.D, Z18.D

0x428cb8 LD1D	{Z19.D}, P0/Z, [X25, Z19.D,LSL #3]    [1]

0x428cbc MOVPRFX	Z20, Z17

0x428cc0 MLA	Z20.D, P0/M, Z6.D, Z18.D

0x428cc4 ST1D	{Z19.D}, P0, [X23, Z20.D,LSL #3]    [2]

0x428cc8 MOVPRFX	Z19, Z17

0x428ccc MLA	Z19.D, P0/M, Z7.D, Z18.D

0x428cd0 MLA	Z17.D, P0/M, Z16.D, Z18.D

0x428cd4 LD1D	{Z19.D}, P0/Z, [X19, Z19.D,LSL #3]    [4]

0x428cd8 ST1D	{Z19.D}, P0, [X27, Z17.D,LSL #3]    [3]

0x428cdc B.NE	428c8c

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/reset_field.cpp: 45 - 48

--------------------------------------------------------------------------------

45:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

46:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

47:       xvel0(i, j) = xvel1(i, j);

48:       yvel0(i, j) = yvel1(i, j);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.86
Bottlenecks	P6, P7,
Function	.omp_outlined..2#0x428b60
Source	context.h:69-69,reset_field.cpp:45-48
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	7.50
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	7.50
CQA cycles if fully vectorized	7.50
Front-end cycles	2.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	7.50
P6 cycles	7.50
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.07
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	75.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	87.50
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	33.33
Vector-efficiency ratio all	96.25
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	90.63
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.86
Bottlenecks	P6, P7,
Function	.omp_outlined..2#0x428b60
Source	context.h:69-69,reset_field.cpp:45-48
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	7.50
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	7.50
CQA cycles if fully vectorized	7.50
Front-end cycles	2.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	7.50
P6 cycles	7.50
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.07
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	75.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	87.50
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	33.33
Vector-efficiency ratio all	96.25
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	90.63
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..2#0x428b60
Source file and lines	reset_field.cpp:45-48
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/reset_field.cpp:45-48

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 96% of vector register length is used (average across all VPU instructions).

Details

75% of VPU instructions are used in vector version (process two or more data elements in vector registers):

87% of VPU addition or subtraction instructions are used in vector version.
33% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	7.50	7.50	1.00	1.00	2.00	2.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	7.50	7.50	1.00	1.00	2.00	2.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	2.63
Data deps.	2.00
Overall L1	7.50

Vectorization ratios

all	75%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	87%
fma	100%
div/sqrt	100%
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.50 cycles. At this rate:

8% of peak load performance is reached (8.53 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 428c8c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z17, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z17.D, P0/M, Z17.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z18.D, Z3.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MSB Z17.D, P0/M, Z2.D, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
SXTW Z18.D, P0/M, Z18.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD Z17.D, Z4.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z17.D, P0/M, Z17.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z19, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z19.D, P0/M, Z5.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z19.D}, P0/Z, [X25, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z20, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z20.D, P0/M, Z6.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z19.D}, P0, [X23, Z20.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z19, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z19.D, P0/M, Z7.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MLA Z17.D, P0/M, Z16.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z19.D}, P0/Z, [X19, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z19.D}, P0, [X27, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 428c8c <.omp_outlined..2+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..2#0x428b60
Source file and lines	reset_field.cpp:45-48
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/reset_field.cpp:45-48

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 96% of vector register length is used (average across all VPU instructions).

Details

75% of VPU instructions are used in vector version (process two or more data elements in vector registers):

87% of VPU addition or subtraction instructions are used in vector version.
33% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	7.50	7.50	1.00	1.00	2.00	2.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	7.50	7.50	1.00	1.00	2.00	2.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	2.63
Data deps.	2.00
Overall L1	7.50

Vectorization ratios

all	75%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	87%
fma	100%
div/sqrt	100%
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.50 cycles. At this rate:

8% of peak load performance is reached (8.53 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 428c8c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z17, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z17.D, P0/M, Z17.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z18.D, Z3.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MSB Z17.D, P0/M, Z2.D, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
SXTW Z18.D, P0/M, Z18.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD Z17.D, Z4.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z17.D, P0/M, Z17.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z19, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z19.D, P0/M, Z5.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z19.D}, P0/Z, [X25, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z20, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z20.D, P0/M, Z6.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z19.D}, P0, [X23, Z20.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z19, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z19.D, P0/M, Z7.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MLA Z17.D, P0/M, Z16.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z19.D}, P0/Z, [X19, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z19.D}, P0, [X27, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 428c8c <.omp_outlined..2+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code