OV - exec - Loop 184

	Loop Id: 184	Module: exec	Source: build_field.cpp:101-113 [...]	Coverage: 0.05%

0x41eae0 MOVPRFX	Z23, Z0

0x41eae4 SDIV	Z23.D, P0/M, Z23.D, Z2.D

0x41eae8 MOVPRFX	Z24, Z0

0x41eaec MLS	Z24.D, P0/M, Z23.D, Z2.D

0x41eaf0 SXTW	Z24.D, P0/M, Z24.D

0x41eaf4 ADD	Z0.D, Z0.D, Z1.D

0x41eaf8 SUBS	X30, X30, X26

0x41eafc SXTW	Z23.D, P0/M, Z23.D

0x41eb00 MOVPRFX	Z25, Z24

0x41eb04 MLA	Z25.D, P0/M, Z23.D, Z3.D

0x41eb08 ST1D	{Z21.D}, P0, [X9, Z25.D,LSL #3]    [1]

0x41eb0c MOVPRFX	Z25, Z24

0x41eb10 MLA	Z25.D, P0/M, Z23.D, Z4.D

0x41eb14 ST1D	{Z21.D}, P0, [X11, Z25.D,LSL #3]    [6]

0x41eb18 MOVPRFX	Z25, Z24

0x41eb1c MLA	Z25.D, P0/M, Z23.D, Z5.D

0x41eb20 ST1D	{Z21.D}, P0, [X13, Z25.D,LSL #3]    [5]

0x41eb24 MOVPRFX	Z25, Z24

0x41eb28 MLA	Z25.D, P0/M, Z23.D, Z6.D

0x41eb2c ST1D	{Z21.D}, P0, [X15, Z25.D,LSL #3]    [8]

0x41eb30 MOVPRFX	Z25, Z24

0x41eb34 MLA	Z25.D, P0/M, Z23.D, Z7.D

0x41eb38 ST1D	{Z21.D}, P0, [X17, Z25.D,LSL #3]    [11]

0x41eb3c MOVPRFX	Z25, Z24

0x41eb40 MLA	Z25.D, P0/M, Z23.D, Z16.D

0x41eb44 ST1D	{Z21.D}, P0, [X1, Z25.D,LSL #3]    [9]

0x41eb48 MOVPRFX	Z25, Z24

0x41eb4c MLA	Z25.D, P0/M, Z23.D, Z17.D

0x41eb50 ST1D	{Z21.D}, P0, [X0, Z25.D,LSL #3]    [3]

0x41eb54 MOVPRFX	Z25, Z24

0x41eb58 MLA	Z25.D, P0/M, Z23.D, Z18.D

0x41eb5c ST1D	{Z21.D}, P0, [X4, Z25.D,LSL #3]    [10]

0x41eb60 MOVPRFX	Z25, Z24

0x41eb64 MLA	Z25.D, P0/M, Z23.D, Z19.D

0x41eb68 ST1D	{Z21.D}, P0, [X6, Z25.D,LSL #3]    [7]

0x41eb6c MOVPRFX	Z25, Z24

0x41eb70 MLA	Z25.D, P0/M, Z23.D, Z20.D

0x41eb74 ST1D	{Z21.D}, P0, [X24, Z25.D,LSL #3]    [4]

0x41eb78 MAD	Z23.D, P0/M, Z22.D, Z24.D

0x41eb7c ST1D	{Z21.D}, P0, [X23, Z23.D,LSL #3]    [2]

0x41eb80 B.NE	41eae0

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/build_field.cpp: 101 - 113

--------------------------------------------------------------------------------

101:     for (int j = (0); j < (yrange + 1); j++) {

102:       for (int i = (0); i < (xrange + 1); i++) {

103:         field.work_array1(i, j) = 0.0;

104:         field.work_array2(i, j) = 0.0;

105:         field.work_array3(i, j) = 0.0;

106:         field.work_array4(i, j) = 0.0;

107:         field.work_array5(i, j) = 0.0;

108:         field.work_array6(i, j) = 0.0;

109:         field.work_array7(i, j) = 0.0;

110:         field.xvel0(i, j) = 0.0;

111:         field.xvel1(i, j) = 0.0;

112:         field.yvel0(i, j) = 0.0;

113:         field.yvel1(i, j) = 0.0;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.55
Bottlenecks	P6, P7,
Function	.omp_outlined.#0x41e9a0
Source	context.h:69-69,build_field.cpp:101-113
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	14.00
CQA cycles if no scalar integer	14.00
CQA cycles if FP arith vectorized	14.00
CQA cycles if fully vectorized	14.00
Front-end cycles	5.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	14.00
P6 cycles	14.00
P7 cycles	5.50
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	5.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	41.00
Nb uops	41.00
Nb loads	NA
Nb stores	11.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.14
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	352.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	67.50
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	92.31
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	14.29
Vector-efficiency ratio all	98.13
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	94.23
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.55
Bottlenecks	P6, P7,
Function	.omp_outlined.#0x41e9a0
Source	context.h:69-69,build_field.cpp:101-113
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	14.00
CQA cycles if no scalar integer	14.00
CQA cycles if FP arith vectorized	14.00
CQA cycles if fully vectorized	14.00
Front-end cycles	5.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	14.00
P6 cycles	14.00
P7 cycles	5.50
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	5.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	41.00
Nb uops	41.00
Nb loads	NA
Nb stores	11.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.14
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	352.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	67.50
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	92.31
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	14.29
Vector-efficiency ratio all	98.13
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	94.23
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x41e9a0
Source file and lines	build_field.cpp:101-113
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/build_field.cpp:101-113

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

67% of VPU instructions are used in vector version (process two or more data elements in vector registers):

92% of VPU addition or subtraction instructions are used in vector version.
14% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 352 bytes.

General properties

nb instructions	41
loop length	164
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	14.00	14.00	5.50	5.50	5.50	5.50	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	14.00	14.00	5.50	5.50	5.50	5.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	5.13
Data deps.	2.00
Overall L1	14.00

Vectorization ratios

all	67%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	92%
fma	100%
div/sqrt	100%
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

52% of peak store performance is reached (25.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41eae0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z23, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z23.D, P0/M, Z23.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z24, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z24.D, P0/M, Z23.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
SXTW Z24.D, P0/M, Z24.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X30, X30, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
SXTW Z23.D, P0/M, Z23.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z23.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X9, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z23.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X11, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z23.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X13, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z23.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X15, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z23.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X17, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z23.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X1, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z23.D, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X0, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z23.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X4, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z23.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X6, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z23.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X24, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MAD Z23.D, P0/M, Z22.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X23, Z23.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41eae0 <.omp_outlined.+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.#0x41e9a0
Source file and lines	build_field.cpp:101-113
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/build_field.cpp:101-113

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

67% of VPU instructions are used in vector version (process two or more data elements in vector registers):

92% of VPU addition or subtraction instructions are used in vector version.
14% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 352 bytes.

General properties

nb instructions	41
loop length	164
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	14.00	14.00	5.50	5.50	5.50	5.50	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	14.00	14.00	5.50	5.50	5.50	5.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	5.13
Data deps.	2.00
Overall L1	14.00

Vectorization ratios

all	67%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	92%
fma	100%
div/sqrt	100%
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

52% of peak store performance is reached (25.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41eae0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z23, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z23.D, P0/M, Z23.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z24, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z24.D, P0/M, Z23.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
SXTW Z24.D, P0/M, Z24.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X30, X30, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
SXTW Z23.D, P0/M, Z23.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z23.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X9, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z23.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X11, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z23.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X13, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z23.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X15, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z23.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X17, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z23.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X1, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z23.D, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X0, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z23.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X4, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z23.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X6, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z23.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X24, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MAD Z23.D, P0/M, Z22.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z21.D}, P0, [X23, Z23.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41eae0 <.omp_outlined.+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code