OV - exec - Loop 170

0x4229c0 LD1RD	{Z17.D}, P0/Z, [X21]    [8]

0x4229c4 MOVPRFX	Z7, Z0

0x4229c8 SDIV	Z7.D, P0/M, Z7.D, Z2.D

0x4229cc MOVPRFX	Z16, Z0

0x4229d0 MLS	Z16.D, P0/M, Z7.D, Z2.D

0x4229d4 SXTW	Z16.D, P0/M, Z16.D

0x4229d8 ADD	Z0.D, Z0.D, Z1.D

0x4229dc SUBS	X2, X2, X18

0x4229e0 SXTW	Z7.D, P0/M, Z7.D

0x4229e4 MOVPRFX	Z18, Z16

0x4229e8 MLA	Z18.D, P0/M, Z7.D, Z3.D

0x4229ec ST1D	{Z17.D}, P0, [X8, Z18.D,LSL #3]    [6]

0x4229f0 MOVPRFX	Z18, Z16

0x4229f4 MLA	Z18.D, P0/M, Z7.D, Z4.D

0x4229f8 LD1RD	{Z17.D}, P0/Z, [X22]    [1]

0x4229fc ST1D	{Z17.D}, P0, [X10, Z18.D,LSL #3]    [7]

0x422a00 MOVPRFX	Z18, Z16

0x422a04 MLA	Z18.D, P0/M, Z7.D, Z5.D

0x422a08 MAD	Z7.D, P0/M, Z6.D, Z16.D

0x422a0c LD1RD	{Z17.D}, P0/Z, [X23]    [2]

0x422a10 ST1D	{Z17.D}, P0, [X12, Z18.D,LSL #3]    [3]

0x422a14 LD1RD	{Z17.D}, P0/Z, [X24]    [4]

0x422a18 ST1D	{Z17.D}, P0, [X14, Z7.D,LSL #3]    [5]

0x422a1c B.NE	4229c0

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp: 75 - 77

--------------------------------------------------------------------------------

75:   for (int j = (0); j < (yrange); j++) {

76:     for (int i = (0); i < (xrange); i++) {

77:       field.energy0(i, j) = state_energy[0];

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.75
Bottlenecks	P6, P7,
Function	.omp_outlined.#0x4228a0
Source	context.h:69-69,generate_chunk.cpp:75-77
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	7.00
Front-end cycles	3.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	7.00
P6 cycles	7.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.86
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	56.52
Vectorization ratio load	0.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	83.33
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	28.57
Vector-efficiency ratio all	83.70
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	87.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.75
Bottlenecks	P6, P7,
Function	.omp_outlined.#0x4228a0
Source	context.h:69-69,generate_chunk.cpp:75-77
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	7.00
Front-end cycles	3.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	7.00
P6 cycles	7.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.86
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	56.52
Vectorization ratio load	0.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	83.33
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	28.57
Vector-efficiency ratio all	83.70
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	87.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x4228a0
Source file and lines	generate_chunk.cpp:75-77
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp:75-77

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 83% of vector register length is used (average across all VPU instructions).

Details

56% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
83% of VPU addition or subtraction instructions are used in vector version.
28% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 128 bytes.

General properties

nb instructions	24
loop length	96
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	7.00	7.00	2.00	2.00	4.00	4.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	7.00	7.00	2.00	2.00	4.00	4.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.00
Data deps.	2.00
Overall L1	7.00

Vectorization ratios

all	56%
load	0%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	83%
fma	100%
div/sqrt	100%
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

4% of peak load performance is reached (4.57 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
38% of peak store performance is reached (18.29 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4229c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1RD {Z17.D}, P0/Z, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z7, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z7.D, P0/M, Z7.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z16, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z16.D, P0/M, Z7.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
SXTW Z16.D, P0/M, Z16.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X2, X2, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
SXTW Z7.D, P0/M, Z7.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z18, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z18.D, P0/M, Z7.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z17.D}, P0, [X8, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z18, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z18.D, P0/M, Z7.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1RD {Z17.D}, P0/Z, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z17.D}, P0, [X10, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z18, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z18.D, P0/M, Z7.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MAD Z7.D, P0/M, Z6.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1RD {Z17.D}, P0/Z, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z17.D}, P0, [X12, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1RD {Z17.D}, P0/Z, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z17.D}, P0, [X14, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 4229c0 <.omp_outlined.+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.#0x4228a0
Source file and lines	generate_chunk.cpp:75-77
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp:75-77

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 83% of vector register length is used (average across all VPU instructions).

Details

56% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
83% of VPU addition or subtraction instructions are used in vector version.
28% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 128 bytes.

General properties

nb instructions	24
loop length	96
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	7.00	7.00	2.00	2.00	4.00	4.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	7.00	7.00	2.00	2.00	4.00	4.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.00
Data deps.	2.00
Overall L1	7.00

Vectorization ratios

all	56%
load	0%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	83%
fma	100%
div/sqrt	100%
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

4% of peak load performance is reached (4.57 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
38% of peak store performance is reached (18.29 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4229c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1RD {Z17.D}, P0/Z, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z7, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z7.D, P0/M, Z7.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z16, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z16.D, P0/M, Z7.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
SXTW Z16.D, P0/M, Z16.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X2, X2, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
SXTW Z7.D, P0/M, Z7.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z18, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z18.D, P0/M, Z7.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z17.D}, P0, [X8, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z18, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z18.D, P0/M, Z7.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1RD {Z17.D}, P0/Z, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z17.D}, P0, [X10, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z18, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z18.D, P0/M, Z7.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MAD Z7.D, P0/M, Z6.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1RD {Z17.D}, P0/Z, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z17.D}, P0, [X12, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1RD {Z17.D}, P0/Z, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z17.D}, P0, [X14, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 4229c0 <.omp_outlined.+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code