OV - exec - Loop 146

	Loop Id: 146	Module: exec	Source: viscosity.cpp:37-64 [...]	Coverage: 6.05%

0x43de20 MOVPRFX	Z26, Z0

0x43de24 SDIV	Z26.D, P0/M, Z26.D, Z2.D

0x43de28 MOVPRFX	Z29, Z0

0x43de2c MLS	Z29.D, P0/M, Z26.D, Z2.D

0x43de30 ADD	Z30.D, Z4.D, Z29.D

0x43de34 ADD	Z31.D, Z20.D, Z29.D

0x43de38 SUBS	X12, X12, X10

0x43de3c ADD	Z9.D, Z21.D, Z26.D

0x43de40 ADD	Z28.D, Z3.D, Z26.D

0x43de44 MOVPRFX	Z25, Z28

0x43de48 SXTW	Z25.D, P0/M, Z28.D

0x43de4c MOVPRFX	Z27, Z5

0x43de50 MUL	Z27.D, P0/M, Z27.D, Z25.D

0x43de54 ADD	Z29.D, Z16.D, Z29.D

0x43de58 ADD	Z0.D, Z0.D, Z1.D

0x43de5c ADR	Z8.D, [Z27, Z31.D,SXTW]    [27]

0x43de60 LD1D	{Z8.D}, P0/Z, [X24, Z8.D,LSL #3]    [20]

0x43de64 SXTW	Z9.D, P0/M, Z9.D

0x43de68 MOVPRFX	Z10, Z5

0x43de6c MUL	Z10.D, P0/M, Z10.D, Z9.D

0x43de70 ADR	Z11.D, [Z10, Z31.D,SXTW]    [6]

0x43de74 ADR	Z27.D, [Z27, Z30.D,SXTW]    [13]

0x43de78 LD1D	{Z11.D}, P0/Z, [X24, Z11.D,LSL #3]    [3]

0x43de7c LD1D	{Z27.D}, P0/Z, [X24, Z27.D,LSL #3]    [23]

0x43de80 MOVPRFX	Z14, Z6

0x43de84 MUL	Z14.D, P0/M, Z14.D, Z9.D

0x43de88 ADR	Z10.D, [Z10, Z30.D,SXTW]    [5]

0x43de8c LD1D	{Z10.D}, P0/Z, [X24, Z10.D,LSL #3]    [7]

0x43de90 FADD	Z12.D, Z11.D, Z8.D

0x43de94 FADD	Z13.D, Z27.D, Z10.D

0x43de98 FADD	Z27.D, Z8.D, Z27.D

0x43de9c ADR	Z8.D, [Z14, Z30.D,SXTW]    [19]

0x43dea0 ADR	Z14.D, [Z14, Z31.D,SXTW]    [8]

0x43dea4 FSUB	Z27.D, Z11.D, Z27.D

0x43dea8 MOVPRFX	Z11, Z6

0x43deac MUL	Z11.D, P0/M, Z11.D, Z25.D

0x43deb0 FSUB	Z12.D, Z12.D, Z13.D

0x43deb4 ADR	Z13.D, [Z11, Z30.D,SXTW]    [18]

0x43deb8 LD1D	{Z8.D}, P0/Z, [X26, Z8.D,LSL #3]    [12]

0x43debc LD1D	{Z14.D}, P0/Z, [X26, Z14.D,LSL #3]    [16]

0x43dec0 ADR	Z11.D, [Z11, Z31.D,SXTW]    [9]

0x43dec4 LD1D	{Z13.D}, P0/Z, [X26, Z13.D,LSL #3]    [10]

0x43dec8 FADD	Z10.D, Z27.D, Z10.D

0x43decc LD1D	{Z11.D}, P0/Z, [X26, Z11.D,LSL #3]    [14]

0x43ded0 FADD	Z27.D, Z14.D, Z8.D

0x43ded4 FMUL	Z10.D, P0/M, Z10.D, #0

0x43ded8 FADD	Z8.D, Z8.D, Z13.D

0x43dedc FADD	Z13.D, Z13.D, Z11.D

0x43dee0 FSUB	Z8.D, Z14.D, Z8.D

0x43dee4 FSUB	Z13.D, Z27.D, Z13.D

0x43dee8 MOVPRFX	Z27, Z30

0x43deec SXTW	Z27.D, P0/M, Z30.D

0x43def0 LD1D	{Z30.D}, P0/Z, [X27, Z30.D,SXTW #3]    [21]

0x43def4 LD1D	{Z28.D}, P0/Z, [X28, Z28.D,SXTW #3]    [24]

0x43def8 FADD	Z8.D, Z8.D, Z11.D

0x43defc MOVPRFX	Z11, Z7

0x43df00 MUL	Z11.D, P0/M, Z11.D, Z25.D

0x43df04 ADR	Z29.D, [Z11, Z29.D,SXTW]    [4]

0x43df08 ADR	Z11.D, [Z11, Z31.D,SXTW]    [25]

0x43df0c LD1D	{Z11.D}, P0/Z, [X22, Z11.D,LSL #3]    [26]

0x43df10 LD1D	{Z29.D}, P0/Z, [X22, Z29.D,LSL #3]    [11]

0x43df14 LD1D	{Z31.D}, P0/Z, [X27, Z31.D,SXTW #3]    [28]

0x43df18 FMUL	Z8.D, P0/M, Z8.D, #0

0x43df1c FDIV	Z10.D, P0/M, Z10.D, Z28.D

0x43df20 FDIV	Z8.D, P0/M, Z8.D, Z30.D

0x43df24 FSUB	Z29.D, Z11.D, Z29.D

0x43df28 FADD	Z31.D, Z31.D, Z30.D

0x43df2c MOVPRFX	Z11, Z13

0x43df30 FMUL	Z11.D, P0/M, Z11.D, #0

0x43df34 FDIV	Z29.D, P0/M, Z29.D, Z31.D

0x43df38 MOVPRFX	Z31, Z27

0x43df3c MLA	Z31.D, P0/M, Z7.D, Z9.D

0x43df40 ADD	Z9.D, Z17.D, Z26.D

0x43df44 ADD	Z26.D, Z24.D, Z26.D

0x43df48 LD1D	{Z31.D}, P0/Z, [X22, Z31.D,LSL #3]    [22]

0x43df4c SXTW	Z9.D, P0/M, Z9.D

0x43df50 MAD	Z9.D, P0/M, Z7.D, Z27.D

0x43df54 LD1D	{Z9.D}, P0/Z, [X22, Z9.D,LSL #3]    [17]

0x43df58 LD1D	{Z26.D}, P0/Z, [X28, Z26.D,SXTW #3]    [1]

0x43df5c FSUB	Z31.D, Z31.D, Z9.D

0x43df60 FADD	Z26.D, Z26.D, Z28.D

0x43df64 FDIVR	Z26.D, P0/M, Z26.D, Z31.D

0x43df68 FADD	Z31.D, Z8.D, Z10.D

0x43df6c FMUL	Z8.D, Z29.D, Z29.D

0x43df70 MOVPRFX	Z10, Z12

0x43df74 FMUL	Z10.D, P0/M, Z10.D, #0

0x43df78 FCMLT	P2.D, P0/Z, Z29.D, #0

0x43df7c FMUL	Z31.D, Z29.D, Z31.D

0x43df80 FABS	Z29.D, P0/M, Z29.D

0x43df84 FMUL	Z10.D, Z10.D, Z8.D

0x43df88 FMAXNM	Z29.D, P0/M, Z29.D, Z22.D

0x43df8c FDIV	Z10.D, P0/M, Z10.D, Z30.D

0x43df90 FMUL	Z9.D, Z26.D, Z26.D

0x43df94 FMUL	Z11.D, Z11.D, Z9.D

0x43df98 FADD	Z8.D, Z9.D, Z8.D

0x43df9c MOVPRFX	Z9, Z29

0x43dfa0 FNEG	Z9.D, P0/M, Z29.D

0x43dfa4 SEL	Z29.D, P2, Z9.D, Z29.D

0x43dfa8 FMAXNM	Z8.D, P0/M, Z8.D, Z22.D

0x43dfac FCMLT	P2.D, P0/Z, Z29.D, #0

0x43dfb0 FDIV	Z11.D, P0/M, Z11.D, Z28.D

0x43dfb4 FMAD	Z31.D, P0/M, Z26.D, Z10.D

0x43dfb8 FABS	Z26.D, P0/M, Z26.D

0x43dfbc FMAXNM	Z26.D, P0/M, Z26.D, Z22.D

0x43dfc0 MOVPRFX	Z9, Z26

0x43dfc4 FNEG	Z9.D, P0/M, Z26.D

0x43dfc8 SEL	Z26.D, P2, Z9.D, Z26.D

0x43dfcc FMUL	Z9.D, Z29.D, Z29.D

0x43dfd0 FMLA	Z9.D, P0/M, Z26.D, Z26.D

0x43dfd4 FADD	Z31.D, Z31.D, Z11.D

0x43dfd8 FDIV	Z31.D, P0/M, Z31.D, Z8.D

0x43dfdc FMUL	Z8.D, Z30.D, Z12.D

0x43dfe0 FMLA	Z8.D, P0/M, Z28.D, Z13.D

0x43dfe4 FCMLE	P1.D, P0/Z, Z31.D, #0

0x43dfe8 FCMLT	P1.D, P1/Z, Z8.D, #0

0x43dfec MOVPRFX	Z8, Z9

0x43dff0 FSQRT	Z8.D, P0/M, Z9.D

0x43dff4 FMUL	Z28.D, Z8.D, Z28.D

0x43dff8 FMUL	Z30.D, Z8.D, Z30.D

0x43dffc FDIVR	Z26.D, P0/M, Z26.D, Z28.D

0x43e000 FDIVR	Z29.D, P0/M, Z29.D, Z30.D

0x43e004 MOVPRFX	Z28, Z29

0x43e008 FABS	Z28.D, P0/M, Z29.D

0x43e00c FABS	Z26.D, P0/M, Z26.D

0x43e010 FMINNM	Z26.D, P0/M, Z26.D, Z28.D

0x43e014 MOVPRFX	Z28, Z27

0x43e018 MLA	Z28.D, P0/M, Z18.D, Z25.D

0x43e01c LD1D	{Z28.D}, P1/Z, [X13, Z28.D,LSL #3]    [15]

0x43e020 MAD	Z25.D, P0/M, Z19.D, Z27.D

0x43e024 FMUL	Z26.D, Z26.D, Z31.D

0x43e028 FADD	Z28.D, Z28.D, Z28.D

0x43e02c FMUL	Z26.D, Z26.D, Z26.D

0x43e030 FMUL	Z26.D, Z26.D, Z28.D

0x43e034 SEL	Z26.D, P1, Z26.D, Z23.D

0x43e038 ST1D	{Z26.D}, P0, [X21, Z25.D,LSL #3]    [2]

0x43e03c B.NE	43de20

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp: 37 - 64

--------------------------------------------------------------------------------

37:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

39:       double ugrad = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) - (xvel0(i, j) + xvel0(i + 0, j + 1));

40:       double vgrad = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) - (yvel0(i, j) + yvel0(i + 1, j + 0));

41:       double div = (celldx[i] * (ugrad) + celldy[j] * (vgrad));

42:       double strain2 = 0.5 * (xvel0(i + 0, j + 1) + xvel0(i + 1, j + 1) - xvel0(i, j) - xvel0(i + 1, j + 0)) / celldy[j] +

43:                        0.5 * (yvel0(i + 1, j + 0) + yvel0(i + 1, j + 1) - yvel0(i, j) - yvel0(i + 0, j + 1)) / celldx[i];

44:       double pgradx = (pressure(i + 1, j + 0) - pressure(i - 1, j + 0)) / (celldx[i] + celldx[i + 1]);

45:       double pgrady = (pressure(i + 0, j + 1) - pressure(i + 0, j - 1)) / (celldy[j] + celldy[j + 2]);

46:       double pgradx2 = pgradx * pgradx;

47:       double pgrady2 = pgrady * pgrady;

48:       double limiter = ((0.5 * (ugrad) / celldx[i]) * pgradx2 + (0.5 * (vgrad) / celldy[j]) * pgrady2 + strain2 * pgradx * pgrady) /

49:                        std::fmax(pgradx2 + pgrady2, g_small);

50:       if ((limiter > 0.0) || (div >= 0.0)) {

51:         viscosity(i, j) = 0.0;

52:       } else {

53:         double dirx = 1.0;

54:         if (pgradx < 0.0) dirx = -1.0;

55:         pgradx = dirx * std::fmax(g_small, std::fabs(pgradx));

56:         double diry = 1.0;

57:         if (pgradx < 0.0) diry = -1.0;

58:         pgrady = diry * std::fmax(g_small, std::fabs(pgrady));

59:         double pgrad = std::sqrt(pgradx * pgradx + pgrady * pgrady);

60:         double xgrad = std::fabs(celldx[i] * pgrad / pgradx);

61:         double ygrad = std::fabs(celldy[j] * pgrad / pgrady);

62:         double grad = std::fmin(xgrad, ygrad);

63:         double grad2 = grad * grad;

64:         viscosity(i, j) = 2.0 * density0(i, j) * grad2 * limiter * limiter;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.07
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.97
Bottlenecks	P6, P7,
Function	.omp_outlined.#0x43dc20
Source	context.h:69-69,viscosity.cpp:37-64
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	58.00
CQA cycles if no scalar integer	58.00
CQA cycles if FP arith vectorized	58.00
CQA cycles if fully vectorized	54.25
Front-end cycles	17.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	58.00
P6 cycles	58.00
P7 cycles	19.50
P8 cycles	19.50
P9 cycles	9.00
P10 cycles	9.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	11.00 - 5.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	136.00
Nb uops	136.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	3.59
Nb FLOP add-sub	80.00
Nb FLOP mul	64.00
Nb FLOP fma	12.00
Nb FLOP div	36.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.93
Bytes prefetched	0.00
Bytes loaded	544.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	79.26
Vectorization ratio load	62.96
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	73.81
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	55.26
Vector-efficiency ratio all	93.89
Vector-efficiency ratio load	72.22
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	80.36
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.07
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.97
Bottlenecks	P6, P7,
Function	.omp_outlined.#0x43dc20
Source	context.h:69-69,viscosity.cpp:37-64
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	58.00
CQA cycles if no scalar integer	58.00
CQA cycles if FP arith vectorized	58.00
CQA cycles if fully vectorized	54.25
Front-end cycles	17.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	58.00
P6 cycles	58.00
P7 cycles	19.50
P8 cycles	19.50
P9 cycles	9.00
P10 cycles	9.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	11.00 - 5.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	136.00
Nb uops	136.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	3.59
Nb FLOP add-sub	80.00
Nb FLOP mul	64.00
Nb FLOP fma	12.00
Nb FLOP div	36.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.93
Bytes prefetched	0.00
Bytes loaded	544.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	79.26
Vectorization ratio load	62.96
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	73.81
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	55.26
Vector-efficiency ratio all	93.89
Vector-efficiency ratio load	72.22
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	80.36
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x43dc20
Source file and lines	viscosity.cpp:37-64
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp:37-64

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 93% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 58.00 to 54.25 cycles (1.07x speedup).

Details

79% of VPU instructions are used in vector version (process two or more data elements in vector registers):

62% of VPU loads are used in vector version.
73% of VPU addition or subtraction instructions are used in vector version.
55% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 208 FP arithmetical operations:

92: addition or subtraction (12 inside FMA instructions)
76: multiply (12 inside FMA instructions)
36: divide
4: square root

The binary loop is loading 544 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.36 FP operations per loaded or stored byte.

General properties

nb instructions	136
loop length	544
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	58.00	58.00	0.50	0.50	9.00	9.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	58.00	58.00	19.50	19.50	9.00	9.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	11.00-5.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	17.00
Data deps.	1.00
Overall L1	58.00

Vectorization ratios

INT

all	61%
load	62%
store	100%
mul	100%
add-sub	50%
fma	100%
other	32%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	79%
load	62%
store	100%
mul	100%
add-sub	73%
fma	100%
div/sqrt	100%
other	55%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 58.00 cycles. At this rate:

9% of peak load performance is reached (9.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.55 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43de20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z26, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z26.D, P0/M, Z26.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z29, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z29.D, P0/M, Z26.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z30.D, Z4.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z31.D, Z20.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z9.D, Z21.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z28.D, Z3.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z25, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z25.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z27, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z27.D, P0/M, Z27.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z29.D, Z16.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z8.D, [Z27, Z31.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z8.D}, P0/Z, [X24, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SXTW Z9.D, P0/M, Z9.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z10, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z10.D, P0/M, Z10.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z11.D, [Z10, Z31.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z27.D, [Z27, Z30.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z11.D}, P0/Z, [X24, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z27.D}, P0/Z, [X24, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z14, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z14.D, P0/M, Z14.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z10.D, [Z10, Z30.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z10.D}, P0/Z, [X24, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z12.D, Z11.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z13.D, Z27.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z27.D, Z8.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z8.D, [Z14, Z30.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z14.D, [Z14, Z31.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z27.D, Z11.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z11, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z11.D, P0/M, Z11.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FSUB Z12.D, Z12.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z13.D, [Z11, Z30.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z8.D}, P0/Z, [X26, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z14.D}, P0/Z, [X26, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z11.D, [Z11, Z31.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z13.D}, P0/Z, [X26, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z10.D, Z27.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z11.D}, P0/Z, [X26, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z27.D, Z14.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z10.D, P0/M, Z10.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z8.D, Z8.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z13.D, Z13.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z8.D, Z14.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z13.D, Z27.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z27, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z27.D, P0/M, Z30.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
LD1D {Z30.D}, P0/Z, [X27, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P0/Z, [X28, Z28.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z8.D, Z8.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z11, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z11.D, P0/M, Z11.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z29.D, [Z11, Z29.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z11.D, [Z11, Z31.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z11.D}, P0/Z, [X22, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z29.D}, P0/Z, [X22, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X27, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z8.D, P0/M, Z8.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z10.D, P0/M, Z10.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIV Z8.D, P0/M, Z8.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FSUB Z29.D, Z11.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z31.D, Z31.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z11, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z11.D, P0/M, Z11.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z29.D, P0/M, Z29.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z31, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z31.D, P0/M, Z7.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z9.D, Z17.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z26.D, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z31.D}, P0/Z, [X22, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SXTW Z9.D, P0/M, Z9.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MAD Z9.D, P0/M, Z7.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z9.D}, P0/Z, [X22, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P0/Z, [X28, Z26.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z31.D, Z31.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z26.D, Z26.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIVR Z26.D, P0/M, Z26.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z31.D, Z8.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z8.D, Z29.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z10, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z10.D, P0/M, Z10.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FCMLT P2.D, P0/Z, Z29.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z31.D, Z29.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FABS Z29.D, P0/M, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z10.D, Z10.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAXNM Z29.D, P0/M, Z29.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z10.D, P0/M, Z10.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z9.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z11.D, Z11.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z8.D, Z9.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z9, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z9.D, P0/M, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z29.D, P2, Z9.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAXNM Z8.D, P0/M, Z8.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMLT P2.D, P0/Z, Z29.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FDIV Z11.D, P0/M, Z11.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMAD Z31.D, P0/M, Z26.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FABS Z26.D, P0/M, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAXNM Z26.D, P0/M, Z26.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z9, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z9.D, P0/M, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z26.D, P2, Z9.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z9.D, Z29.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z9.D, P0/M, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z31.D, Z31.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z31.D, P0/M, Z31.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z8.D, Z30.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z8.D, P0/M, Z28.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FCMLE P1.D, P0/Z, Z31.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FCMLT P1.D, P1/Z, Z8.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z8, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSQRT Z8.D, P0/M, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	1-0.50
FMUL Z28.D, Z8.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z30.D, Z8.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIVR Z26.D, P0/M, Z26.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIVR Z29.D, P0/M, Z29.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z28, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z28.D, P0/M, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z26.D, P0/M, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z26.D, P0/M, Z26.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z28, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z28.D, P0/M, Z18.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z28.D}, P1/Z, [X13, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z25.D, P0/M, Z19.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMUL Z26.D, Z26.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z28.D, Z28.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z26.D, Z26.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
SEL Z26.D, P1, Z26.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z26.D}, P0, [X21, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 43de20 <.omp_outlined.+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.#0x43dc20
Source file and lines	viscosity.cpp:37-64
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp:37-64

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

79% of VPU instructions are used in vector version (process two or more data elements in vector registers):

62% of VPU loads are used in vector version.
73% of VPU addition or subtraction instructions are used in vector version.
55% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 208 FP arithmetical operations:

92: addition or subtraction (12 inside FMA instructions)
76: multiply (12 inside FMA instructions)
36: divide
4: square root

The binary loop is loading 544 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.36 FP operations per loaded or stored byte.

General properties

nb instructions	136
loop length	544
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	58.00	58.00	0.50	0.50	9.00	9.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	58.00	58.00	19.50	19.50	9.00	9.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	11.00-5.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	17.00
Data deps.	1.00
Overall L1	58.00

Vectorization ratios

INT

all	61%
load	62%
store	100%
mul	100%
add-sub	50%
fma	100%
other	32%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	79%
load	62%
store	100%
mul	100%
add-sub	73%
fma	100%
div/sqrt	100%
other	55%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 58.00 cycles. At this rate:

9% of peak load performance is reached (9.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.55 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43de20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z26, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z26.D, P0/M, Z26.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z29, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z29.D, P0/M, Z26.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z30.D, Z4.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z31.D, Z20.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z9.D, Z21.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z28.D, Z3.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z25, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z25.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z27, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z27.D, P0/M, Z27.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z29.D, Z16.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z8.D, [Z27, Z31.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z8.D}, P0/Z, [X24, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SXTW Z9.D, P0/M, Z9.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z10, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z10.D, P0/M, Z10.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z11.D, [Z10, Z31.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z27.D, [Z27, Z30.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z11.D}, P0/Z, [X24, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z27.D}, P0/Z, [X24, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z14, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z14.D, P0/M, Z14.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z10.D, [Z10, Z30.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z10.D}, P0/Z, [X24, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z12.D, Z11.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z13.D, Z27.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z27.D, Z8.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z8.D, [Z14, Z30.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z14.D, [Z14, Z31.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z27.D, Z11.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z11, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z11.D, P0/M, Z11.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FSUB Z12.D, Z12.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z13.D, [Z11, Z30.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z8.D}, P0/Z, [X26, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z14.D}, P0/Z, [X26, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z11.D, [Z11, Z31.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z13.D}, P0/Z, [X26, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z10.D, Z27.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z11.D}, P0/Z, [X26, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z27.D, Z14.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z10.D, P0/M, Z10.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z8.D, Z8.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z13.D, Z13.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z8.D, Z14.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z13.D, Z27.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z27, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z27.D, P0/M, Z30.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
LD1D {Z30.D}, P0/Z, [X27, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P0/Z, [X28, Z28.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z8.D, Z8.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z11, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z11.D, P0/M, Z11.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z29.D, [Z11, Z29.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z11.D, [Z11, Z31.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z11.D}, P0/Z, [X22, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z29.D}, P0/Z, [X22, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X27, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z8.D, P0/M, Z8.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z10.D, P0/M, Z10.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIV Z8.D, P0/M, Z8.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FSUB Z29.D, Z11.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z31.D, Z31.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z11, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z11.D, P0/M, Z11.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z29.D, P0/M, Z29.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z31, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z31.D, P0/M, Z7.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z9.D, Z17.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z26.D, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z31.D}, P0/Z, [X22, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SXTW Z9.D, P0/M, Z9.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MAD Z9.D, P0/M, Z7.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z9.D}, P0/Z, [X22, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P0/Z, [X28, Z26.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z31.D, Z31.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z26.D, Z26.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIVR Z26.D, P0/M, Z26.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z31.D, Z8.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z8.D, Z29.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z10, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z10.D, P0/M, Z10.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FCMLT P2.D, P0/Z, Z29.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z31.D, Z29.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FABS Z29.D, P0/M, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z10.D, Z10.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAXNM Z29.D, P0/M, Z29.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z10.D, P0/M, Z10.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z9.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z11.D, Z11.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z8.D, Z9.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z9, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z9.D, P0/M, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z29.D, P2, Z9.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAXNM Z8.D, P0/M, Z8.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMLT P2.D, P0/Z, Z29.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FDIV Z11.D, P0/M, Z11.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMAD Z31.D, P0/M, Z26.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FABS Z26.D, P0/M, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAXNM Z26.D, P0/M, Z26.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z9, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z9.D, P0/M, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z26.D, P2, Z9.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z9.D, Z29.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z9.D, P0/M, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z31.D, Z31.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z31.D, P0/M, Z31.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z8.D, Z30.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z8.D, P0/M, Z28.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FCMLE P1.D, P0/Z, Z31.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FCMLT P1.D, P1/Z, Z8.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z8, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSQRT Z8.D, P0/M, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	1-0.50
FMUL Z28.D, Z8.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z30.D, Z8.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIVR Z26.D, P0/M, Z26.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIVR Z29.D, P0/M, Z29.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z28, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z28.D, P0/M, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z26.D, P0/M, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z26.D, P0/M, Z26.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z28, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z28.D, P0/M, Z18.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z28.D}, P1/Z, [X13, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z25.D, P0/M, Z19.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMUL Z26.D, Z26.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z28.D, Z28.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z26.D, Z26.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
SEL Z26.D, P1, Z26.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z26.D}, P0, [X21, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 43de20 <.omp_outlined.+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code