OV - exec - Function .omp_outlined..20#0x42b930

	Function: .omp_outlined..20#0x42b930	Module: exec	Source: update_halo.cpp:150-153	Coverage: 0.04%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 150 - 153

--------------------------------------------------------------------------------

150: #pragma omp parallel for simd

151:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

152:         for (int j = 0; j < depth; ++j) {

153:           field.energy0(1 - j, k) = field.energy0(2 + j, k);

0x42b930 SUB	SP, SP, #128

0x42b934 STP	X29, X30, [SP, #32]

0x42b938 STP	X28, X27, [SP, #48]

0x42b93c STP	X26, X25, [SP, #64]

0x42b940 STP	X24, X23, [SP, #80]

0x42b944 STP	X22, X21, [SP, #96]

0x42b948 STP	X20, X19, [SP, #112]

0x42b94c ADD	X29, SP, #32

0x42b950 LDR	W22, [X2]

0x42b954 LDR	W20, [X3]

0x42b958 LDR	W8, [X4]

0x42b95c SUB	W9, W22, W20

0x42b960 ADD	W8, W8, W20

0x42b964 SUBS	W24, W8, W9

0x42b968 B.LT	42b9e0

0x42b96c LDR	W19, [X0]

0x42b970 LDR	X23, [X5, #48]

0x42b974 LDR	X21, [X5, #64]

0x42b978 MOVZ	W8, #1

0x42b97c ADRP	X0,

0x42b980 ADD	X0, X0, #3408

0x42b984 ADD	X3, SP, #16

0x42b988 SUB	X4, X29, #4

0x42b98c STP	W24, WZR, [X29, #504]

0x42b990 SUB	X5, X29, #8

0x42b994 SUB	X6, X29, #12

0x42b998 MOVZ	W2, #34

0x42b99c STUR	W8, [X29, #500]

0x42b9a0 STR	WZR, [SP, #16]

0x42b9a4 STR	W8, [SP]

0x42b9a8 MOVZ	W7, #1

0x42b9ac ORR	W1, WZR, W19

0x42b9b0 BL	402dc0

0x42b9b4 LDP	W8, W9, [X29, #504]

0x42b9b8 CMP	W8, W24

0x42b9bc CSEL	W8, W8, W24, #3

0x42b9c0 ADD	W10, W8, #1

0x42b9c4 CMP	W9, W10

0x42b9c8 CCMP	W20, #1, #8, #3

0x42b9cc B.GE	42ba00

(352) 0x42b9d0 ORR	W1, WZR, W19

(352) 0x42b9d4 ADRP	X0,

(352) 0x42b9d8 ADD	X0, X0, #3432

(352) 0x42b9dc BL	403260

(352) 0x42b9e0 LDP	X20, X19, [SP, #112]

(352) 0x42b9e4 LDP	X22, X21, [SP, #96]

(352) 0x42b9e8 LDP	X24, X23, [SP, #80]

(352) 0x42b9ec LDP	X26, X25, [SP, #64]

(352) 0x42b9f0 LDP	X28, X27, [SP, #48]

(352) 0x42b9f4 LDP	X29, X30, [SP, #32]

(352) 0x42b9f8 ADD	SP, SP, #128

(352) 0x42b9fc RET

(352) 0x42ba00 ADD	W15, W9, W22

(352) 0x42ba04 CNTW	X11, ALL

(352) 0x42ba08 SUB	X2, X20, #1

(352) 0x42ba0c ADD	X14, X21, #16

(352) 0x42ba10 MOVZ	W17, #12

(352) 0x42ba14 RDVL	X4, #1

(352) 0x42ba18 ORR	W10, WZR, WZR

(352) 0x42ba1c ADD	X12, X21, #8

(352) 0x42ba20 UBFM	X13, X23, #61, #60

(352) 0x42ba24 RDVL	X18, #2

(352) 0x42ba28 RDVL	X0, #62

(352) 0x42ba2c ADD	X1, X21, #24

(352) 0x42ba30 CMP	X11, #12

(352) 0x42ba34 SUB	W16, W15, W20

(352) 0x42ba38 SUB	X15, XZR, X2,LSL #3

(352) 0x42ba3c UBFM	X2, X2, #61, #63

(352) 0x42ba40 CSEL	X17, X11, X17, #8

(352) 0x42ba44 ADDVL	X3, X14, #1

(352) 0x42ba48 SUB	X4, X14, X4

(352) 0x42ba4c ADD	W16, W16, #1

(352) 0x42ba50 ADDVL	X5, X14, #62

(352) 0x42ba54 PTRUE	P0.B, ALL

(352) 0x42ba58 ORR	W6, WZR, W16

(352) 0x42ba5c B	42ba74

(352) 0x42ba60 CMP	W9, W8

(352) 0x42ba64 ADD	W9, W9, #1

(352) 0x42ba68 ADD	W10, W10, #1

(352) 0x42ba6c ADD	W6, W6, #1

(352) 0x42ba70 B.EQ	42b9d0

(352) 0x42ba74 SBFM	X7, X6, #0, #31

(352) 0x42ba78 CMP	X17, X20

(352) 0x42ba7c MADD	X7, X13, X7, XZR

(352) 0x42ba80 B.HI	42baa0

(352) 0x42ba84 ADD	W22, W16, W10

(352) 0x42ba88 SBFM	X22, X22, #0, #31

(352) 0x42ba8c MADD	X22, X13, X22, X12

(352) 0x42ba90 ADD	X23, X22, X15

(352) 0x42ba94 CMP	X23, X22

(352) 0x42ba98 CCMP	X2, #0, #0, #9

(352) 0x42ba9c B.EQ	42bb40

(352) 0x42baa0 ORR	X22, XZR, XZR

(352) 0x42baa4 SUB	W23, W20, W22

(352) 0x42baa8 ANDS	X24, X23, #4160

(352) 0x42baac ORR	X23, XZR, X22

(352) 0x42bab0 B.EQ	42bad8

(352) 0x42bab4 SUB	X23, X7, X22,LSL #3

(352) 0x42bab8 ADD	X25, X14, X7

(352) 0x42babc ADD	X26, X12, X23

(352) 0x42bac0 ORR	X23, XZR, X22

  (354) 0x42bac4 LDR	D0, [X25, X23,LSL #3]

  (354) 0x42bac8 ADD	X23, X23, #1

  (354) 0x42bacc SUBS	X24, X24, #1

  (354) 0x42bad0 STR	D0, [X26], #504

  (354) 0x42bad4 B.NE	42bac4

(352) 0x42bad8 ORN	X22, XZR, X22

(352) 0x42badc ADD	X22, X22, X20

(352) 0x42bae0 CMP	X22, #3

(352) 0x42bae4 B.CC	42ba60

(352) 0x42bae8 UBFM	X24, X23, #61, #60

(352) 0x42baec SUB	X23, X20, X23

(352) 0x42baf0 SUB	X22, X7, X24

(352) 0x42baf4 ADD	X7, X7, X24

(352) 0x42baf8 ADD	X22, X21, X22

(352) 0x42bafc ADD	X7, X1, X7

  (353) 0x42bb00 LDUR	D0, [X7, #504]

  (353) 0x42bb04 SUBS	X23, X23, #4

  (353) 0x42bb08 STR	D0, [X22, #8]

  (353) 0x42bb0c LDR	D0, [X7]

  (353) 0x42bb10 STR	D0, [X22]

  (353) 0x42bb14 LDR	D0, [X7, #8]

  (353) 0x42bb18 STUR	D0, [X22, #504]

  (353) 0x42bb1c LDR	D0, [X7, #16]

  (353) 0x42bb20 ADD	X7, X7, #32

  (353) 0x42bb24 STUR	D0, [X22, #496]

  (353) 0x42bb28 SUB	X22, X22, #32

  (353) 0x42bb2c B.NE	42bb00

(352) 0x42bb30 B	42ba60

0x42bb34 HINT	#0

0x42bb38 HINT	#0

0x42bb3c HINT	#0

(352) 0x42bb40 UDIV	X22, X20, X11

(352) 0x42bb44 ORR	X25, XZR, X5

(352) 0x42bb48 ORR	X26, XZR, X4

(352) 0x42bb4c ORR	X27, XZR, X3

(352) 0x42bb50 ORR	X28, XZR, X14

(352) 0x42bb54 UMSUBL	X23, W22, W11, X20

(352) 0x42bb58 UMADDL	X22, W22, W11, XZR

(352) 0x42bb5c ORR	X24, XZR, X22

  (355) 0x42bb60 LD1B	{Z0.B}, P0/Z, [X28, X7]

  (355) 0x42bb64 LD1B	{Z1.B}, P0/Z, [X27, X7]

  (355) 0x42bb68 ADD	X28, X28, X18

  (355) 0x42bb6c ADD	X27, X27, X18

  (355) 0x42bb70 SUBS	X24, X24, X11

  (355) 0x42bb74 REV	Z0.D, Z0.D

  (355) 0x42bb78 ST1B	{Z0.B}, P0, [X26, X7]

  (355) 0x42bb7c REV	Z0.D, Z1.D

  (355) 0x42bb80 ADD	X26, X26, X0

  (355) 0x42bb84 ST1B	{Z0.B}, P0, [X25, X7]

  (355) 0x42bb88 ADD	X25, X25, X0

  (355) 0x42bb8c B.NE	42bb60

(352) 0x42bb90 CBNZ	X23, 42baa4

0x42bb94 B	42ba60

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:150-153
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:150-153.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.67 to 0.71 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	44
loop length	176
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42b930

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42b9e0 <.omp_outlined..20+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <46397c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3408	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42ba00 <.omp_outlined..20+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 42ba60 <.omp_outlined..20+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	update_halo.cpp:150-153
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:150-153.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	44
loop length	176
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42b930

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42b9e0 <.omp_outlined..20+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <46397c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3408	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42ba00 <.omp_outlined..20+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 42ba60 <.omp_outlined..20+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined..20#0x42b930–	0.04	0.02
▼Loop 352 - update_halo.cpp:150-153 - exec–	0	0
○Loop 354 - update_halo.cpp:152-153 - exec	0.04	0.02
○Loop 355 - update_halo.cpp:152-153 - exec	0	0
○Loop 353 - update_halo.cpp:152-153 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code