OV - exec - Function .omp_outlined..2#0x428b60

	Function: .omp_outlined..2#0x428b60	Module: exec	Source: reset_field.cpp:44-48 [...]	Coverage: 1.36%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/reset_field.cpp: 44 - 48

--------------------------------------------------------------------------------

44: #pragma omp parallel for simd collapse(2)

45:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

46:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

47:       xvel0(i, j) = xvel1(i, j);

48:       yvel0(i, j) = yvel1(i, j);

0x428b60 SUB	SP, SP, #160

0x428b64 STP	X29, X30, [SP, #64]

0x428b68 STP	X28, X27, [SP, #80]

0x428b6c STP	X26, X25, [SP, #96]

0x428b70 STP	X24, X23, [SP, #112]

0x428b74 STP	X22, X21, [SP, #128]

0x428b78 STP	X20, X19, [SP, #144]

0x428b7c ADD	X29, SP, #64

0x428b80 LDR	W8, [X2]

0x428b84 LDR	W9, [X3]

0x428b88 LDR	W10, [X4]

0x428b8c ADD	W20, W8, #1

0x428b90 LDR	W11, [X5]

0x428b94 ADD	W8, W9, #3

0x428b98 ADD	W21, W10, #1

0x428b9c ADD	W9, W11, #3

0x428ba0 SUBS	W8, W8, W20

0x428ba4 CCMP	W9, W21, #4, #12

0x428ba8 B.LE	428d40

0x428bac LDP	X11, X10, [X29, #96]

0x428bb0 LDR	X12, [X6]

0x428bb4 SUB	W22, W9, W21

0x428bb8 MOVN	X9, #0

0x428bbc LDR	W1, [X0]

0x428bc0 ADRP	X0,

0x428bc4 ADD	X0, X0, #2544

0x428bc8 SUB	X3, X29, #28

0x428bcc LDR	X23, [X6, #16]

0x428bd0 LDR	X24, [X7]

0x428bd4 LDR	X25, [X7, #16]

0x428bd8 SUB	X4, X29, #8

0x428bdc SUB	X5, X29, #16

0x428be0 SUB	X6, X29, #24

0x428be4 MOVZ	W2, #34

0x428be8 STUR	WZR, [X29, #484]

0x428bec MOVZ	W7, #1

0x428bf0 LDR	X26, [X11]

0x428bf4 LDR	X27, [X11, #16]

0x428bf8 LDR	X28, [X10]

0x428bfc LDR	X19, [X10, #16]

0x428c00 UMADDL	X8, W22, W8, X9

0x428c04 STP	X12, X8, [SP, #16]

0x428c08 STP	X8, XZR, [X29, #1008]

0x428c0c MOVZ	W8, #1

0x428c10 STR	W1, [SP, #32]

0x428c14 STUR	X8, [X29, #488]

0x428c18 STR	X8, [SP]

0x428c1c BL	4033a0

0x428c20 LDP	X8, X13, [X29, #1008]

0x428c24 LDR	X9, [SP, #24]

0x428c28 CMP	X8, X9

0x428c2c CSEL	X8, X8, X9, #11

0x428c30 CMP	X13, X8

0x428c34 B.GT	428d30

0x428c38 ADD	X8, X8, #1

0x428c3c CNTD	X10, ALL

0x428c40 ORR	X9, XZR, X13

0x428c44 SUB	X11, X8, X13

0x428c48 CMP	X11, X10

0x428c4c B.CC	428ce4

0x428c50 UDIV	X9, X11, X10

0x428c54 PTRUE	P0.D, ALL

0x428c58 MADD	X12, X9, X10, XZR

0x428c5c INDEX	Z0.D, X13, #1

0x428c60 ADD	X9, X13, X12

0x428c64 LDR	X13, [SP, #16]

0x428c68 DUP	Z1.D, X10

0x428c6c SUB	X11, X11, X12

0x428c70 DUP	Z2.D, X22

0x428c74 DUP	Z3.D, X20

0x428c78 DUP	Z4.D, X21

0x428c7c DUP	Z5.D, X24

0x428c80 DUP	Z7.D, X28

0x428c84 DUP	Z16.D, X26

0x428c88 DUP	Z6.D, X13

(200) 0x428c8c MOVPRFX	Z17, Z0

(200) 0x428c90 SDIV	Z17.D, P0/M, Z17.D, Z2.D

(200) 0x428c94 ADD	Z18.D, Z3.D, Z17.D

(200) 0x428c98 MSB	Z17.D, P0/M, Z2.D, Z0.D

(200) 0x428c9c ADD	Z0.D, Z0.D, Z1.D

(200) 0x428ca0 SUBS	X12, X12, X10

(200) 0x428ca4 SXTW	Z18.D, P0/M, Z18.D

(200) 0x428ca8 ADD	Z17.D, Z4.D, Z17.D

(200) 0x428cac SXTW	Z17.D, P0/M, Z17.D

(200) 0x428cb0 MOVPRFX	Z19, Z17

(200) 0x428cb4 MLA	Z19.D, P0/M, Z5.D, Z18.D

(200) 0x428cb8 LD1D	{Z19.D}, P0/Z, [X25, Z19.D,LSL #3]

(200) 0x428cbc MOVPRFX	Z20, Z17

(200) 0x428cc0 MLA	Z20.D, P0/M, Z6.D, Z18.D

(200) 0x428cc4 ST1D	{Z19.D}, P0, [X23, Z20.D,LSL #3]

(200) 0x428cc8 MOVPRFX	Z19, Z17

(200) 0x428ccc MLA	Z19.D, P0/M, Z7.D, Z18.D

(200) 0x428cd0 MLA	Z17.D, P0/M, Z16.D, Z18.D

(200) 0x428cd4 LD1D	{Z19.D}, P0/Z, [X19, Z19.D,LSL #3]

(200) 0x428cd8 ST1D	{Z19.D}, P0, [X27, Z17.D,LSL #3]

(200) 0x428cdc B.NE	428c8c

0x428ce0 CBZ	X11, 428d30

0x428ce4 LDR	X14, [SP, #16]

0x428ce8 SUB	W10, WZR, W22

(199) 0x428cec SDIV	X11, X9, X22

(199) 0x428cf0 ADD	W13, W21, W9

(199) 0x428cf4 ADD	X9, X9, #1

(199) 0x428cf8 CMP	X8, X9

(199) 0x428cfc ADD	W12, W20, W11

(199) 0x428d00 MADD	W11, W10, W11, W13

(199) 0x428d04 SBFM	X11, X11, #0, #31

(199) 0x428d08 SBFM	X12, X12, #0, #31

(199) 0x428d0c MADD	X13, X24, X12, X11

(199) 0x428d10 LDR	D0, [X25, X13,LSL #3]

(199) 0x428d14 MADD	X13, X14, X12, X11

(199) 0x428d18 STR	D0, [X23, X13,LSL #3]

(199) 0x428d1c MADD	X13, X28, X12, X11

(199) 0x428d20 MADD	X11, X26, X12, X11

(199) 0x428d24 LDR	D0, [X19, X13,LSL #3]

(199) 0x428d28 STR	D0, [X27, X11,LSL #3]

(199) 0x428d2c B.NE	428cec

0x428d30 LDR	W1, [SP, #32]

0x428d34 ADRP	X0,

0x428d38 ADD	X0, X0, #2568

0x428d3c BL	403260

0x428d40 LDP	X20, X19, [SP, #144]

0x428d44 LDP	X22, X21, [SP, #128]

0x428d48 LDP	X24, X23, [SP, #112]

0x428d4c LDP	X26, X25, [SP, #96]

0x428d50 LDP	X28, X27, [SP, #80]

0x428d54 LDP	X29, X30, [SP, #64]

0x428d58 ADD	SP, SP, #160

0x428d5c RET

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	reset_field.cpp:44-48
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/reset_field.cpp:44-48

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.00 to 9.00 cycles (1.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 13.00 to 12.33 cycles (1.05x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.00 to 1.00 cycles (13.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 240 bytes. The binary function is storing 152 bytes.

General properties

nb instructions	90
loop length	360
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	11.50	11.25	13.00	11.25	1.00	0.00	0.00	0.00	12.33	12.33	12.33	6.00	6.00
cycles	3.50	3.50	11.50	11.25	13.00	11.25	1.00	0.00	0.00	0.00	12.33	12.33	12.33	6.00	6.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	11.25
Overall L1	13.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.00 cycles. At this rate:

19% of peak load performance is reached (18.46 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (11.69 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 428b60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR W8, [X2]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W10, [X4]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W20, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR W11, [X5]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD W21, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD W9, W11, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUBS W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
CCMP W9, W21, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
B.LE 428d40 <.omp_outlined..2+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X29, #96]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X12, [X6]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W22, W9, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463bc0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2544	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR X23, [X6, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X7]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X7, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR X26, [X11]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X11, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X10]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X10, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UMADDL X8, W22, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
STP X12, X8, [SP, #16]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
STR W1, [SP, #32]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X13, [X29, #1008]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X9, [SP, #24]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
CSEL X8, X8, X9, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.GT 428d30 <.omp_outlined..2+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CNTD X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ORR X9, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB X11, X8, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.CC 428ce4 <.omp_outlined..2+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X9, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	5-20	1-0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
MADD X12, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
INDEX Z0.D, X13, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD X9, X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR X13, [SP, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z1.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
DUP Z2.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z3.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z4.D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z5.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z7.D, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z16.D, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z6.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
CBZ X11, 428d30 <.omp_outlined..2+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [SP, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W10, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR W1, [SP, #32]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463d34>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2568	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	reset_field.cpp:44-48
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/reset_field.cpp:44-48

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.00 to 9.00 cycles (1.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.00 to 1.00 cycles (13.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 240 bytes. The binary function is storing 152 bytes.

General properties

nb instructions	90
loop length	360
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	11.50	11.25	13.00	11.25	1.00	0.00	0.00	0.00	12.33	12.33	12.33	6.00	6.00
cycles	3.50	3.50	11.50	11.25	13.00	11.25	1.00	0.00	0.00	0.00	12.33	12.33	12.33	6.00	6.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	11.25
Overall L1	13.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.00 cycles. At this rate:

19% of peak load performance is reached (18.46 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (11.69 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 428b60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR W8, [X2]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W10, [X4]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W20, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR W11, [X5]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD W21, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD W9, W11, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUBS W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
CCMP W9, W21, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
B.LE 428d40 <.omp_outlined..2+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X29, #96]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X12, [X6]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W22, W9, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463bc0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2544	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR X23, [X6, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X7]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X7, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR X26, [X11]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X11, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X10]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X10, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UMADDL X8, W22, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
STP X12, X8, [SP, #16]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
STR W1, [SP, #32]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X13, [X29, #1008]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X9, [SP, #24]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
CSEL X8, X8, X9, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.GT 428d30 <.omp_outlined..2+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CNTD X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ORR X9, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB X11, X8, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.CC 428ce4 <.omp_outlined..2+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X9, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	5-20	1-0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
MADD X12, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
INDEX Z0.D, X13, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD X9, X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR X13, [SP, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z1.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
DUP Z2.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z3.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z4.D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z5.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z7.D, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z16.D, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z6.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
CBZ X11, 428d30 <.omp_outlined..2+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [SP, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W10, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR W1, [SP, #32]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463d34>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2568	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined..2#0x428b60–	1.36	0.73
○Loop 200 - reset_field.cpp:45-48 - exec	1.36	0.73
○Loop 199 - reset_field.cpp:45-48 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code