OV - exec - Function .omp_outlined..2#0x427e60

	Function: .omp_outlined..2#0x427e60	Module: exec	Source: PdV.cpp:69-83 [...]	Coverage: 5.97%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp: 69 - 83

--------------------------------------------------------------------------------

69: #pragma omp parallel for simd collapse(2)

70:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

71:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

72:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1))) * 0.25 * dt;

73:         double right_flux =

74:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel1(i + 1, j + 0) + xvel1(i + 1, j + 1))) * 0.25 * dt;

75:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0))) * 0.25 * dt;

76:         double top_flux =

77:             (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel1(i + 0, j + 1) + yvel1(i + 1, j + 1))) * 0.25 * dt;

78:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

79:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

80:         double recip_volume = 1.0 / volume(i, j);

81:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

82:         energy1(i, j) = energy0(i, j) - energy_change;

83:         density1(i, j) = density0(i, j) * volume_change_s;

0x427e60 STP	D15, D14, [SP, #864]!

0x427e64 STP	D13, D12, [SP, #16]

0x427e68 STP	D11, D10, [SP, #32]

0x427e6c STP	D9, D8, [SP, #48]

0x427e70 STP	X29, X30, [SP, #64]

0x427e74 STP	X28, X27, [SP, #80]

0x427e78 STP	X26, X25, [SP, #96]

0x427e7c STP	X24, X23, [SP, #112]

0x427e80 STP	X22, X21, [SP, #128]

0x427e84 STP	X20, X19, [SP, #144]

0x427e88 ADD	X29, SP, #64

0x427e8c ADDVL	SP, SP, #61

0x427e90 SUB	SP, SP, #272

0x427e94 LDR	W22, [X2]

0x427e98 LDR	W8, [X3]

0x427e9c ADD	W10, W22, #1

0x427ea0 ADD	W8, W8, #2

0x427ea4 SUBS	W8, W8, W10

0x427ea8 B.LE	428538

0x427eac LDR	W21, [X4]

0x427eb0 LDR	W9, [X5]

0x427eb4 ADD	W3, W21, #1

0x427eb8 ADD	W9, W9, #2

0x427ebc CMP	W9, W3

0x427ec0 B.LE	428538

0x427ec4 LDP	X17, X16, [X29, #128]

0x427ec8 LDP	X1, X18, [X29, #112]

0x427ecc LDR	X2, [X29, #96]

0x427ed0 LDP	X15, X14, [X29, #144]

0x427ed4 LDR	X5, [X6]

0x427ed8 LDP	X13, X12, [X29, #160]

0x427edc STR	X10, [SP, #216]

0x427ee0 LDP	X11, X10, [X29, #176]

0x427ee4 LDR	X23, [X6, #16]

0x427ee8 LDR	X6, [X7]

0x427eec LDR	X25, [X7, #16]

0x427ef0 MOVZ	W7, #1

0x427ef4 STR	WZR, [SP, #244]

0x427ef8 LDR	X4, [X2]

0x427efc LDR	X27, [X2, #16]

0x427f00 LDR	X2, [X1]

0x427f04 LDR	X19, [X1, #16]

0x427f08 LDR	X1, [X18]

0x427f0c LDR	X20, [X18, #16]

0x427f10 LDR	X18, [X17]

0x427f14 LDR	X24, [X17, #16]

0x427f18 LDR	X17, [X16]

0x427f1c LDR	X26, [X14, #16]

0x427f20 STP	X17, X5, [SP, #200]

0x427f24 LDR	X17, [X16, #16]

0x427f28 LDR	X16, [X15]

0x427f2c LDR	X15, [X15, #16]

0x427f30 STP	X1, X2, [SP, #24]

0x427f34 ADD	X5, SP, #256

0x427f38 MOVZ	W2, #34

0x427f3c LDR	W1, [X0]

0x427f40 ADRP	X0,

0x427f44 ADD	X0, X0, #2400

0x427f48 STP	X4, X6, [SP, #56]

0x427f4c ADD	X4, SP, #264

0x427f50 ADD	X6, SP, #248

0x427f54 STR	X18, [SP, #48]

0x427f58 STR	X15, [SP, #176]

0x427f5c LDR	X15, [X14]

0x427f60 LDR	X14, [X13]

0x427f64 STP	X16, X17, [SP, #184]

0x427f68 STR	W1, [SP, #76]

0x427f6c STP	X14, X15, [SP, #160]

0x427f70 LDR	X14, [X13, #16]

0x427f74 LDR	X13, [X12]

0x427f78 STP	X13, X14, [SP, #144]

0x427f7c LDR	X13, [X12, #16]

0x427f80 LDR	X12, [X11]

0x427f84 LDR	X11, [X11, #16]

0x427f88 STR	X11, [SP, #120]

0x427f8c SUB	W11, W9, W3

0x427f90 MOVN	X9, #0

0x427f94 UMADDL	X28, W11, W8, X9

0x427f98 LDR	X9, [X10]

0x427f9c STP	X11, X3, [SP, #224]

0x427fa0 MOVZ	W8, #1

0x427fa4 ADD	X3, SP, #244

0x427fa8 STP	X12, X13, [SP, #128]

0x427fac STR	X8, [SP, #248]

0x427fb0 STP	X28, XZR, [SP, #256]

0x427fb4 STR	X9, [SP, #112]

0x427fb8 LDR	X9, [X10, #16]

0x427fbc STR	X8, [SP]

0x427fc0 STR	X9, [SP, #40]

0x427fc4 BL	4033a0

0x427fc8 LDP	X8, X14, [SP, #256]

0x427fcc CMP	X8, X28

0x427fd0 CSEL	X9, X8, X28, #11

0x427fd4 CMP	X14, X9

0x427fd8 B.GT	428528

0x427fdc LDR	X6, [X29, #104]

0x427fe0 ADD	X0, X9, #1

0x427fe4 CNTD	X11, ALL

0x427fe8 ORR	X10, XZR, X14

0x427fec SUB	X12, X0, X14

0x427ff0 CMP	X12, X11

0x427ff4 B.CC	4282d4

0x427ff8 DUP	Z1.D, X11

0x427ffc SUB	X8, X29, #64

0x428000 PTRUE	P0.D, ALL

0x428004 STR	Z1, [X8, #511, MUL VL]

0x428008 UDIV	X10, X12, X11

0x42800c LDP	X9, X8, [SP, #216]

0x428010 MADD	X13, X10, X11, XZR

0x428014 ADD	X10, X14, X13

0x428018 SUB	X12, X12, X13

0x42801c INDEX	Z0.D, X14, #1

0x428020 ADD	W14, W22, #2

0x428024 DUP	Z1.D, X9

0x428028 DUP	Z2.D, X8

0x42802c SUB	X8, X29, #64

0x428030 DUP	Z26.D, X14

0x428034 STR	Z1, [X8, #510, MUL VL]

0x428038 LDR	X9, [SP, #232]

0x42803c SUB	X8, X29, #64

0x428040 ADD	W14, W21, #2

0x428044 DUP	Z1.D, X9

0x428048 STR	Z1, [X8, #509, MUL VL]

0x42804c LDR	X8, [SP, #64]

0x428050 LDR	X9, [SP, #208]

0x428054 DUP	Z6.D, X8

0x428058 LDR	X8, [SP, #56]

0x42805c DUP	Z5.D, X9

0x428060 DUP	Z28.D, X14

0x428064 DUP	Z7.D, X8

0x428068 LDP	X8, X17, [SP, #32]

0x42806c DUP	Z16.D, X8

0x428070 LDR	X8, [SP, #24]

0x428074 DUP	Z17.D, X8

0x428078 LDR	X8, [SP, #48]

0x42807c DUP	Z18.D, X8

0x428080 LDR	X8, [SP, #200]

0x428084 DUP	Z19.D, X8

0x428088 LDP	X9, X8, [SP, #176]

0x42808c DUP	Z20.D, X8

0x428090 LDR	X8, [SP, #168]

0x428094 DUP	Z21.D, X8

0x428098 LDP	X14, X8, [SP, #152]

0x42809c DUP	Z22.D, X8

0x4280a0 LDP	X8, X15, [SP, #128]

0x4280a4 DUP	Z23.D, X8

0x4280a8 LDR	X8, [SP, #144]

0x4280ac DUP	Z24.D, X8

0x4280b0 LDP	X8, X16, [SP, #112]

0x4280b4 DUP	Z25.D, X8

0x4280b8 LDR	X8, [SP, #192]

0x4280bc HINT	#0

(202) 0x4280c0 SUB	X18, X29, #64

(202) 0x4280c4 MOVPRFX	Z31, Z0

(202) 0x4280c8 SDIV	Z31.D, P0/M, Z31.D, Z2.D

(202) 0x4280cc MOVPRFX	Z8, Z0

(202) 0x4280d0 MLS	Z8.D, P0/M, Z31.D, Z2.D

(202) 0x4280d4 SUBS	X13, X13, X11

(202) 0x4280d8 LDR	Z1, [X18, #510, MUL VL]

(202) 0x4280dc SUB	X18, X29, #64

(202) 0x4280e0 ADD	Z29.D, Z1.D, Z31.D

(202) 0x4280e4 LDR	Z1, [X18, #509, MUL VL]

(202) 0x4280e8 ADD	Z31.D, Z26.D, Z31.D

(202) 0x4280ec SUB	X18, X29, #64

(202) 0x4280f0 SXTW	Z29.D, P0/M, Z29.D

(202) 0x4280f4 MOVPRFX	Z10, Z5

(202) 0x4280f8 MUL	Z10.D, P0/M, Z10.D, Z29.D

(202) 0x4280fc MOVPRFX	Z12, Z6

(202) 0x428100 MUL	Z12.D, P0/M, Z12.D, Z29.D

(202) 0x428104 SXTW	Z31.D, P0/M, Z31.D

(202) 0x428108 MOVPRFX	Z14, Z6

(202) 0x42810c MUL	Z14.D, P0/M, Z14.D, Z31.D

(202) 0x428110 ADD	Z9.D, Z1.D, Z8.D

(202) 0x428114 MOVPRFX	Z1, Z7

(202) 0x428118 MUL	Z1.D, P0/M, Z1.D, Z31.D

(202) 0x42811c ADD	Z8.D, Z28.D, Z8.D

(202) 0x428120 MOVPRFX	Z30, Z9

(202) 0x428124 SXTW	Z30.D, P0/M, Z9.D

(202) 0x428128 ADR	Z11.D, [Z10, Z9.D,SXTW]

(202) 0x42812c ADR	Z13.D, [Z12, Z9.D,SXTW]

(202) 0x428130 ADR	Z15.D, [Z14, Z9.D,SXTW]

(202) 0x428134 ADR	Z3.D, [Z1, Z9.D,SXTW]

(202) 0x428138 ADR	Z1.D, [Z1, Z8.D,SXTW]

(202) 0x42813c LD1D	{Z11.D}, P0/Z, [X23, Z11.D,LSL #3]

(202) 0x428140 LD1D	{Z13.D}, P0/Z, [X25, Z13.D,LSL #3]

(202) 0x428144 LD1D	{Z15.D}, P0/Z, [X25, Z15.D,LSL #3]

(202) 0x428148 FADD	Z13.D, Z15.D, Z13.D

(202) 0x42814c MOVPRFX	Z15, Z7

(202) 0x428150 MUL	Z15.D, P0/M, Z15.D, Z29.D

(202) 0x428154 ADR	Z27.D, [Z15, Z9.D,SXTW]

(202) 0x428158 LD1D	{Z27.D}, P0/Z, [X27, Z27.D,LSL #3]

(202) 0x42815c LD1D	{Z3.D}, P0/Z, [X27, Z3.D,LSL #3]

(202) 0x428160 LDR	D4, [X6]

(202) 0x428164 FADD	Z3.D, Z27.D, Z3.D

(202) 0x428168 ADR	Z27.D, [Z10, Z8.D,SXTW]

(202) 0x42816c ADR	Z10.D, [Z12, Z8.D,SXTW]

(202) 0x428170 ADR	Z12.D, [Z14, Z8.D,SXTW]

(202) 0x428174 LD1D	{Z27.D}, P0/Z, [X23, Z27.D,LSL #3]

(202) 0x428178 LD1D	{Z10.D}, P0/Z, [X25, Z10.D,LSL #3]

(202) 0x42817c LD1D	{Z12.D}, P0/Z, [X25, Z12.D,LSL #3]

(202) 0x428180 FADD	Z3.D, Z13.D, Z3.D

(202) 0x428184 MOVPRFX	Z13, Z17

(202) 0x428188 MUL	Z13.D, P0/M, Z13.D, Z29.D

(202) 0x42818c ADR	Z14.D, [Z13, Z9.D,SXTW]

(202) 0x428190 ADR	Z13.D, [Z13, Z8.D,SXTW]

(202) 0x428194 FMUL	Z3.D, Z3.D, Z11.D

(202) 0x428198 FADD	Z10.D, Z12.D, Z10.D

(202) 0x42819c ADR	Z12.D, [Z15, Z8.D,SXTW]

(202) 0x4281a0 LD1D	{Z12.D}, P0/Z, [X27, Z12.D,LSL #3]

(202) 0x4281a4 LD1D	{Z1.D}, P0/Z, [X27, Z1.D,LSL #3]

(202) 0x4281a8 FADD	Z1.D, Z12.D, Z1.D

(202) 0x4281ac MOVPRFX	Z12, Z30

(202) 0x4281b0 MLA	Z12.D, P0/M, Z16.D, Z29.D

(202) 0x4281b4 LD1D	{Z12.D}, P0/Z, [X19, Z12.D,LSL #3]

(202) 0x4281b8 LD1D	{Z14.D}, P0/Z, [X20, Z14.D,LSL #3]

(202) 0x4281bc FADD	Z1.D, Z10.D, Z1.D

(202) 0x4281c0 LD1D	{Z10.D}, P0/Z, [X20, Z13.D,LSL #3]

(202) 0x4281c4 MOVPRFX	Z13, Z18

(202) 0x4281c8 MUL	Z13.D, P0/M, Z13.D, Z29.D

(202) 0x4281cc FMUL	Z1.D, Z1.D, Z27.D

(202) 0x4281d0 FADD	Z10.D, Z10.D, Z14.D

(202) 0x4281d4 ADR	Z14.D, [Z13, Z9.D,SXTW]

(202) 0x4281d8 ADR	Z13.D, [Z13, Z8.D,SXTW]

(202) 0x4281dc LD1D	{Z14.D}, P0/Z, [X24, Z14.D,LSL #3]

(202) 0x4281e0 LD1D	{Z13.D}, P0/Z, [X24, Z13.D,LSL #3]

(202) 0x4281e4 FADD	Z13.D, Z14.D, Z13.D

(202) 0x4281e8 MOVPRFX	Z14, Z30

(202) 0x4281ec MLA	Z14.D, P0/M, Z16.D, Z31.D

(202) 0x4281f0 LD1D	{Z27.D}, P0/Z, [X19, Z14.D,LSL #3]

(202) 0x4281f4 MOVPRFX	Z14, Z17

(202) 0x4281f8 MUL	Z14.D, P0/M, Z14.D, Z31.D

(202) 0x4281fc MUL	Z31.D, P0/M, Z31.D, Z18.D

(202) 0x428200 ADR	Z15.D, [Z14, Z9.D,SXTW]

(202) 0x428204 ADR	Z14.D, [Z14, Z8.D,SXTW]

(202) 0x428208 LD1D	{Z15.D}, P0/Z, [X20, Z15.D,LSL #3]

(202) 0x42820c LD1D	{Z14.D}, P0/Z, [X20, Z14.D,LSL #3]

(202) 0x428210 FADD	Z10.D, Z10.D, Z13.D

(202) 0x428214 FMLA	Z3.D, P0/M, Z10.D, Z12.D

(202) 0x428218 ADR	Z9.D, [Z31, Z9.D,SXTW]

(202) 0x42821c ADR	Z31.D, [Z31, Z8.D,SXTW]

(202) 0x428220 FADD	Z14.D, Z14.D, Z15.D

(202) 0x428224 LD1D	{Z8.D}, P0/Z, [X24, Z9.D,LSL #3]

(202) 0x428228 LD1D	{Z31.D}, P0/Z, [X24, Z31.D,LSL #3]

(202) 0x42822c MOVPRFX	Z9, Z30

(202) 0x428230 MLA	Z9.D, P0/M, Z22.D, Z29.D

(202) 0x428234 FADD	Z31.D, Z8.D, Z31.D

(202) 0x428238 FADD	Z31.D, Z14.D, Z31.D

(202) 0x42823c FMLA	Z1.D, P0/M, Z31.D, Z27.D

(202) 0x428240 FMOV	D27, #0.2500000

(202) 0x428244 MOVPRFX	Z31, Z30

(202) 0x428248 MLA	Z31.D, P0/M, Z21.D, Z29.D

(202) 0x42824c FMUL	D4, D4, D27

(202) 0x428250 MOVPRFX	Z27, Z30

(202) 0x428254 MLA	Z27.D, P0/M, Z20.D, Z29.D

(202) 0x428258 FSUB	Z1.D, Z1.D, Z3.D

(202) 0x42825c DUP	Z3.D, Z4.D[0]

(202) 0x428260 MOVPRFX	Z4, Z30

(202) 0x428264 MLA	Z4.D, P0/M, Z19.D, Z29.D

(202) 0x428268 LD1D	{Z4.D}, P0/Z, [X8, Z4.D,LSL #3]

(202) 0x42826c LD1D	{Z27.D}, P0/Z, [X9, Z27.D,LSL #3]

(202) 0x428270 LD1D	{Z8.D}, P0/Z, [X26, Z31.D,LSL #3]

(202) 0x428274 LD1D	{Z9.D}, P0/Z, [X14, Z9.D,LSL #3]

(202) 0x428278 FMUL	Z1.D, Z3.D, Z1.D

(202) 0x42827c FADD	Z3.D, Z9.D, Z27.D

(202) 0x428280 FMUL	Z27.D, Z8.D, Z4.D

(202) 0x428284 FMUL	Z3.D, Z3.D, Z1.D

(202) 0x428288 FADD	Z1.D, Z1.D, Z4.D

(202) 0x42828c FDIV	Z3.D, P0/M, Z3.D, Z27.D

(202) 0x428290 MOVPRFX	Z27, Z30

(202) 0x428294 MLA	Z27.D, P0/M, Z23.D, Z29.D

(202) 0x428298 LD1D	{Z27.D}, P0/Z, [X16, Z27.D,LSL #3]

(202) 0x42829c FSUB	Z3.D, Z27.D, Z3.D

(202) 0x4282a0 MOVPRFX	Z27, Z30

(202) 0x4282a4 MLA	Z27.D, P0/M, Z24.D, Z29.D

(202) 0x4282a8 ST1D	{Z3.D}, P0, [X15, Z27.D,LSL #3]

(202) 0x4282ac LD1D	{Z3.D}, P0/Z, [X26, Z31.D,LSL #3]

(202) 0x4282b0 FMUL	Z3.D, Z3.D, Z4.D

(202) 0x4282b4 LDR	Z4, [X18, #511, MUL VL]

(202) 0x4282b8 FDIVR	Z1.D, P0/M, Z1.D, Z3.D

(202) 0x4282bc MOVPRFX	Z3, Z30

(202) 0x4282c0 MLA	Z3.D, P0/M, Z25.D, Z29.D

(202) 0x4282c4 ADD	Z0.D, Z0.D, Z4.D

(202) 0x4282c8 ST1D	{Z1.D}, P0, [X17, Z3.D,LSL #3]

(202) 0x4282cc B.NE	4280c0

0x4282d0 CBZ	X12, 428528

0x4282d4 LDP	X1, X5, [SP, #224]

0x4282d8 LDP	X21, X22, [SP, #24]

0x4282dc STR	X23, [SP, #80]

0x4282e0 FMOV	D0, #0.2500000

0x4282e4 UBFM	X17, X10, #32, #31

0x4282e8 SBFM	X15, X5, #61, #31

0x4282ec SUB	X8, XZR, X1,LSL #32

0x4282f0 LDP	X18, X16, [SP, #40]

0x4282f4 ADD	X11, X23, X15

0x4282f8 ADD	X12, X25, X15

0x4282fc ADD	X13, X27, X15

0x428300 ADD	X14, X20, X15

0x428304 ADD	X15, X24, X15

0x428308 ADD	X9, X11, #8

0x42830c ADD	X12, X12, #8

0x428310 ADD	X13, X13, #8

0x428314 ADD	X14, X14, #8

0x428318 ADD	X15, X15, #8

0x42831c STP	X8, X9, [SP, #96]

0x428320 SUB	W8, WZR, W1

0x428324 STR	W8, [SP, #92]

0x428328 LDP	X23, X8, [SP, #56]

(201) 0x42832c SDIV	X3, X10, X1

(201) 0x428330 LDP	X11, X9, [SP, #208]

(201) 0x428334 ADD	W1, W5, W10

(201) 0x428338 ADD	X10, X10, #1

(201) 0x42833c CMP	X0, X10

(201) 0x428340 ADD	W4, W9, W3

(201) 0x428344 LDR	W9, [SP, #92]

(201) 0x428348 MADD	W2, W9, W3, W1

(201) 0x42834c SBFM	X1, X4, #0, #31

(201) 0x428350 ORR	X9, XZR, X6

(201) 0x428354 ADD	W4, W4, #1

(201) 0x428358 MADD	X5, X8, X1, XZR

(201) 0x42835c SBFM	X4, X4, #0, #31

(201) 0x428360 MADD	X28, X23, X1, XZR

(201) 0x428364 SBFM	X2, X2, #0, #31

(201) 0x428368 ADD	X6, X5, X2

(201) 0x42836c ADD	X30, X28, X2

(201) 0x428370 LDR	D1, [X25, X6,LSL #3]

(201) 0x428374 MADD	X6, X8, X4, XZR

(201) 0x428378 LDR	D3, [X27, X30,LSL #3]

(201) 0x42837c ADD	X7, X6, X2

(201) 0x428380 LDR	D2, [X25, X7,LSL #3]

(201) 0x428384 MADD	X7, X23, X4, XZR

(201) 0x428388 ADD	X30, X7, X2

(201) 0x42838c FADD	D1, D1, D3

(201) 0x428390 LDR	D4, [X27, X30,LSL #3]

(201) 0x428394 MADD	X30, X11, X1, XZR

(201) 0x428398 LDR	X11, [SP, #96]

(201) 0x42839c MADD	X3, X11, X3, X17

(201) 0x4283a0 LDR	X11, [SP, #80]

(201) 0x4283a4 ADD	X5, X5, X3,ASR #32

(201) 0x4283a8 FADD	D2, D2, D4

(201) 0x4283ac LDR	D5, [X12, X5,LSL #3]

(201) 0x4283b0 ADD	X5, X30, X2

(201) 0x4283b4 FADD	D1, D2, D1

(201) 0x4283b8 LDR	D6, [X11, X5,LSL #3]

(201) 0x4283bc ADD	X5, X6, X3,ASR #32

(201) 0x4283c0 ADD	X6, X28, X3,ASR #32

(201) 0x4283c4 LDR	X28, [SP, #104]

(201) 0x4283c8 LDR	D16, [X13, X6,LSL #3]

(201) 0x4283cc ADD	X6, X7, X3,ASR #32

(201) 0x4283d0 LDR	D7, [X12, X5,LSL #3]

(201) 0x4283d4 ADD	X5, X30, X3,ASR #32

(201) 0x4283d8 LDR	D17, [X13, X6,LSL #3]

(201) 0x4283dc MADD	X6, X21, X1, XZR

(201) 0x4283e0 LDR	D18, [X28, X5,LSL #3]

(201) 0x4283e4 ADD	X5, X6, X3,ASR #32

(201) 0x4283e8 ADD	X7, X6, X2

(201) 0x4283ec FMUL	D1, D1, D6

(201) 0x4283f0 LDR	D20, [X14, X5,LSL #3]

(201) 0x4283f4 MADD	X5, X16, X1, XZR

(201) 0x4283f8 LDR	D19, [X20, X7,LSL #3]

(201) 0x4283fc FADD	D2, D5, D16

(201) 0x428400 ADD	X6, X5, X2

(201) 0x428404 ADD	X5, X5, X3,ASR #32

(201) 0x428408 FADD	D3, D7, D17

(201) 0x42840c LDR	D21, [X24, X6,LSL #3]

(201) 0x428410 MADD	X6, X22, X1, X2

(201) 0x428414 LDR	D22, [X15, X5,LSL #3]

(201) 0x428418 MADD	X5, X21, X4, XZR

(201) 0x42841c FADD	D2, D3, D2

(201) 0x428420 LDR	D23, [X19, X6,LSL #3]

(201) 0x428424 ADD	X6, X5, X2

(201) 0x428428 ADD	X5, X5, X3,ASR #32

(201) 0x42842c FMUL	D2, D2, D18

(201) 0x428430 LDR	D25, [X14, X5,LSL #3]

(201) 0x428434 MADD	X5, X16, X4, XZR

(201) 0x428438 LDR	D24, [X20, X6,LSL #3]

(201) 0x42843c MADD	X4, X22, X4, X2

(201) 0x428440 ADD	X6, X5, X2

(201) 0x428444 FADD	D3, D19, D21

(201) 0x428448 FADD	D4, D20, D22

(201) 0x42844c ADD	X3, X5, X3,ASR #32

(201) 0x428450 LDR	D27, [X19, X4,LSL #3]

(201) 0x428454 LDR	X5, [SP, #232]

(201) 0x428458 LDR	D26, [X24, X6,LSL #3]

(201) 0x42845c ORR	X6, XZR, X9

(201) 0x428460 FADD	D3, D4, D3

(201) 0x428464 LDR	D4, [X9]

(201) 0x428468 LDR	X9, [SP, #200]

(201) 0x42846c LDR	D7, [X15, X3,LSL #3]

(201) 0x428470 FMADD	D1, D3, D23, D1

(201) 0x428474 MADD	X3, X9, X1, X2

(201) 0x428478 LDR	X9, [SP, #192]

(201) 0x42847c FADD	D5, D24, D26

(201) 0x428480 FADD	D7, D25, D7

(201) 0x428484 LDR	D3, [X9, X3,LSL #3]

(201) 0x428488 LDR	X9, [SP, #184]

(201) 0x42848c FADD	D5, D7, D5

(201) 0x428490 FMADD	D2, D5, D27, D2

(201) 0x428494 MADD	X3, X9, X1, X2

(201) 0x428498 LDR	X9, [SP, #176]

(201) 0x42849c FSUB	D1, D2, S1

(201) 0x4284a0 FMUL	D2, D4, D0

(201) 0x4284a4 LDR	D4, [X9, X3,LSL #3]

(201) 0x4284a8 LDR	X9, [SP, #168]

(201) 0x4284ac FMUL	D1, D2, D1

(201) 0x4284b0 MADD	X3, X9, X1, X2

(201) 0x4284b4 LDR	X9, [SP, #160]

(201) 0x4284b8 LDR	D5, [X26, X3,LSL #3]

(201) 0x4284bc MADD	X4, X9, X1, X2

(201) 0x4284c0 LDR	X9, [SP, #152]

(201) 0x4284c4 LDR	D6, [X9, X4,LSL #3]

(201) 0x4284c8 LDR	X9, [SP, #128]

(201) 0x4284cc MADD	X4, X9, X1, X2

(201) 0x4284d0 LDR	X9, [SP, #120]

(201) 0x4284d4 FADD	D2, D6, D4

(201) 0x4284d8 FMUL	D4, D5, D3

(201) 0x4284dc FMUL	D2, D2, D1

(201) 0x4284e0 FADD	D1, D1, D3

(201) 0x4284e4 FDIV	D2, D2, D4

(201) 0x4284e8 LDR	D4, [X9, X4,LSL #3]

(201) 0x4284ec LDR	X9, [SP, #144]

(201) 0x4284f0 MADD	X4, X9, X1, X2

(201) 0x4284f4 LDR	X9, [SP, #136]

(201) 0x4284f8 FSUB	D2, D4, S2

(201) 0x4284fc STR	D2, [X9, X4,LSL #3]

(201) 0x428500 LDR	X9, [SP, #112]

(201) 0x428504 LDR	D2, [X26, X3,LSL #3]

(201) 0x428508 MADD	X1, X9, X1, X2

(201) 0x42850c MOVZ	X9, #1

(201) 0x428510 ADD	X17, X17, X9

(201) 0x428514 FMUL	D2, D2, D3

(201) 0x428518 FDIV	D1, D2, D1

(201) 0x42851c STR	D1, [X18, X1,LSL #3]

(201) 0x428520 LDR	X1, [SP, #224]

(201) 0x428524 B.NE	42832c

0x428528 LDR	W1, [SP, #76]

0x42852c ADRP	X0,

0x428530 ADD	X0, X0, #2424

0x428534 BL	403260

0x428538 ADDVL	SP, SP, #3

0x42853c ADD	SP, SP, #272

0x428540 LDP	D9, D8, [SP, #48]

0x428544 LDP	D11, D10, [SP, #32]

0x428548 LDP	D13, D12, [SP, #16]

0x42854c LDP	X20, X19, [SP, #144]

0x428550 LDP	X22, X21, [SP, #128]

0x428554 LDP	X24, X23, [SP, #112]

0x428558 LDP	X26, X25, [SP, #96]

0x42855c LDP	X28, X27, [SP, #80]

0x428560 LDP	X29, X30, [SP, #64]

0x428564 LDP	D15, D14, [SP], #160

0x428568 RET

0x42856c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	PdV.cpp:69-83
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:69-83

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 35.17 to 22.00 cycles (1.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 37% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 35.17 to 33.67 cycles (1.04x speedup).

Details

28% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 35.17 to 1.00 cycles (35.17x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 744 bytes. The binary function is storing 500 bytes.

General properties

nb instructions	193
loop length	772
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

23.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	18.00	18.00	26.00	18.00	2.50	2.50	2.00	2.00	35.17	34.83	35.00	14.00	14.00
cycles	4.00	4.00	18.00	18.00	26.00	18.00	2.50	2.50	2.00	2.00	35.17	34.83	35.00	14.00	14.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	23.88
Overall L1	35.17

Vectorization ratios

all	28%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 35.17 cycles. At this rate:

22% of peak load performance is reached (21.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
29% of peak store performance is reached (14.22 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 427e60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP D15, D14, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL SP, SP, #61	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB SP, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W10, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 428538 <.omp_outlined..2+0x6d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W21, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 428538 <.omp_outlined..2+0x6d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X17, X16, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X1, X18, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X2, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X15, X14, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X5, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X13, X12, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X10, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X11, X10, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X23, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #244]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X17, X5, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X1, X2, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X5, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463f40>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X4, X6, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, SP, #264	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #248	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X18, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X15, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X16, X17, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W1, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X14, X15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X13, X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W11, W9, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UMADDL X28, W11, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X11, X3, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #244	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X12, X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, XZR, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X14, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X9, X8, X28, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X14, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 428528 <.omp_outlined..2+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X10, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4282d4 <.omp_outlined..2+0x474>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
DUP Z1.D, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR Z1, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
UDIV X10, X12, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
LDP X9, X8, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X13, X10, X11, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X10, X14, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
INDEX Z0.D, X14, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
ADD W14, W22, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z2.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z26.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
STR Z1, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LDR X9, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W14, W21, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
STR Z1, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LDR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z6.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z5.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z28.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z7.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X8, X17, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z16.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z17.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z18.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z19.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X9, X8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z20.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z21.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X14, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z22.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X8, X15, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z23.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z24.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X8, X16, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z25.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
CBZ X12, 428528 <.omp_outlined..2+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X1, X5, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
UBFM X17, X10, #32, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X15, X5, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, XZR, X1,LSL #32	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDP X18, X16, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X11, X23, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X25, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X27, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X20, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X24, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X8, X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, WZR, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #92]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W1, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <46352c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2424	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADDVL SP, SP, #3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD SP, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D15, D14, [SP], #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	PdV.cpp:69-83
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:69-83

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

28% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 35.17 to 1.00 cycles (35.17x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 744 bytes. The binary function is storing 500 bytes.

General properties

nb instructions	193
loop length	772
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

23.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	18.00	18.00	26.00	18.00	2.50	2.50	2.00	2.00	35.17	34.83	35.00	14.00	14.00
cycles	4.00	4.00	18.00	18.00	26.00	18.00	2.50	2.50	2.00	2.00	35.17	34.83	35.00	14.00	14.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	23.88
Overall L1	35.17

Vectorization ratios

all	28%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 35.17 cycles. At this rate:

22% of peak load performance is reached (21.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
29% of peak store performance is reached (14.22 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 427e60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP D15, D14, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL SP, SP, #61	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB SP, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W10, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 428538 <.omp_outlined..2+0x6d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W21, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 428538 <.omp_outlined..2+0x6d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X17, X16, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X1, X18, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X2, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X15, X14, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X5, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X13, X12, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X10, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X11, X10, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X23, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #244]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X17, X5, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X1, X2, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X5, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463f40>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X4, X6, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, SP, #264	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #248	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X18, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X15, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X16, X17, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W1, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X14, X15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X13, X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W11, W9, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UMADDL X28, W11, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X11, X3, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #244	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X12, X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, XZR, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X14, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X9, X8, X28, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X14, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 428528 <.omp_outlined..2+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X10, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4282d4 <.omp_outlined..2+0x474>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
DUP Z1.D, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR Z1, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
UDIV X10, X12, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
LDP X9, X8, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X13, X10, X11, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X10, X14, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
INDEX Z0.D, X14, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
ADD W14, W22, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z2.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z26.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
STR Z1, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LDR X9, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W14, W21, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
STR Z1, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LDR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z6.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z5.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z28.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z7.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X8, X17, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z16.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z17.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z18.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z19.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X9, X8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z20.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z21.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X14, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z22.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X8, X15, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z23.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z24.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X8, X16, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z25.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
CBZ X12, 428528 <.omp_outlined..2+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X1, X5, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
UBFM X17, X10, #32, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X15, X5, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, XZR, X1,LSL #32	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDP X18, X16, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X11, X23, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X25, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X27, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X20, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X24, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X8, X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, WZR, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #92]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W1, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <46352c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2424	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADDVL SP, SP, #3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD SP, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D15, D14, [SP], #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..2#0x427e60–	5.97	3.22
○Loop 202 - PdV.cpp:69-83 - exec	5.97	3.22
○Loop 201 - PdV.cpp:70-83 - exec	0	0

Report Configuration

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Vectorization

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code