OV - exec - Function .omp_outlined.#0x43dc20

	Function: .omp_outlined.#0x43dc20	Module: exec	Source: viscosity.cpp:36-64 [...]	Coverage: 6.05%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp: 36 - 64

--------------------------------------------------------------------------------

36: #pragma omp parallel for simd collapse(2)

37:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

39:       double ugrad = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) - (xvel0(i, j) + xvel0(i + 0, j + 1));

40:       double vgrad = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) - (yvel0(i, j) + yvel0(i + 1, j + 0));

41:       double div = (celldx[i] * (ugrad) + celldy[j] * (vgrad));

42:       double strain2 = 0.5 * (xvel0(i + 0, j + 1) + xvel0(i + 1, j + 1) - xvel0(i, j) - xvel0(i + 1, j + 0)) / celldy[j] +

43:                        0.5 * (yvel0(i + 1, j + 0) + yvel0(i + 1, j + 1) - yvel0(i, j) - yvel0(i + 0, j + 1)) / celldx[i];

44:       double pgradx = (pressure(i + 1, j + 0) - pressure(i - 1, j + 0)) / (celldx[i] + celldx[i + 1]);

45:       double pgrady = (pressure(i + 0, j + 1) - pressure(i + 0, j - 1)) / (celldy[j] + celldy[j + 2]);

46:       double pgradx2 = pgradx * pgradx;

47:       double pgrady2 = pgrady * pgrady;

48:       double limiter = ((0.5 * (ugrad) / celldx[i]) * pgradx2 + (0.5 * (vgrad) / celldy[j]) * pgrady2 + strain2 * pgradx * pgrady) /

49:                        std::fmax(pgradx2 + pgrady2, g_small);

50:       if ((limiter > 0.0) || (div >= 0.0)) {

51:         viscosity(i, j) = 0.0;

52:       } else {

53:         double dirx = 1.0;

54:         if (pgradx < 0.0) dirx = -1.0;

55:         pgradx = dirx * std::fmax(g_small, std::fabs(pgradx));

56:         double diry = 1.0;

57:         if (pgradx < 0.0) diry = -1.0;

58:         pgrady = diry * std::fmax(g_small, std::fabs(pgrady));

59:         double pgrad = std::sqrt(pgradx * pgradx + pgrady * pgrady);

60:         double xgrad = std::fabs(celldx[i] * pgrad / pgradx);

61:         double ygrad = std::fabs(celldy[j] * pgrad / pgrady);

62:         double grad = std::fmin(xgrad, ygrad);

63:         double grad2 = grad * grad;

64:         viscosity(i, j) = 2.0 * density0(i, j) * grad2 * limiter * limiter;

0x43dc20 SUB	SP, SP, #272

0x43dc24 STR	D14, [SP, #112]

0x43dc28 STP	D13, D12, [SP, #128]

0x43dc2c STP	D11, D10, [SP, #144]

0x43dc30 STP	D9, D8, [SP, #160]

0x43dc34 STP	X29, X30, [SP, #176]

0x43dc38 STP	X28, X27, [SP, #192]

0x43dc3c STP	X26, X25, [SP, #208]

0x43dc40 STP	X24, X23, [SP, #224]

0x43dc44 STP	X22, X21, [SP, #240]

0x43dc48 STP	X20, X19, [SP, #256]

0x43dc4c ADD	X29, SP, #176

0x43dc50 LDR	W9, [X2]

0x43dc54 LDR	W8, [X3]

0x43dc58 STR	X9, [SP, #64]

0x43dc5c ADD	W9, W9, #1

0x43dc60 ADD	W8, W8, #2

0x43dc64 SUBS	W8, W8, W9

0x43dc68 STR	X9, [SP, #72]

0x43dc6c B.LE	43dd4c

0x43dc70 LDR	W10, [X4]

0x43dc74 LDR	W9, [X5]

0x43dc78 ADD	W15, W10, #1

0x43dc7c ADD	W9, W9, #2

0x43dc80 STR	X10, [SP, #56]

0x43dc84 CMP	W9, W15

0x43dc88 B.LE	43dd4c

0x43dc8c LDP	X11, X10, [X29, #120]

0x43dc90 LDP	X13, X12, [X29, #104]

0x43dc94 LDR	X14, [X29, #96]

0x43dc98 ADD	X3, SP, #84

0x43dc9c SUB	X4, X29, #56

0x43dca0 SUB	X5, X29, #80

0x43dca4 MOVZ	W2, #34

0x43dca8 LDR	W1, [X0]

0x43dcac LDR	X23, [X6]

0x43dcb0 LDR	X24, [X6, #16]

0x43dcb4 ADRP	X0,

0x43dcb8 ADD	X0, X0, #3136

0x43dcbc ADD	X6, SP, #88

0x43dcc0 LDR	X25, [X7]

0x43dcc4 LDR	X26, [X7, #16]

0x43dcc8 MOVZ	W7, #1

0x43dccc STUR	XZR, [X29, #456]

0x43dcd0 STR	WZR, [SP, #84]

0x43dcd4 LDR	X19, [X12]

0x43dcd8 LDR	X22, [X12, #16]

0x43dcdc LDR	X12, [X11]

0x43dce0 LDR	X21, [X11, #16]

0x43dce4 SUB	W11, W9, W15

0x43dce8 MOVN	X9, #0

0x43dcec LDR	X27, [X14, #8]

0x43dcf0 UMADDL	X20, W11, W8, X9

0x43dcf4 LDR	X9, [X10]

0x43dcf8 LDR	X28, [X13, #8]

0x43dcfc MOVZ	W8, #1

0x43dd00 STR	W1, [SP, #20]

0x43dd04 STR	X8, [SP, #88]

0x43dd08 STP	X12, X11, [SP, #40]

0x43dd0c STUR	X20, [X29, #432]

0x43dd10 STR	X9, [SP, #32]

0x43dd14 LDR	X9, [X10, #16]

0x43dd18 STP	X8, X15, [SP]

0x43dd1c STR	X9, [SP, #24]

0x43dd20 BL	4033a0

0x43dd24 LDUR	X8, [X29, #432]

0x43dd28 LDUR	X13, [X29, #456]

0x43dd2c CMP	X8, X20

0x43dd30 CSEL	X8, X8, X20, #11

0x43dd34 CMP	X13, X8

0x43dd38 B.LE	43dd7c

  (147) 0x43dd3c LDR	W1, [SP, #20]

  (147) 0x43dd40 ADRP	X0,

  (147) 0x43dd44 ADD	X0, X0, #3160

  (147) 0x43dd48 BL	403260

  (147) 0x43dd4c LDP	D9, D8, [SP, #160]

  (147) 0x43dd50 LDP	D11, D10, [SP, #144]

  (147) 0x43dd54 LDP	D13, D12, [SP, #128]

  (147) 0x43dd58 LDR	D14, [SP, #112]

  (147) 0x43dd5c LDP	X20, X19, [SP, #256]

  (147) 0x43dd60 LDP	X22, X21, [SP, #240]

  (147) 0x43dd64 LDP	X24, X23, [SP, #224]

  (147) 0x43dd68 LDP	X26, X25, [SP, #208]

  (147) 0x43dd6c LDP	X28, X27, [SP, #192]

  (147) 0x43dd70 LDP	X29, X30, [SP, #176]

  (147) 0x43dd74 ADD	SP, SP, #272

  (147) 0x43dd78 RET

  (147) 0x43dd7c ADD	X8, X8, #1

  (147) 0x43dd80 CNTD	X10, ALL

  (147) 0x43dd84 ORR	X9, XZR, X13

  (147) 0x43dd88 SUB	X11, X8, X13

  (147) 0x43dd8c CMP	X11, X10

  (147) 0x43dd90 B.CC	43e044

  (147) 0x43dd94 UDIV	X9, X11, X10

  (147) 0x43dd98 LDR	X15, [SP, #32]

  (147) 0x43dd9c PTRUE	P0.D, ALL

  (147) 0x43dda0 DUP	Z23.D, #0

  (147) 0x43dda4 MADD	X12, X9, X10, XZR

  (147) 0x43dda8 INDEX	Z0.D, X13, #1

  (147) 0x43ddac ADD	X9, X13, X12

  (147) 0x43ddb0 DUP	Z18.D, X15

  (147) 0x43ddb4 LDP	X15, X13, [SP, #40]

  (147) 0x43ddb8 SUB	X11, X11, X12

  (147) 0x43ddbc DUP	Z1.D, X10

  (147) 0x43ddc0 DUP	Z5.D, X23

  (147) 0x43ddc4 DUP	Z6.D, X25

  (147) 0x43ddc8 DUP	Z7.D, X19

  (147) 0x43ddcc DUP	Z19.D, X15

  (147) 0x43ddd0 DUP	Z2.D, X13

  (147) 0x43ddd4 LDP	X14, X13, [SP, #64]

  (147) 0x43ddd8 DUP	Z3.D, X13

  (147) 0x43dddc LDR	X13, [SP, #8]

  (147) 0x43dde0 DUP	Z17.D, X14

  (147) 0x43dde4 DUP	Z4.D, X13

  (147) 0x43dde8 LDR	X13, [SP, #56]

  (147) 0x43ddec DUP	Z16.D, X13

  (147) 0x43ddf0 ADD	W13, W13, #2

  (147) 0x43ddf4 DUP	Z20.D, X13

  (147) 0x43ddf8 ADD	W13, W14, #2

  (147) 0x43ddfc DUP	Z21.D, X13

  (147) 0x43de00 ADRP	X13,

  (147) 0x43de04 ADD	X13, X13, #2032

  (147) 0x43de08 LD1RD	{Z22.D}, P0/Z, [X13]

  (147) 0x43de0c ADD	W13, W14, #3

  (147) 0x43de10 DUP	Z24.D, X13

  (147) 0x43de14 LDR	X13, [SP, #24]

  (147) 0x43de18 HINT	#0

  (147) 0x43de1c HINT	#0

    (146) 0x43de20 MOVPRFX	Z26, Z0

    (146) 0x43de24 SDIV	Z26.D, P0/M, Z26.D, Z2.D

    (146) 0x43de28 MOVPRFX	Z29, Z0

    (146) 0x43de2c MLS	Z29.D, P0/M, Z26.D, Z2.D

    (146) 0x43de30 ADD	Z30.D, Z4.D, Z29.D

    (146) 0x43de34 ADD	Z31.D, Z20.D, Z29.D

    (146) 0x43de38 SUBS	X12, X12, X10

    (146) 0x43de3c ADD	Z9.D, Z21.D, Z26.D

    (146) 0x43de40 ADD	Z28.D, Z3.D, Z26.D

    (146) 0x43de44 MOVPRFX	Z25, Z28

    (146) 0x43de48 SXTW	Z25.D, P0/M, Z28.D

    (146) 0x43de4c MOVPRFX	Z27, Z5

    (146) 0x43de50 MUL	Z27.D, P0/M, Z27.D, Z25.D

    (146) 0x43de54 ADD	Z29.D, Z16.D, Z29.D

    (146) 0x43de58 ADD	Z0.D, Z0.D, Z1.D

    (146) 0x43de5c ADR	Z8.D, [Z27, Z31.D,SXTW]

    (146) 0x43de60 LD1D	{Z8.D}, P0/Z, [X24, Z8.D,LSL #3]

    (146) 0x43de64 SXTW	Z9.D, P0/M, Z9.D

    (146) 0x43de68 MOVPRFX	Z10, Z5

    (146) 0x43de6c MUL	Z10.D, P0/M, Z10.D, Z9.D

    (146) 0x43de70 ADR	Z11.D, [Z10, Z31.D,SXTW]

    (146) 0x43de74 ADR	Z27.D, [Z27, Z30.D,SXTW]

    (146) 0x43de78 LD1D	{Z11.D}, P0/Z, [X24, Z11.D,LSL #3]

    (146) 0x43de7c LD1D	{Z27.D}, P0/Z, [X24, Z27.D,LSL #3]

    (146) 0x43de80 MOVPRFX	Z14, Z6

    (146) 0x43de84 MUL	Z14.D, P0/M, Z14.D, Z9.D

    (146) 0x43de88 ADR	Z10.D, [Z10, Z30.D,SXTW]

    (146) 0x43de8c LD1D	{Z10.D}, P0/Z, [X24, Z10.D,LSL #3]

    (146) 0x43de90 FADD	Z12.D, Z11.D, Z8.D

    (146) 0x43de94 FADD	Z13.D, Z27.D, Z10.D

    (146) 0x43de98 FADD	Z27.D, Z8.D, Z27.D

    (146) 0x43de9c ADR	Z8.D, [Z14, Z30.D,SXTW]

    (146) 0x43dea0 ADR	Z14.D, [Z14, Z31.D,SXTW]

    (146) 0x43dea4 FSUB	Z27.D, Z11.D, Z27.D

    (146) 0x43dea8 MOVPRFX	Z11, Z6

    (146) 0x43deac MUL	Z11.D, P0/M, Z11.D, Z25.D

    (146) 0x43deb0 FSUB	Z12.D, Z12.D, Z13.D

    (146) 0x43deb4 ADR	Z13.D, [Z11, Z30.D,SXTW]

    (146) 0x43deb8 LD1D	{Z8.D}, P0/Z, [X26, Z8.D,LSL #3]

    (146) 0x43debc LD1D	{Z14.D}, P0/Z, [X26, Z14.D,LSL #3]

    (146) 0x43dec0 ADR	Z11.D, [Z11, Z31.D,SXTW]

    (146) 0x43dec4 LD1D	{Z13.D}, P0/Z, [X26, Z13.D,LSL #3]

    (146) 0x43dec8 FADD	Z10.D, Z27.D, Z10.D

    (146) 0x43decc LD1D	{Z11.D}, P0/Z, [X26, Z11.D,LSL #3]

    (146) 0x43ded0 FADD	Z27.D, Z14.D, Z8.D

    (146) 0x43ded4 FMUL	Z10.D, P0/M, Z10.D, #0

    (146) 0x43ded8 FADD	Z8.D, Z8.D, Z13.D

    (146) 0x43dedc FADD	Z13.D, Z13.D, Z11.D

    (146) 0x43dee0 FSUB	Z8.D, Z14.D, Z8.D

    (146) 0x43dee4 FSUB	Z13.D, Z27.D, Z13.D

    (146) 0x43dee8 MOVPRFX	Z27, Z30

    (146) 0x43deec SXTW	Z27.D, P0/M, Z30.D

    (146) 0x43def0 LD1D	{Z30.D}, P0/Z, [X27, Z30.D,SXTW #3]

    (146) 0x43def4 LD1D	{Z28.D}, P0/Z, [X28, Z28.D,SXTW #3]

    (146) 0x43def8 FADD	Z8.D, Z8.D, Z11.D

    (146) 0x43defc MOVPRFX	Z11, Z7

    (146) 0x43df00 MUL	Z11.D, P0/M, Z11.D, Z25.D

    (146) 0x43df04 ADR	Z29.D, [Z11, Z29.D,SXTW]

    (146) 0x43df08 ADR	Z11.D, [Z11, Z31.D,SXTW]

    (146) 0x43df0c LD1D	{Z11.D}, P0/Z, [X22, Z11.D,LSL #3]

    (146) 0x43df10 LD1D	{Z29.D}, P0/Z, [X22, Z29.D,LSL #3]

    (146) 0x43df14 LD1D	{Z31.D}, P0/Z, [X27, Z31.D,SXTW #3]

    (146) 0x43df18 FMUL	Z8.D, P0/M, Z8.D, #0

    (146) 0x43df1c FDIV	Z10.D, P0/M, Z10.D, Z28.D

    (146) 0x43df20 FDIV	Z8.D, P0/M, Z8.D, Z30.D

    (146) 0x43df24 FSUB	Z29.D, Z11.D, Z29.D

    (146) 0x43df28 FADD	Z31.D, Z31.D, Z30.D

    (146) 0x43df2c MOVPRFX	Z11, Z13

    (146) 0x43df30 FMUL	Z11.D, P0/M, Z11.D, #0

    (146) 0x43df34 FDIV	Z29.D, P0/M, Z29.D, Z31.D

    (146) 0x43df38 MOVPRFX	Z31, Z27

    (146) 0x43df3c MLA	Z31.D, P0/M, Z7.D, Z9.D

    (146) 0x43df40 ADD	Z9.D, Z17.D, Z26.D

    (146) 0x43df44 ADD	Z26.D, Z24.D, Z26.D

    (146) 0x43df48 LD1D	{Z31.D}, P0/Z, [X22, Z31.D,LSL #3]

    (146) 0x43df4c SXTW	Z9.D, P0/M, Z9.D

    (146) 0x43df50 MAD	Z9.D, P0/M, Z7.D, Z27.D

    (146) 0x43df54 LD1D	{Z9.D}, P0/Z, [X22, Z9.D,LSL #3]

    (146) 0x43df58 LD1D	{Z26.D}, P0/Z, [X28, Z26.D,SXTW #3]

    (146) 0x43df5c FSUB	Z31.D, Z31.D, Z9.D

    (146) 0x43df60 FADD	Z26.D, Z26.D, Z28.D

    (146) 0x43df64 FDIVR	Z26.D, P0/M, Z26.D, Z31.D

    (146) 0x43df68 FADD	Z31.D, Z8.D, Z10.D

    (146) 0x43df6c FMUL	Z8.D, Z29.D, Z29.D

    (146) 0x43df70 MOVPRFX	Z10, Z12

    (146) 0x43df74 FMUL	Z10.D, P0/M, Z10.D, #0

    (146) 0x43df78 FCMLT	P2.D, P0/Z, Z29.D, #0

    (146) 0x43df7c FMUL	Z31.D, Z29.D, Z31.D

    (146) 0x43df80 FABS	Z29.D, P0/M, Z29.D

    (146) 0x43df84 FMUL	Z10.D, Z10.D, Z8.D

    (146) 0x43df88 FMAXNM	Z29.D, P0/M, Z29.D, Z22.D

    (146) 0x43df8c FDIV	Z10.D, P0/M, Z10.D, Z30.D

    (146) 0x43df90 FMUL	Z9.D, Z26.D, Z26.D

    (146) 0x43df94 FMUL	Z11.D, Z11.D, Z9.D

    (146) 0x43df98 FADD	Z8.D, Z9.D, Z8.D

    (146) 0x43df9c MOVPRFX	Z9, Z29

    (146) 0x43dfa0 FNEG	Z9.D, P0/M, Z29.D

    (146) 0x43dfa4 SEL	Z29.D, P2, Z9.D, Z29.D

    (146) 0x43dfa8 FMAXNM	Z8.D, P0/M, Z8.D, Z22.D

    (146) 0x43dfac FCMLT	P2.D, P0/Z, Z29.D, #0

    (146) 0x43dfb0 FDIV	Z11.D, P0/M, Z11.D, Z28.D

    (146) 0x43dfb4 FMAD	Z31.D, P0/M, Z26.D, Z10.D

    (146) 0x43dfb8 FABS	Z26.D, P0/M, Z26.D

    (146) 0x43dfbc FMAXNM	Z26.D, P0/M, Z26.D, Z22.D

    (146) 0x43dfc0 MOVPRFX	Z9, Z26

    (146) 0x43dfc4 FNEG	Z9.D, P0/M, Z26.D

    (146) 0x43dfc8 SEL	Z26.D, P2, Z9.D, Z26.D

    (146) 0x43dfcc FMUL	Z9.D, Z29.D, Z29.D

    (146) 0x43dfd0 FMLA	Z9.D, P0/M, Z26.D, Z26.D

    (146) 0x43dfd4 FADD	Z31.D, Z31.D, Z11.D

    (146) 0x43dfd8 FDIV	Z31.D, P0/M, Z31.D, Z8.D

    (146) 0x43dfdc FMUL	Z8.D, Z30.D, Z12.D

    (146) 0x43dfe0 FMLA	Z8.D, P0/M, Z28.D, Z13.D

    (146) 0x43dfe4 FCMLE	P1.D, P0/Z, Z31.D, #0

    (146) 0x43dfe8 FCMLT	P1.D, P1/Z, Z8.D, #0

    (146) 0x43dfec MOVPRFX	Z8, Z9

    (146) 0x43dff0 FSQRT	Z8.D, P0/M, Z9.D

    (146) 0x43dff4 FMUL	Z28.D, Z8.D, Z28.D

    (146) 0x43dff8 FMUL	Z30.D, Z8.D, Z30.D

    (146) 0x43dffc FDIVR	Z26.D, P0/M, Z26.D, Z28.D

    (146) 0x43e000 FDIVR	Z29.D, P0/M, Z29.D, Z30.D

    (146) 0x43e004 MOVPRFX	Z28, Z29

    (146) 0x43e008 FABS	Z28.D, P0/M, Z29.D

    (146) 0x43e00c FABS	Z26.D, P0/M, Z26.D

    (146) 0x43e010 FMINNM	Z26.D, P0/M, Z26.D, Z28.D

    (146) 0x43e014 MOVPRFX	Z28, Z27

    (146) 0x43e018 MLA	Z28.D, P0/M, Z18.D, Z25.D

    (146) 0x43e01c LD1D	{Z28.D}, P1/Z, [X13, Z28.D,LSL #3]

    (146) 0x43e020 MAD	Z25.D, P0/M, Z19.D, Z27.D

    (146) 0x43e024 FMUL	Z26.D, Z26.D, Z31.D

    (146) 0x43e028 FADD	Z28.D, Z28.D, Z28.D

    (146) 0x43e02c FMUL	Z26.D, Z26.D, Z26.D

    (146) 0x43e030 FMUL	Z26.D, Z26.D, Z28.D

    (146) 0x43e034 SEL	Z26.D, P1, Z26.D, Z23.D

    (146) 0x43e038 ST1D	{Z26.D}, P0, [X21, Z25.D,LSL #3]

    (146) 0x43e03c B.NE	43de20

  (147) 0x43e040 CBZ	X11, 43dd3c

(145) 0x43e044 LDR	X10, [SP, #8]

(145) 0x43e048 LDR	X13, [SP, #72]

(145) 0x43e04c ADRP	X17, 43e04c

(145) 0x43e050 LDR	X16, [SP, #48]

(145) 0x43e054 FMOV	D0, #0.5000000

(145) 0x43e058 UBFM	X15, X9, #32, #31

(145) 0x43e05c SBFM	X12, X10, #61, #31

(145) 0x43e060 LDR	D1, [X17, #2032]

(145) 0x43e064 ADD	X13, X28, W13,SXTW #3

(145) 0x43e068 SUB	X14, XZR, X16,LSL #32

(145) 0x43e06c SUB	W16, WZR, W16

(145) 0x43e070 MOVZ	X17, #1

(145) 0x43e074 ADD	X10, X24, X12

(145) 0x43e078 ADD	X11, X26, X12

(145) 0x43e07c ADD	X12, X22, X12

(145) 0x43e080 ADD	X13, X13, #16

(145) 0x43e084 ADD	X10, X10, #8

(145) 0x43e088 ADD	X11, X11, #8

(145) 0x43e08c ADD	X12, X12, #8

(145) 0x43e090 B	43e0bc

0x43e094 HINT	#0

0x43e098 HINT	#0

0x43e09c HINT	#0

(145) 0x43e0a0 LDR	X1, [SP, #40]

(145) 0x43e0a4 ADD	X9, X9, #1

(145) 0x43e0a8 ADD	X15, X15, X17

(145) 0x43e0ac CMP	X8, X9

(145) 0x43e0b0 MADD	X18, X1, X18, X0

(145) 0x43e0b4 STR	D17, [X21, X18,LSL #3]

(145) 0x43e0b8 B.EQ	43dd3c

(145) 0x43e0bc LDR	X18, [SP, #48]

(145) 0x43e0c0 SDIV	X1, X9, X18

(145) 0x43e0c4 LDR	X18, [SP, #72]

(145) 0x43e0c8 ADD	W2, W18, W1

(145) 0x43e0cc LDR	X18, [SP, #56]

(145) 0x43e0d0 MADD	X7, X14, X1, X15

(145) 0x43e0d4 ADD	W18, W18, W9

(145) 0x43e0d8 MADD	W3, W16, W1, W18

(145) 0x43e0dc SBFM	X18, X2, #0, #31

(145) 0x43e0e0 MADD	X6, X23, X18, XZR

(145) 0x43e0e4 ADD	W4, W3, #1

(145) 0x43e0e8 ADD	W5, W3, #2

(145) 0x43e0ec ADD	X0, X6, X7,ASR #32

(145) 0x43e0f0 LDR	D6, [X10, X0,LSL #3]

(145) 0x43e0f4 ADD	W0, W2, #1

(145) 0x43e0f8 SBFM	X20, X0, #0, #31

(145) 0x43e0fc MADD	X30, X23, X20, XZR

(145) 0x43e100 ADD	X0, X30, X7,ASR #32

(145) 0x43e104 LDR	D7, [X10, X0,LSL #3]

(145) 0x43e108 SBFM	X0, X4, #0, #31

(145) 0x43e10c ADD	X6, X6, X0

(145) 0x43e110 LDR	D16, [X24, X6,LSL #3]

(145) 0x43e114 ADD	X6, X30, X0

(145) 0x43e118 LDR	D17, [X24, X6,LSL #3]

(145) 0x43e11c MADD	X6, X25, X20, XZR

(145) 0x43e120 FADD	D2, D7, D6

(145) 0x43e124 ADD	X30, X6, X0

(145) 0x43e128 ADD	X6, X6, X7,ASR #32

(145) 0x43e12c LDR	D19, [X11, X6,LSL #3]

(145) 0x43e130 MADD	X6, X25, X18, XZR

(145) 0x43e134 LDR	D18, [X26, X30,LSL #3]

(145) 0x43e138 FADD	D6, D6, D16

(145) 0x43e13c ADD	X30, X6, X0

(145) 0x43e140 ADD	X6, X6, X7,ASR #32

(145) 0x43e144 FADD	D3, D16, D17

(145) 0x43e148 FSUB	D6, D7, S6

(145) 0x43e14c LDR	D20, [X26, X30,LSL #3]

(145) 0x43e150 LDR	D21, [X11, X6,LSL #3]

(145) 0x43e154 FSUB	D4, D2, S3

(145) 0x43e158 FADD	D6, D6, D17

(145) 0x43e15c FADD	D2, D19, D18

(145) 0x43e160 FMUL	D6, D6, D0

(145) 0x43e164 FADD	D7, D18, D20

(145) 0x43e168 FADD	D3, D20, D21

(145) 0x43e16c FSUB	D7, D19, S7

(145) 0x43e170 FSUB	D5, D2, S3

(145) 0x43e174 LDR	D3, [X27, X4,SXTW #3]

(145) 0x43e178 LDR	D2, [X28, X2,SXTW #3]

(145) 0x43e17c MADD	X2, X19, X18, XZR

(145) 0x43e180 FMUL	D19, D4, D0

(145) 0x43e184 FADD	D7, D7, D21

(145) 0x43e188 ADD	X4, X2, X7,ASR #32

(145) 0x43e18c ADD	X2, X2, W3,SXTW

(145) 0x43e190 FMUL	D20, D5, D0

(145) 0x43e194 FMUL	D7, D7, D0

(145) 0x43e198 LDR	D16, [X22, X2,LSL #3]

(145) 0x43e19c MADD	X2, X19, X20, X0

(145) 0x43e1a0 FDIV	D6, D6, D2

(145) 0x43e1a4 FDIV	D7, D7, D3

(145) 0x43e1a8 FADD	D7, D7, D6

(145) 0x43e1ac LDR	D6, [X12, X4,LSL #3]

(145) 0x43e1b0 FSUB	D6, D6, S16

(145) 0x43e1b4 LDR	D16, [X27, X5,SXTW #3]

(145) 0x43e1b8 FADD	D16, D16, D3

(145) 0x43e1bc FDIV	D6, D6, D16

(145) 0x43e1c0 LDR	D16, [X22, X2,LSL #3]

(145) 0x43e1c4 LDR	X2, [SP, #64]

(145) 0x43e1c8 ADD	W2, W2, W1

(145) 0x43e1cc SBFM	X1, X1, #61, #31

(145) 0x43e1d0 SBFM	X2, X2, #0, #31

(145) 0x43e1d4 MADD	X2, X19, X2, X0

(145) 0x43e1d8 LDR	D17, [X22, X2,LSL #3]

(145) 0x43e1dc FSUB	D16, D16, S17

(145) 0x43e1e0 LDR	D17, [X13, X1]

(145) 0x43e1e4 FADD	D17, D17, D2

(145) 0x43e1e8 FDIV	D16, D16, D17

(145) 0x43e1ec FMUL	D17, D6, D6

(145) 0x43e1f0 FMUL	D19, D19, D17

(145) 0x43e1f4 FDIV	D19, D19, D3

(145) 0x43e1f8 FMUL	D18, D16, D16

(145) 0x43e1fc FMUL	D21, D6, D16

(145) 0x43e200 FMUL	D20, D20, D18

(145) 0x43e204 FADD	D17, D18, D17

(145) 0x43e208 FMAXNM	D17, D17, D1

(145) 0x43e20c FDIV	D20, D20, D2

(145) 0x43e210 FMADD	D7, D21, D7, D19

(145) 0x43e214 FADD	D7, D7, D20

(145) 0x43e218 FDIV	D7, D7, D17

(145) 0x43e21c MOVI	D17, #0

(145) 0x43e220 FCMP	D7, #0

(145) 0x43e224 B.GT	43e0a0

(145) 0x43e228 FMUL	D4, D3, D4

(145) 0x43e22c FMADD	D4, D2, D5, D4

(145) 0x43e230 FCMP	D4, #0

(145) 0x43e234 B.GE	43e0a0

(145) 0x43e238 FABS	D4, D6

(145) 0x43e23c FCMP	D6, #0

(145) 0x43e240 LDP	X2, X1, [SP, #24]

(145) 0x43e244 MADD	X1, X1, X18, X0

(145) 0x43e248 FMAXNM	D4, D4, D1

(145) 0x43e24c FNEG	D5, D4

(145) 0x43e250 FCSEL	D4, D5, D4, #11

(145) 0x43e254 FABS	D5, D16

(145) 0x43e258 FMAXNM	D5, D5, D1

(145) 0x43e25c FCMP	D4, #0

(145) 0x43e260 FNEG	D6, D5

(145) 0x43e264 FCSEL	D5, D6, D5, #11

(145) 0x43e268 FMUL	D6, D4, D4

(145) 0x43e26c FMADD	D6, D5, D5, D6

(145) 0x43e270 FSQRT	D6, D6

(145) 0x43e274 FMUL	D3, D6, D3

(145) 0x43e278 FMUL	D2, D6, D2

(145) 0x43e27c FDIV	D3, D3, D4

(145) 0x43e280 FDIV	D2, D2, D5

(145) 0x43e284 FABS	D3, D3

(145) 0x43e288 FABS	D2, D2

(145) 0x43e28c FMINNM	D2, D3, D2

(145) 0x43e290 LDR	D3, [X2, X1,LSL #3]

(145) 0x43e294 FMUL	D2, D2, D7

(145) 0x43e298 FMUL	D2, D2, D2

(145) 0x43e29c FADD	D3, D3, D3

(145) 0x43e2a0 FMUL	D17, D2, D3

(145) 0x43e2a4 B	43e0a0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	viscosity.cpp:36-64
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp:36-64

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.67 to 2.33 cycles (6.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 27% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 14.67 to 2.25 cycles (6.52x speedup).

Details

27% of VPU instructions are used in vector version (process two or more data elements in vector registers):

75% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.67 to 0.50 cycles (29.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 172 bytes. The binary function is storing 256 bytes.

General properties

nb instructions	74
loop length	296
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	6.00	6.00	6.00	6.00	2.00	2.00	0.00	0.00	14.67	14.67	14.67	9.00	9.00
cycles	2.00	2.00	6.00	6.00	6.00	6.00	2.00	2.00	0.00	0.00	14.67	14.67	14.67	9.00	9.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.88
Overall L1	14.67

Vectorization ratios

all	27%
load	NA (no load vectorizable/vectorized instructions)
store	75%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.67 cycles. At this rate:

12% of peak load performance is reached (11.73 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
36% of peak store performance is reached (17.45 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 43dc20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D14, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D13, D12, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D11, D10, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D9, D8, [SP, #160]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR X9, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LE 43dd4c <.omp_outlined.+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W10, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W15, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X10, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W9, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 43dd4c <.omp_outlined.+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X13, X12, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X14, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, SP, #84	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <465cb4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3136	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X25, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR XZR, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X19, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W11, W9, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X27, [X14, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UMADDL X20, W11, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X13, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X12, X11, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X20, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X15, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X8, X8, X20, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 43dd7c <.omp_outlined.+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	viscosity.cpp:36-64
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp:36-64

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.67 to 2.33 cycles (6.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

27% of VPU instructions are used in vector version (process two or more data elements in vector registers):

75% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.67 to 0.50 cycles (29.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 172 bytes. The binary function is storing 256 bytes.

General properties

nb instructions	74
loop length	296
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	6.00	6.00	6.00	6.00	2.00	2.00	0.00	0.00	14.67	14.67	14.67	9.00	9.00
cycles	2.00	2.00	6.00	6.00	6.00	6.00	2.00	2.00	0.00	0.00	14.67	14.67	14.67	9.00	9.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.88
Overall L1	14.67

Vectorization ratios

all	27%
load	NA (no load vectorizable/vectorized instructions)
store	75%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.67 cycles. At this rate:

12% of peak load performance is reached (11.73 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
36% of peak store performance is reached (17.45 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 43dc20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D14, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D13, D12, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D11, D10, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D9, D8, [SP, #160]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W9, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR X9, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LE 43dd4c <.omp_outlined.+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W10, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W15, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X10, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W9, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 43dd4c <.omp_outlined.+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X13, X12, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X14, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, SP, #84	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <465cb4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3136	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X25, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR XZR, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X19, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W11, W9, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X27, [X14, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UMADDL X20, W11, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X13, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X12, X11, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X20, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X15, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X8, X8, X20, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 43dd7c <.omp_outlined.+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined.#0x43dc20–	6.05	3.27
▼Loop 145 - viscosity.cpp:36-64 - exec–	0	0
▼Loop 147 - viscosity.cpp:36-64 - exec–	0	0
○Loop 146 - viscosity.cpp:37-64 - exec	6.05	3.27

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code