OV - exec - Function .omp_outlined.#0x428f40

	Function: .omp_outlined.#0x428f40	Module: exec	Source: revert.cpp:34-38 [...]	Coverage: 1.33%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

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69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/revert.cpp: 34 - 38

--------------------------------------------------------------------------------

34: #pragma omp parallel for simd collapse(2)

35:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

36:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

37:       density1(i, j) = density0(i, j);

38:       energy1(i, j) = energy0(i, j);

0x428f40 SUB	SP, SP, #160

0x428f44 STP	X29, X30, [SP, #64]

0x428f48 STP	X28, X27, [SP, #80]

0x428f4c STP	X26, X25, [SP, #96]

0x428f50 STP	X24, X23, [SP, #112]

0x428f54 STP	X22, X21, [SP, #128]

0x428f58 STP	X20, X19, [SP, #144]

0x428f5c ADD	X29, SP, #64

0x428f60 LDR	W8, [X2]

0x428f64 LDR	W9, [X3]

0x428f68 LDR	W10, [X4]

0x428f6c ADD	W20, W8, #1

0x428f70 LDR	W11, [X5]

0x428f74 ADD	W8, W9, #2

0x428f78 ADD	W21, W10, #1

0x428f7c ADD	W9, W11, #2

0x428f80 SUBS	W8, W8, W20

0x428f84 CCMP	W9, W21, #4, #12

0x428f88 B.LE	429120

0x428f8c LDP	X11, X10, [X29, #96]

0x428f90 LDR	X12, [X6]

0x428f94 SUB	W22, W9, W21

0x428f98 MOVN	X9, #0

0x428f9c LDR	W1, [X0]

0x428fa0 ADRP	X0,

0x428fa4 ADD	X0, X0, #2616

0x428fa8 SUB	X3, X29, #28

0x428fac LDR	X23, [X6, #16]

0x428fb0 LDR	X24, [X7]

0x428fb4 LDR	X25, [X7, #16]

0x428fb8 SUB	X4, X29, #8

0x428fbc SUB	X5, X29, #16

0x428fc0 SUB	X6, X29, #24

0x428fc4 MOVZ	W2, #34

0x428fc8 STUR	WZR, [X29, #484]

0x428fcc MOVZ	W7, #1

0x428fd0 LDR	X26, [X11]

0x428fd4 LDR	X27, [X11, #16]

0x428fd8 LDR	X28, [X10]

0x428fdc LDR	X19, [X10, #16]

0x428fe0 UMADDL	X8, W22, W8, X9

0x428fe4 STP	X12, X8, [SP, #16]

0x428fe8 STP	X8, XZR, [X29, #1008]

0x428fec MOVZ	W8, #1

0x428ff0 STR	W1, [SP, #32]

0x428ff4 STUR	X8, [X29, #488]

0x428ff8 STR	X8, [SP]

0x428ffc BL	4033a0

0x429000 LDP	X8, X13, [X29, #1008]

0x429004 LDR	X9, [SP, #24]

0x429008 CMP	X8, X9

0x42900c CSEL	X8, X8, X9, #11

0x429010 CMP	X13, X8

0x429014 B.GT	429110

0x429018 ADD	X8, X8, #1

0x42901c CNTD	X10, ALL

0x429020 ORR	X9, XZR, X13

0x429024 SUB	X11, X8, X13

0x429028 CMP	X11, X10

0x42902c B.CC	4290c4

0x429030 UDIV	X9, X11, X10

0x429034 PTRUE	P0.D, ALL

0x429038 MADD	X12, X9, X10, XZR

0x42903c INDEX	Z0.D, X13, #1

0x429040 ADD	X9, X13, X12

0x429044 LDR	X13, [SP, #16]

0x429048 DUP	Z1.D, X10

0x42904c SUB	X11, X11, X12

0x429050 DUP	Z2.D, X22

0x429054 DUP	Z3.D, X20

0x429058 DUP	Z4.D, X21

0x42905c DUP	Z5.D, X24

0x429060 DUP	Z7.D, X28

0x429064 DUP	Z16.D, X26

0x429068 DUP	Z6.D, X13

(156) 0x42906c MOVPRFX	Z17, Z0

(156) 0x429070 SDIV	Z17.D, P0/M, Z17.D, Z2.D

(156) 0x429074 ADD	Z18.D, Z3.D, Z17.D

(156) 0x429078 MSB	Z17.D, P0/M, Z2.D, Z0.D

(156) 0x42907c ADD	Z0.D, Z0.D, Z1.D

(156) 0x429080 SUBS	X12, X12, X10

(156) 0x429084 SXTW	Z18.D, P0/M, Z18.D

(156) 0x429088 ADD	Z17.D, Z4.D, Z17.D

(156) 0x42908c SXTW	Z17.D, P0/M, Z17.D

(156) 0x429090 MOVPRFX	Z19, Z17

(156) 0x429094 MLA	Z19.D, P0/M, Z5.D, Z18.D

(156) 0x429098 LD1D	{Z19.D}, P0/Z, [X25, Z19.D,LSL #3]

(156) 0x42909c MOVPRFX	Z20, Z17

(156) 0x4290a0 MLA	Z20.D, P0/M, Z6.D, Z18.D

(156) 0x4290a4 ST1D	{Z19.D}, P0, [X23, Z20.D,LSL #3]

(156) 0x4290a8 MOVPRFX	Z19, Z17

(156) 0x4290ac MLA	Z19.D, P0/M, Z7.D, Z18.D

(156) 0x4290b0 MLA	Z17.D, P0/M, Z16.D, Z18.D

(156) 0x4290b4 LD1D	{Z19.D}, P0/Z, [X19, Z19.D,LSL #3]

(156) 0x4290b8 ST1D	{Z19.D}, P0, [X27, Z17.D,LSL #3]

(156) 0x4290bc B.NE	42906c

0x4290c0 CBZ	X11, 429110

0x4290c4 LDR	X14, [SP, #16]

0x4290c8 SUB	W10, WZR, W22

(155) 0x4290cc SDIV	X11, X9, X22

(155) 0x4290d0 ADD	W13, W21, W9

(155) 0x4290d4 ADD	X9, X9, #1

(155) 0x4290d8 CMP	X8, X9

(155) 0x4290dc ADD	W12, W20, W11

(155) 0x4290e0 MADD	W11, W10, W11, W13

(155) 0x4290e4 SBFM	X11, X11, #0, #31

(155) 0x4290e8 SBFM	X12, X12, #0, #31

(155) 0x4290ec MADD	X13, X24, X12, X11

(155) 0x4290f0 LDR	D0, [X25, X13,LSL #3]

(155) 0x4290f4 MADD	X13, X14, X12, X11

(155) 0x4290f8 STR	D0, [X23, X13,LSL #3]

(155) 0x4290fc MADD	X13, X28, X12, X11

(155) 0x429100 MADD	X11, X26, X12, X11

(155) 0x429104 LDR	D0, [X19, X13,LSL #3]

(155) 0x429108 STR	D0, [X27, X11,LSL #3]

(155) 0x42910c B.NE	4290cc

0x429110 LDR	W1, [SP, #32]

0x429114 ADRP	X0,

0x429118 ADD	X0, X0, #2640

0x42911c BL	403260

0x429120 LDP	X20, X19, [SP, #144]

0x429124 LDP	X22, X21, [SP, #128]

0x429128 LDP	X24, X23, [SP, #112]

0x42912c LDP	X26, X25, [SP, #96]

0x429130 LDP	X28, X27, [SP, #80]

0x429134 LDP	X29, X30, [SP, #64]

0x429138 ADD	SP, SP, #160

0x42913c RET

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	revert.cpp:34-38
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/revert.cpp:34-38

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.00 to 9.00 cycles (1.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 13.00 to 12.33 cycles (1.05x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.00 to 1.00 cycles (13.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 240 bytes. The binary function is storing 152 bytes.

General properties

nb instructions	90
loop length	360
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	11.50	11.25	13.00	11.25	1.00	0.00	0.00	0.00	12.33	12.33	12.33	6.00	6.00
cycles	3.50	3.50	11.50	11.25	13.00	11.25	1.00	0.00	0.00	0.00	12.33	12.33	12.33	6.00	6.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	11.25
Overall L1	13.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.00 cycles. At this rate:

19% of peak load performance is reached (18.46 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (11.69 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 428f40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR W8, [X2]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W10, [X4]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W20, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR W11, [X5]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD W21, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD W9, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUBS W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
CCMP W9, W21, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
B.LE 429120 <.omp_outlined.+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X29, #96]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X12, [X6]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W22, W9, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463fa0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2616	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR X23, [X6, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X7]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X7, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR X26, [X11]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X11, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X10]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X10, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UMADDL X8, W22, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
STP X12, X8, [SP, #16]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
STR W1, [SP, #32]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X13, [X29, #1008]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X9, [SP, #24]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
CSEL X8, X8, X9, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.GT 429110 <.omp_outlined.+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CNTD X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ORR X9, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB X11, X8, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.CC 4290c4 <.omp_outlined.+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X9, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	5-20	1-0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
MADD X12, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
INDEX Z0.D, X13, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD X9, X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR X13, [SP, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z1.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
DUP Z2.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z3.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z4.D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z5.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z7.D, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z16.D, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z6.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
CBZ X11, 429110 <.omp_outlined.+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [SP, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W10, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR W1, [SP, #32]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463114>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2640	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	revert.cpp:34-38
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/revert.cpp:34-38

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.00 to 9.00 cycles (1.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.00 to 1.00 cycles (13.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 240 bytes. The binary function is storing 152 bytes.

General properties

nb instructions	90
loop length	360
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	11.50	11.25	13.00	11.25	1.00	0.00	0.00	0.00	12.33	12.33	12.33	6.00	6.00
cycles	3.50	3.50	11.50	11.25	13.00	11.25	1.00	0.00	0.00	0.00	12.33	12.33	12.33	6.00	6.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	11.25
Overall L1	13.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.00 cycles. At this rate:

19% of peak load performance is reached (18.46 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (11.69 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 428f40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR W8, [X2]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W10, [X4]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W20, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR W11, [X5]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD W21, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD W9, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUBS W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
CCMP W9, W21, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
B.LE 429120 <.omp_outlined.+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X29, #96]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X12, [X6]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W22, W9, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463fa0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2616	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR X23, [X6, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X7]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X7, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR X26, [X11]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X11, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X10]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X10, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UMADDL X8, W22, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
STP X12, X8, [SP, #16]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
STR W1, [SP, #32]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X13, [X29, #1008]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X9, [SP, #24]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
CSEL X8, X8, X9, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.GT 429110 <.omp_outlined.+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CNTD X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
ORR X9, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB X11, X8, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.CC 4290c4 <.omp_outlined.+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X9, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	5-20	1-0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
MADD X12, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
INDEX Z0.D, X13, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD X9, X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR X13, [SP, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z1.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
DUP Z2.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z3.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z4.D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z5.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z7.D, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z16.D, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
DUP Z6.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1
CBZ X11, 429110 <.omp_outlined.+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [SP, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W10, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR W1, [SP, #32]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463114>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2640	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined.#0x428f40–	1.33	0.72
○Loop 156 - revert.cpp:35-38 - exec	1.33	0.72
○Loop 155 - revert.cpp:35-38 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code