OV - exec - Function .omp_outlined.#0x4278d0

	Function: .omp_outlined.#0x4278d0	Module: exec	Source: PdV.cpp:48-63 [...]	Coverage: 4.38%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

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69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp: 48 - 63

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48: #pragma omp parallel for simd collapse(2)

49:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

50:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

51:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel0(i, j) + xvel0(i + 0, j + 1))) * 0.25 * dt * 0.5;

52:         double right_flux =

53:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1))) * 0.25 * dt *

54:             0.5;

55:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel0(i, j) + yvel0(i + 1, j + 0))) * 0.25 * dt * 0.5;

56:         double top_flux = (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1))) *

57:                           0.25 * dt * 0.5;

58:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

59:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

60:         double recip_volume = 1.0 / volume(i, j);

61:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

62:         energy1(i, j) = energy0(i, j) - energy_change;

63:         density1(i, j) = density0(i, j) * volume_change_s;

0x4278d0 SUB	SP, SP, #400

0x4278d4 STP	D15, D14, [SP, #240]

0x4278d8 STP	D13, D12, [SP, #256]

0x4278dc STP	D11, D10, [SP, #272]

0x4278e0 STP	D9, D8, [SP, #288]

0x4278e4 STP	X29, X30, [SP, #304]

0x4278e8 STP	X28, X27, [SP, #320]

0x4278ec STP	X26, X25, [SP, #336]

0x4278f0 STP	X24, X23, [SP, #352]

0x4278f4 STP	X22, X21, [SP, #368]

0x4278f8 STP	X20, X19, [SP, #384]

0x4278fc ADD	X29, SP, #304

0x427900 LDR	W24, [X2]

0x427904 LDR	W8, [X3]

0x427908 ADD	W10, W24, #1

0x42790c ADD	W8, W8, #2

0x427910 SUBS	W8, W8, W10

0x427914 B.LE	427e30

0x427918 LDR	W26, [X4]

0x42791c LDR	W9, [X5]

0x427920 ADD	W1, W26, #1

0x427924 ADD	W9, W9, #2

0x427928 CMP	W9, W1

0x42792c B.LE	427e30

0x427930 LDP	X17, X16, [X29, #112]

0x427934 LDP	X13, X12, [X29, #144]

0x427938 LDP	X15, X14, [X29, #128]

0x42793c SUB	X4, X29, #80

0x427940 SUB	X5, X29, #88

0x427944 STUR	X10, [X29, #384]

0x427948 LDP	X11, X10, [X29, #160]

0x42794c LDR	X18, [X29, #104]

0x427950 LDR	X2, [X6]

0x427954 LDR	X3, [X7]

0x427958 LDR	X23, [X6, #16]

0x42795c SUB	X6, X29, #96

0x427960 LDR	X25, [X7, #16]

0x427964 MOVZ	W7, #1

0x427968 LDR	X28, [X17]

0x42796c LDR	X19, [X17, #16]

0x427970 LDR	X17, [X16]

0x427974 LDR	X20, [X15, #16]

0x427978 LDR	X21, [X14, #16]

0x42797c STP	X17, X2, [X29, #880]

0x427980 LDR	X2, [X18]

0x427984 LDR	X27, [X18, #16]

0x427988 STUR	WZR, [X29, #412]

0x42798c LDR	X17, [X16, #16]

0x427990 LDR	X16, [X15]

0x427994 LDR	X15, [X14]

0x427998 LDR	X14, [X13]

0x42799c LDR	X13, [X13, #16]

0x4279a0 STP	X2, X3, [SP, #8]

0x4279a4 SUB	X3, X29, #100

0x4279a8 MOVZ	W2, #34

0x4279ac STP	X13, X14, [SP, #72]

0x4279b0 LDR	X13, [X12]

0x4279b4 LDR	X12, [X12, #16]

0x4279b8 STP	X16, X17, [SP, #144]

0x4279bc STR	X15, [SP, #136]

0x4279c0 STP	X12, X13, [SP, #56]

0x4279c4 LDR	X12, [X11]

0x4279c8 LDR	X11, [X11, #16]

0x4279cc STP	X11, X12, [SP, #40]

0x4279d0 SUB	W11, W9, W1

0x4279d4 MOVN	X9, #0

0x4279d8 UMADDL	X22, W11, W8, X9

0x4279dc LDR	X9, [X10]

0x4279e0 STP	X11, X1, [X29, #904]

0x4279e4 LDR	W1, [X0]

0x4279e8 MOVZ	W8, #1

0x4279ec ADRP	X0,

0x4279f0 ADD	X0, X0, #2328

0x4279f4 STUR	X8, [X29, #416]

0x4279f8 STP	X22, XZR, [X29, #936]

0x4279fc STR	X9, [SP, #32]

0x427a00 LDR	X9, [X10, #16]

0x427a04 STR	X8, [SP]

0x427a08 STR	W1, [SP, #92]

0x427a0c STR	X9, [SP, #24]

0x427a10 BL	4033a0

0x427a14 LDP	X8, X14, [X29, #936]

0x427a18 CMP	X8, X22

0x427a1c CSEL	X9, X8, X22, #11

0x427a20 CMP	X14, X9

0x427a24 B.GT	427e20

0x427a28 LDR	X3, [X29, #96]

0x427a2c ADD	X0, X9, #1

0x427a30 CNTD	X11, ALL

0x427a34 ORR	X10, XZR, X14

0x427a38 SUB	X12, X0, X14

0x427a3c CMP	X12, X11

0x427a40 B.CC	427c54

0x427a44 UDIV	X10, X12, X11

0x427a48 PTRUE	P0.D, ALL

0x427a4c FMOV	D25, #0.2500000

0x427a50 MADD	X13, X10, X11, XZR

0x427a54 INDEX	Z0.D, X14, #1

0x427a58 ADD	X10, X14, X13

0x427a5c DUP	Z1.D, X11

0x427a60 LDP	X14, X8, [X29, #896]

0x427a64 SUB	X12, X12, X13

0x427a68 DUP	Z16.D, X28

0x427a6c DUP	Z2.D, X8

0x427a70 LDR	X8, [SP, #16]

0x427a74 DUP	Z3.D, X14

0x427a78 LDUR	X14, [X29, #400]

0x427a7c DUP	Z4.D, X14

0x427a80 DUP	Z6.D, X8

0x427a84 LDP	X9, X14, [X29, #880]

0x427a88 LDR	X8, [SP, #8]

0x427a8c DUP	Z7.D, X8

0x427a90 DUP	Z17.D, X9

0x427a94 LDP	X8, X9, [SP, #136]

0x427a98 DUP	Z5.D, X14

0x427a9c ADD	W14, W24, #2

0x427aa0 DUP	Z24.D, X14

0x427aa4 ADD	W14, W26, #2

0x427aa8 DUP	Z26.D, X14

0x427aac DUP	Z19.D, X8

0x427ab0 LDR	X8, [SP, #80]

0x427ab4 DUP	Z18.D, X9

0x427ab8 LDR	X9, [SP, #152]

0x427abc DUP	Z20.D, X8

0x427ac0 LDP	X15, X8, [SP, #40]

0x427ac4 DUP	Z21.D, X8

0x427ac8 LDP	X14, X8, [SP, #56]

0x427acc DUP	Z22.D, X8

0x427ad0 LDP	X16, X8, [SP, #24]

0x427ad4 DUP	Z23.D, X8

0x427ad8 LDR	X8, [SP, #72]

0x427adc HINT	#0

(160) 0x427ae0 MOVPRFX	Z28, Z0

(160) 0x427ae4 SDIV	Z28.D, P0/M, Z28.D, Z2.D

(160) 0x427ae8 ADD	Z27.D, Z3.D, Z28.D

(160) 0x427aec MOVPRFX	Z29, Z0

(160) 0x427af0 MLS	Z29.D, P0/M, Z28.D, Z2.D

(160) 0x427af4 ADD	Z30.D, Z4.D, Z29.D

(160) 0x427af8 MOVPRFX	Z9, Z30

(160) 0x427afc SXTW	Z9.D, P0/M, Z30.D

(160) 0x427b00 SUBS	X13, X13, X11

(160) 0x427b04 ADD	Z28.D, Z24.D, Z28.D

(160) 0x427b08 ADD	Z29.D, Z26.D, Z29.D

(160) 0x427b0c ADD	Z0.D, Z0.D, Z1.D

(160) 0x427b10 SXTW	Z27.D, P0/M, Z27.D

(160) 0x427b14 MOVPRFX	Z31, Z5

(160) 0x427b18 MUL	Z31.D, P0/M, Z31.D, Z27.D

(160) 0x427b1c MOVPRFX	Z10, Z6

(160) 0x427b20 MUL	Z10.D, P0/M, Z10.D, Z27.D

(160) 0x427b24 ADR	Z8.D, [Z31, Z30.D,SXTW]

(160) 0x427b28 LD1D	{Z8.D}, P0/Z, [X23, Z8.D,LSL #3]

(160) 0x427b2c ADR	Z11.D, [Z10, Z30.D,SXTW]

(160) 0x427b30 SXTW	Z28.D, P0/M, Z28.D

(160) 0x427b34 MOVPRFX	Z12, Z6

(160) 0x427b38 MUL	Z12.D, P0/M, Z12.D, Z28.D

(160) 0x427b3c ADR	Z13.D, [Z12, Z30.D,SXTW]

(160) 0x427b40 LD1D	{Z11.D}, P0/Z, [X25, Z11.D,LSL #3]

(160) 0x427b44 LD1D	{Z13.D}, P0/Z, [X25, Z13.D,LSL #3]

(160) 0x427b48 MOVPRFX	Z15, Z9

(160) 0x427b4c MLA	Z15.D, P0/M, Z7.D, Z28.D

(160) 0x427b50 ADR	Z31.D, [Z31, Z29.D,SXTW]

(160) 0x427b54 ADR	Z10.D, [Z10, Z29.D,SXTW]

(160) 0x427b58 ADR	Z12.D, [Z12, Z29.D,SXTW]

(160) 0x427b5c FADD	Z11.D, Z13.D, Z11.D

(160) 0x427b60 MUL	Z28.D, P0/M, Z28.D, Z16.D

(160) 0x427b64 LDR	D13, [X3]

(160) 0x427b68 LD1D	{Z31.D}, P0/Z, [X23, Z31.D,LSL #3]

(160) 0x427b6c LD1D	{Z10.D}, P0/Z, [X25, Z10.D,LSL #3]

(160) 0x427b70 LD1D	{Z12.D}, P0/Z, [X25, Z12.D,LSL #3]

(160) 0x427b74 FADD	Z10.D, Z12.D, Z10.D

(160) 0x427b78 MOVPRFX	Z12, Z16

(160) 0x427b7c MUL	Z12.D, P0/M, Z12.D, Z27.D

(160) 0x427b80 ADR	Z14.D, [Z12, Z30.D,SXTW]

(160) 0x427b84 ADR	Z12.D, [Z12, Z29.D,SXTW]

(160) 0x427b88 ADR	Z30.D, [Z28, Z30.D,SXTW]

(160) 0x427b8c ADR	Z28.D, [Z28, Z29.D,SXTW]

(160) 0x427b90 FMUL	Z29.D, Z11.D, Z8.D

(160) 0x427b94 MOVPRFX	Z8, Z9

(160) 0x427b98 MLA	Z8.D, P0/M, Z19.D, Z27.D

(160) 0x427b9c MOVPRFX	Z11, Z9

(160) 0x427ba0 MLA	Z11.D, P0/M, Z20.D, Z27.D

(160) 0x427ba4 FMUL	Z31.D, Z10.D, Z31.D

(160) 0x427ba8 MOVPRFX	Z10, Z9

(160) 0x427bac MLA	Z10.D, P0/M, Z7.D, Z27.D

(160) 0x427bb0 LD1D	{Z10.D}, P0/Z, [X27, Z10.D,LSL #3]

(160) 0x427bb4 LD1D	{Z14.D}, P0/Z, [X19, Z14.D,LSL #3]

(160) 0x427bb8 LD1D	{Z12.D}, P0/Z, [X19, Z12.D,LSL #3]

(160) 0x427bbc LD1D	{Z15.D}, P0/Z, [X27, Z15.D,LSL #3]

(160) 0x427bc0 LD1D	{Z30.D}, P0/Z, [X19, Z30.D,LSL #3]

(160) 0x427bc4 LD1D	{Z28.D}, P0/Z, [X19, Z28.D,LSL #3]

(160) 0x427bc8 FADD	Z12.D, Z12.D, Z14.D

(160) 0x427bcc FADD	Z28.D, Z28.D, Z30.D

(160) 0x427bd0 MOVPRFX	Z30, Z9

(160) 0x427bd4 MLA	Z30.D, P0/M, Z17.D, Z27.D

(160) 0x427bd8 LD1D	{Z30.D}, P0/Z, [X9, Z30.D,LSL #3]

(160) 0x427bdc FMLA	Z29.D, P0/M, Z12.D, Z10.D

(160) 0x427be0 FMAD	Z28.D, P0/M, Z15.D, Z31.D

(160) 0x427be4 MOVPRFX	Z31, Z9

(160) 0x427be8 MLA	Z31.D, P0/M, Z18.D, Z27.D

(160) 0x427bec LD1D	{Z31.D}, P0/Z, [X20, Z31.D,LSL #3]

(160) 0x427bf0 LD1D	{Z10.D}, P0/Z, [X21, Z8.D,LSL #3]

(160) 0x427bf4 FSUB	Z28.D, Z28.D, Z29.D

(160) 0x427bf8 FMUL	D29, D13, D25

(160) 0x427bfc DUP	Z29.D, Z29.D[0]

(160) 0x427c00 FMUL	Z28.D, Z29.D, Z28.D

(160) 0x427c04 LD1D	{Z29.D}, P0/Z, [X8, Z11.D,LSL #3]

(160) 0x427c08 FADD	Z29.D, Z29.D, Z31.D

(160) 0x427c0c FMUL	Z31.D, Z10.D, Z30.D

(160) 0x427c10 FMUL	Z29.D, Z29.D, Z28.D

(160) 0x427c14 FADD	Z28.D, Z28.D, Z30.D

(160) 0x427c18 FDIV	Z29.D, P0/M, Z29.D, Z31.D

(160) 0x427c1c MOVPRFX	Z31, Z9

(160) 0x427c20 MLA	Z31.D, P0/M, Z21.D, Z27.D

(160) 0x427c24 LD1D	{Z31.D}, P0/Z, [X15, Z31.D,LSL #3]

(160) 0x427c28 FSUB	Z29.D, Z31.D, Z29.D

(160) 0x427c2c MOVPRFX	Z31, Z9

(160) 0x427c30 MLA	Z31.D, P0/M, Z22.D, Z27.D

(160) 0x427c34 MAD	Z27.D, P0/M, Z23.D, Z9.D

(160) 0x427c38 ST1D	{Z29.D}, P0, [X14, Z31.D,LSL #3]

(160) 0x427c3c LD1D	{Z29.D}, P0/Z, [X21, Z8.D,LSL #3]

(160) 0x427c40 FMUL	Z29.D, Z29.D, Z30.D

(160) 0x427c44 FDIVR	Z28.D, P0/M, Z28.D, Z29.D

(160) 0x427c48 ST1D	{Z28.D}, P0, [X16, Z27.D,LSL #3]

(160) 0x427c4c B.NE	427ae0

0x427c50 CBZ	X12, 427e20

0x427c54 LDP	X18, X8, [X29, #904]

0x427c58 STP	X23, X20, [SP, #96]

0x427c5c FMOV	D0, #0.2500000

0x427c60 UBFM	X15, X10, #32, #31

0x427c64 SBFM	X13, X8, #61, #31

0x427c68 LDP	X26, X24, [SP, #8]

0x427c6c ADD	X11, X23, X13

0x427c70 LDP	X14, X23, [SP, #72]

0x427c74 LDP	X7, X16, [SP, #56]

0x427c78 LDP	X9, X30, [SP, #40]

0x427c7c ADD	X12, X25, X13

0x427c80 ADD	X13, X19, X13

0x427c84 ADD	X8, X11, #8

0x427c88 ADD	X12, X12, #8

0x427c8c ADD	X13, X13, #8

0x427c90 STR	X8, [SP, #128]

0x427c94 SUB	X8, XZR, X18,LSL #32

0x427c98 STR	X8, [SP, #120]

0x427c9c SUB	W8, WZR, W18

0x427ca0 STR	W8, [SP, #116]

0x427ca4 LDP	X8, X17, [SP, #24]

(159) 0x427ca8 SDIV	X1, X10, X18

(159) 0x427cac LDP	X4, X11, [X29, #888]

(159) 0x427cb0 ORR	X20, XZR, X3

(159) 0x427cb4 LDR	X22, [SP, #120]

(159) 0x427cb8 ADD	W2, W11, W1

(159) 0x427cbc LDUR	X11, [X29, #400]

(159) 0x427cc0 ADD	W18, W11, W10

(159) 0x427cc4 LDR	W11, [SP, #116]

(159) 0x427cc8 ADD	X10, X10, #1

(159) 0x427ccc MADD	W18, W11, W1, W18

(159) 0x427cd0 ORR	X11, XZR, X0

(159) 0x427cd4 SBFM	X0, X2, #0, #31

(159) 0x427cd8 ADD	W2, W2, #1

(159) 0x427cdc MADD	X1, X22, X1, X15

(159) 0x427ce0 LDR	X22, [SP, #96]

(159) 0x427ce4 MADD	X3, X24, X0, XZR

(159) 0x427ce8 SBFM	X2, X2, #0, #31

(159) 0x427cec MADD	X4, X4, X0, XZR

(159) 0x427cf0 SBFM	X18, X18, #0, #31

(159) 0x427cf4 ADD	X5, X3, X18

(159) 0x427cf8 ADD	X3, X3, X1,ASR #32

(159) 0x427cfc LDR	D1, [X25, X5,LSL #3]

(159) 0x427d00 MADD	X5, X24, X2, XZR

(159) 0x427d04 LDR	D5, [X12, X3,LSL #3]

(159) 0x427d08 ADD	X6, X5, X18

(159) 0x427d0c ADD	X3, X5, X1,ASR #32

(159) 0x427d10 LDR	D2, [X25, X6,LSL #3]

(159) 0x427d14 ADD	X6, X4, X18

(159) 0x427d18 ADD	X4, X4, X1,ASR #32

(159) 0x427d1c LDR	D6, [X12, X3,LSL #3]

(159) 0x427d20 MADD	X3, X26, X0, X18

(159) 0x427d24 LDR	D3, [X22, X6,LSL #3]

(159) 0x427d28 LDR	X6, [SP, #128]

(159) 0x427d2c LDR	D7, [X27, X3,LSL #3]

(159) 0x427d30 LDR	D4, [X6, X4,LSL #3]

(159) 0x427d34 MADD	X4, X28, X0, XZR

(159) 0x427d38 FADD	D1, D2, D1

(159) 0x427d3c FADD	D2, D6, D5

(159) 0x427d40 ADD	X3, X4, X1,ASR #32

(159) 0x427d44 ADD	X5, X4, X18

(159) 0x427d48 FMUL	D1, D1, D3

(159) 0x427d4c LDR	D17, [X13, X3,LSL #3]

(159) 0x427d50 MADD	X3, X26, X2, X18

(159) 0x427d54 MADD	X2, X28, X2, XZR

(159) 0x427d58 LDR	D16, [X19, X5,LSL #3]

(159) 0x427d5c LDR	D18, [X27, X3,LSL #3]

(159) 0x427d60 ADD	X3, X2, X18

(159) 0x427d64 ADD	X1, X2, X1,ASR #32

(159) 0x427d68 LDR	X2, [SP, #152]

(159) 0x427d6c FMUL	D2, D2, D4

(159) 0x427d70 LDR	D4, [X20]

(159) 0x427d74 LDR	D19, [X19, X3,LSL #3]

(159) 0x427d78 LDR	D6, [X13, X1,LSL #3]

(159) 0x427d7c LDUR	X1, [X29, #368]

(159) 0x427d80 ORR	X3, XZR, X20

(159) 0x427d84 FADD	D5, D17, D16

(159) 0x427d88 MADD	X1, X1, X0, X18

(159) 0x427d8c FMADD	D1, D5, D7, D1

(159) 0x427d90 FADD	D6, D6, D19

(159) 0x427d94 LDR	D3, [X2, X1,LSL #3]

(159) 0x427d98 LDR	X1, [SP, #144]

(159) 0x427d9c LDR	X2, [SP, #104]

(159) 0x427da0 FMADD	D2, D6, D18, D2

(159) 0x427da4 MADD	X1, X1, X0, X18

(159) 0x427da8 FSUB	D1, D2, S1

(159) 0x427dac FMUL	D2, D4, D0

(159) 0x427db0 LDR	D4, [X2, X1,LSL #3]

(159) 0x427db4 LDR	X1, [SP, #136]

(159) 0x427db8 MADD	X2, X23, X0, X18

(159) 0x427dbc LDR	D6, [X14, X2,LSL #3]

(159) 0x427dc0 MADD	X2, X30, X0, X18

(159) 0x427dc4 FMUL	D1, D2, D1

(159) 0x427dc8 MADD	X1, X1, X0, X18

(159) 0x427dcc LDR	D5, [X21, X1,LSL #3]

(159) 0x427dd0 FADD	D2, D6, D4

(159) 0x427dd4 FMUL	D2, D2, D1

(159) 0x427dd8 FADD	D1, D1, D3

(159) 0x427ddc FMUL	D4, D5, D3

(159) 0x427de0 FDIV	D2, D2, D4

(159) 0x427de4 LDR	D4, [X9, X2,LSL #3]

(159) 0x427de8 MADD	X2, X16, X0, X18

(159) 0x427dec MADD	X18, X17, X0, X18

(159) 0x427df0 ORR	X0, XZR, X11

(159) 0x427df4 MOVZ	X11, #1

(159) 0x427df8 ADD	X15, X15, X11

(159) 0x427dfc CMP	X0, X10

(159) 0x427e00 FSUB	D2, D4, S2

(159) 0x427e04 STR	D2, [X7, X2,LSL #3]

(159) 0x427e08 LDR	D2, [X21, X1,LSL #3]

(159) 0x427e0c FMUL	D2, D2, D3

(159) 0x427e10 FDIV	D1, D2, D1

(159) 0x427e14 STR	D1, [X8, X18,LSL #3]

(159) 0x427e18 LDUR	X18, [X29, #392]

(159) 0x427e1c B.NE	427ca8

0x427e20 LDR	W1, [SP, #92]

0x427e24 ADRP	X0,

0x427e28 ADD	X0, X0, #2352

0x427e2c BL	403260

0x427e30 LDP	D9, D8, [SP, #288]

0x427e34 LDP	D11, D10, [SP, #272]

0x427e38 LDP	D13, D12, [SP, #256]

0x427e3c LDP	D15, D14, [SP, #240]

0x427e40 LDP	X20, X19, [SP, #384]

0x427e44 LDP	X22, X21, [SP, #368]

0x427e48 LDP	X24, X23, [SP, #352]

0x427e4c LDP	X26, X25, [SP, #336]

0x427e50 LDP	X28, X27, [SP, #320]

0x427e54 LDP	X29, X30, [SP, #304]

0x427e58 ADD	SP, SP, #400

0x427e5c RET

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	PdV.cpp:48-63
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:48-63

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 31.00 to 18.00 cycles (1.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 29% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 31.00 to 29.67 cycles (1.04x speedup).

Details

20% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 31.00 to 1.00 cycles (31.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 696 bytes. The binary function is storing 380 bytes.

General properties

nb instructions	170
loop length	680
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	15.00	15.00	22.00	15.00	2.50	2.50	1.00	1.00	31.00	31.00	31.00	13.00	13.00
cycles	4.00	4.00	15.00	15.00	22.00	15.00	2.50	2.50	1.00	1.00	31.00	31.00	31.00	13.00	13.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	21.13
Overall L1	31.00

Vectorization ratios

all	20%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 31.00 cycles. At this rate:

23% of peak load performance is reached (22.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (12.26 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4278d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP D15, D14, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D13, D12, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D11, D10, [SP, #272]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D9, D8, [SP, #288]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W10, W24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 427e30 <.omp_outlined.+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W26, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W1, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 427e30 <.omp_outlined.+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X17, X16, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X13, X12, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X15, X14, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X4, X29, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X10, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X11, X10, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X18, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X6, X29, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X25, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X17, X2, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR WZR, [X29, #412]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X2, X3, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X3, X29, #100	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X13, X14, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X16, X17, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X12, X13, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X11, X12, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W11, W9, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UMADDL X22, W11, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X11, X1, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4639ec>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2328	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, XZR, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W1, [SP, #92]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X14, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X9, X8, X22, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X14, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 427e20 <.omp_outlined.+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X10, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 427c54 <.omp_outlined.+0x384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X10, X12, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FMOV D25, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MADD X13, X10, X11, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
INDEX Z0.D, X14, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
ADD X10, X14, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X14, X8, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X12, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z16.D, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z2.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z3.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDUR X14, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z4.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z6.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X9, X14, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z7.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z17.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X8, X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z5.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD W14, W24, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z24.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD W14, W26, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z26.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z19.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z18.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X9, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z20.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X15, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z21.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X14, X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z22.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X16, X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z23.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
CBZ X12, 427e20 <.omp_outlined.+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X18, X8, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X23, X20, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
UBFM X15, X10, #32, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X13, X8, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X26, X24, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X11, X23, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X14, X23, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X7, X16, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X30, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X12, X25, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X19, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X8, XZR, X18,LSL #32	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, WZR, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X17, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W1, [SP, #92]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463e24>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP D9, D8, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D11, D10, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D13, D12, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D15, D14, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	PdV.cpp:48-63
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:48-63

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

20% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 31.00 to 1.00 cycles (31.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 696 bytes. The binary function is storing 380 bytes.

General properties

nb instructions	170
loop length	680
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	15.00	15.00	22.00	15.00	2.50	2.50	1.00	1.00	31.00	31.00	31.00	13.00	13.00
cycles	4.00	4.00	15.00	15.00	22.00	15.00	2.50	2.50	1.00	1.00	31.00	31.00	31.00	13.00	13.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	21.13
Overall L1	31.00

Vectorization ratios

all	20%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 31.00 cycles. At this rate:

23% of peak load performance is reached (22.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (12.26 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4278d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP D15, D14, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D13, D12, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D11, D10, [SP, #272]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D9, D8, [SP, #288]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W10, W24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 427e30 <.omp_outlined.+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W26, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W1, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 427e30 <.omp_outlined.+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X17, X16, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X13, X12, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X15, X14, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X4, X29, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X10, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X11, X10, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X18, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X6, X29, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X25, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X17, X2, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR WZR, [X29, #412]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X2, X3, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X3, X29, #100	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X13, X14, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X16, X17, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X12, X13, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X11, X12, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W11, W9, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UMADDL X22, W11, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X11, X1, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4639ec>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2328	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, XZR, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W1, [SP, #92]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X14, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X9, X8, X22, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X14, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 427e20 <.omp_outlined.+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X10, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 427c54 <.omp_outlined.+0x384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X10, X12, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FMOV D25, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MADD X13, X10, X11, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
INDEX Z0.D, X14, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
ADD X10, X14, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X14, X8, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X12, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z16.D, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z2.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z3.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDUR X14, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z4.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z6.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X9, X14, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z7.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z17.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X8, X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z5.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD W14, W24, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z24.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD W14, W26, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z26.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z19.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z18.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X9, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z20.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X15, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z21.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X14, X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z22.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X16, X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z23.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
CBZ X12, 427e20 <.omp_outlined.+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X18, X8, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X23, X20, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
UBFM X15, X10, #32, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X13, X8, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X26, X24, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X11, X23, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X14, X23, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X7, X16, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X30, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X12, X25, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X19, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X8, XZR, X18,LSL #32	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, WZR, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X17, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W1, [SP, #92]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463e24>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP D9, D8, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D11, D10, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D13, D12, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D15, D14, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined.#0x4278d0–	4.38	2.36
○Loop 160 - PdV.cpp:48-63 - exec	4.38	2.36
○Loop 159 - PdV.cpp:49-63 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code