OV - exec - Function .omp_outlined.#0x4228a0

	Function: .omp_outlined.#0x4228a0	Module: exec	Source: generate_chunk.cpp:74-80 [...]	Coverage: 0.01%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

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69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp: 74 - 80

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74: #pragma omp parallel for simd collapse(2)

75:   for (int j = (0); j < (yrange); j++) {

76:     for (int i = (0); i < (xrange); i++) {

77:       field.energy0(i, j) = state_energy[0];

78:       field.density0(i, j) = state_density[0];

79:       field.xvel0(i, j) = state_xvel[0];

80:       field.yvel0(i, j) = state_yvel[0];

0x4228a0 SUB	SP, SP, #128

0x4228a4 STP	X29, X30, [SP, #48]

0x4228a8 STP	X26, X25, [SP, #64]

0x4228ac STP	X24, X23, [SP, #80]

0x4228b0 STP	X22, X21, [SP, #96]

0x4228b4 STP	X20, X19, [SP, #112]

0x4228b8 ADD	X29, SP, #48

0x4228bc LDR	W8, [X2]

0x4228c0 LDR	W9, [X3]

0x4228c4 CMP	W8, #1

0x4228c8 CCMP	W9, #1, #8, #10

0x4228cc B.LT	422aa0

0x4228d0 LDR	X10, [X29, #80]

0x4228d4 LDR	W19, [X0]

0x4228d8 LDR	X21, [X5, #8]

0x4228dc SBFM	X25, X9, #0, #31

0x4228e0 MOVN	X9, #0

0x4228e4 ORR	X20, XZR, X4

0x4228e8 ADRP	X0,

0x4228ec ADD	X0, X0, #1160

0x4228f0 LDR	X22, [X6, #8]

0x4228f4 ADD	X3, SP, #20

0x4228f8 LDR	X23, [X7, #8]

0x4228fc MADD	X26, X25, X8, X9

0x422900 MOVZ	W8, #1

0x422904 STR	WZR, [SP, #20]

0x422908 STR	X8, [SP, #24]

0x42290c SUB	X4, X29, #8

0x422910 SUB	X5, X29, #16

0x422914 ADD	X6, SP, #24

0x422918 MOVZ	W2, #34

0x42291c STP	X26, XZR, [X29, #1008]

0x422920 MOVZ	W7, #1

0x422924 LDR	X24, [X10, #8]

0x422928 ORR	W1, WZR, W19

0x42292c STR	X8, [SP]

0x422930 BL	4033a0

0x422934 LDP	X8, X0, [X29, #1008]

0x422938 CMP	X8, X26

0x42293c CSEL	X16, X8, X26, #11

0x422940 CMP	X0, X16

0x422944 B.GT	422a90

0x422948 LDR	X8, [X20, #64]

0x42294c LDR	X9, [X20, #48]

0x422950 LDR	X10, [X20, #16]

0x422954 ADD	X16, X16, #1

0x422958 CNTD	X18, ALL

0x42295c ORR	X17, XZR, X0

0x422960 SUB	X1, X16, X0

0x422964 LDR	X11, [X20]

0x422968 LDR	X12, [X20, #184]

0x42296c LDR	X13, [X20, #168]

0x422970 CMP	X1, X18

0x422974 LDR	X14, [X20, #232]

0x422978 LDR	X15, [X20, #216]

0x42297c B.CC	422a24

0x422980 UDIV	X17, X1, X18

0x422984 PTRUE	P0.D, ALL

0x422988 MADD	X2, X17, X18, XZR

0x42298c INDEX	Z0.D, X0, #1

0x422990 SUB	X1, X1, X2

0x422994 DUP	Z1.D, X18

0x422998 ADD	X17, X0, X2

0x42299c DUP	Z2.D, X25

0x4229a0 DUP	Z3.D, X9

0x4229a4 DUP	Z4.D, X11

0x4229a8 DUP	Z5.D, X13

0x4229ac DUP	Z6.D, X15

0x4229b0 HINT	#0

0x4229b4 HINT	#0

0x4229b8 HINT	#0

0x4229bc HINT	#0

(170) 0x4229c0 LD1RD	{Z17.D}, P0/Z, [X21]

(170) 0x4229c4 MOVPRFX	Z7, Z0

(170) 0x4229c8 SDIV	Z7.D, P0/M, Z7.D, Z2.D

(170) 0x4229cc MOVPRFX	Z16, Z0

(170) 0x4229d0 MLS	Z16.D, P0/M, Z7.D, Z2.D

(170) 0x4229d4 SXTW	Z16.D, P0/M, Z16.D

(170) 0x4229d8 ADD	Z0.D, Z0.D, Z1.D

(170) 0x4229dc SUBS	X2, X2, X18

(170) 0x4229e0 SXTW	Z7.D, P0/M, Z7.D

(170) 0x4229e4 MOVPRFX	Z18, Z16

(170) 0x4229e8 MLA	Z18.D, P0/M, Z7.D, Z3.D

(170) 0x4229ec ST1D	{Z17.D}, P0, [X8, Z18.D,LSL #3]

(170) 0x4229f0 MOVPRFX	Z18, Z16

(170) 0x4229f4 MLA	Z18.D, P0/M, Z7.D, Z4.D

(170) 0x4229f8 LD1RD	{Z17.D}, P0/Z, [X22]

(170) 0x4229fc ST1D	{Z17.D}, P0, [X10, Z18.D,LSL #3]

(170) 0x422a00 MOVPRFX	Z18, Z16

(170) 0x422a04 MLA	Z18.D, P0/M, Z7.D, Z5.D

(170) 0x422a08 MAD	Z7.D, P0/M, Z6.D, Z16.D

(170) 0x422a0c LD1RD	{Z17.D}, P0/Z, [X23]

(170) 0x422a10 ST1D	{Z17.D}, P0, [X12, Z18.D,LSL #3]

(170) 0x422a14 LD1RD	{Z17.D}, P0/Z, [X24]

(170) 0x422a18 ST1D	{Z17.D}, P0, [X14, Z7.D,LSL #3]

(170) 0x422a1c B.NE	4229c0

0x422a20 CBZ	X1, 422a90

0x422a24 SUB	X18, XZR, X25,LSL #32

0x422a28 UBFM	X0, X17, #32, #31

0x422a2c MOVZ	X1, #1

0x422a30 HINT	#0

0x422a34 HINT	#0

0x422a38 HINT	#0

0x422a3c HINT	#0

(169) 0x422a40 SDIV	X2, X17, X25

(169) 0x422a44 LDR	D0, [X21]

(169) 0x422a48 ADD	X17, X17, #1

(169) 0x422a4c CMP	X16, X17

(169) 0x422a50 MADD	X3, X18, X2, X0

(169) 0x422a54 SBFM	X2, X2, #0, #31

(169) 0x422a58 ADD	X0, X0, X1

(169) 0x422a5c SBFM	X3, X3, #32, #63

(169) 0x422a60 MADD	X4, X2, X9, X3

(169) 0x422a64 STR	D0, [X8, X4,LSL #3]

(169) 0x422a68 MADD	X4, X2, X11, X3

(169) 0x422a6c LDR	D0, [X22]

(169) 0x422a70 STR	D0, [X10, X4,LSL #3]

(169) 0x422a74 MADD	X4, X2, X13, X3

(169) 0x422a78 MADD	X2, X2, X15, X3

(169) 0x422a7c LDR	D0, [X23]

(169) 0x422a80 STR	D0, [X12, X4,LSL #3]

(169) 0x422a84 LDR	D0, [X24]

(169) 0x422a88 STR	D0, [X14, X2,LSL #3]

(169) 0x422a8c B.NE	422a40

0x422a90 ORR	W1, WZR, W19

0x422a94 ADRP	X0,

0x422a98 ADD	X0, X0, #1184

0x422a9c BL	403260

0x422aa0 LDP	X20, X19, [SP, #112]

0x422aa4 LDP	X22, X21, [SP, #96]

0x422aa8 LDP	X24, X23, [SP, #80]

0x422aac LDP	X26, X25, [SP, #64]

0x422ab0 LDP	X29, X30, [SP, #48]

0x422ab4 ADD	SP, SP, #128

0x422ab8 RET

0x422abc HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	generate_chunk.cpp:74-80
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp:74-80

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.50 to 7.00 cycles (1.64x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 11.50 to 10.50 cycles (1.10x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 11.50 to 1.00 cycles (11.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 212 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	92
loop length	368
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	11.50	11.50	11.50	11.50	1.00	0.00	0.00	0.00	10.50	10.17	10.33	4.50	4.50
cycles	3.50	3.50	11.50	11.50	11.50	11.50	1.00	0.00	0.00	0.00	10.50	10.17	10.33	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	10.38
Overall L1	11.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.50 cycles. At this rate:

19% of peak load performance is reached (18.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.09 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4228a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W9, #1, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LT 422aa0 <.omp_outlined.+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X29, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X25, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4638e8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X22, [X6, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X23, [X7, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X26, X25, X8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X26, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X24, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X0, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X16, X8, X26, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X0, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 422a90 <.omp_outlined.+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X18, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X17, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X1, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X20, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X20, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X14, [X20, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X20, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 422a24 <.omp_outlined.+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X17, X1, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X2, X17, X18, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
INDEX Z0.D, X0, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
SUB X1, X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD X17, X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z2.D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z3.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z4.D, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z5.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z6.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
HINT #0
HINT #0
HINT #0
HINT #0
CBZ X1, 422a90 <.omp_outlined.+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X18, XZR, X25,LSL #32	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
UBFM X0, X17, #32, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <463a94>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	generate_chunk.cpp:74-80
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp:74-80

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.50 to 7.00 cycles (1.64x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 11.50 to 1.00 cycles (11.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 212 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	92
loop length	368
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	11.50	11.50	11.50	11.50	1.00	0.00	0.00	0.00	10.50	10.17	10.33	4.50	4.50
cycles	3.50	3.50	11.50	11.50	11.50	11.50	1.00	0.00	0.00	0.00	10.50	10.17	10.33	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	10.38
Overall L1	11.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.50 cycles. At this rate:

19% of peak load performance is reached (18.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.09 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4228a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W9, #1, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LT 422aa0 <.omp_outlined.+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X29, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X25, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4638e8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X22, [X6, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X23, [X7, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X26, X25, X8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X26, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X24, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X0, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X16, X8, X26, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X0, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 422a90 <.omp_outlined.+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X18, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X17, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X1, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X20, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X20, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X14, [X20, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X20, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 422a24 <.omp_outlined.+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X17, X1, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X2, X17, X18, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
INDEX Z0.D, X0, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
SUB X1, X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD X17, X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z2.D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z3.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z4.D, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z5.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z6.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
HINT #0
HINT #0
HINT #0
HINT #0
CBZ X1, 422a90 <.omp_outlined.+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X18, XZR, X25,LSL #32	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
UBFM X0, X17, #32, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <463a94>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined.#0x4228a0–	0.01	0
○Loop 170 - generate_chunk.cpp:75-77 - exec	0.01	0
○Loop 169 - generate_chunk.cpp:75-80 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code