OV - exec - Function .omp_outlined.#0x422010

	Function: .omp_outlined.#0x422010	Module: exec	Source: flux_calc.cpp:36-40 [...]	Coverage: 2.91%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/flux_calc.cpp: 36 - 40

--------------------------------------------------------------------------------

36: #pragma omp parallel for simd collapse(2)

37:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

39:       vol_flux_x(i, j) = 0.25 * dt * xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1));

40:       vol_flux_y(i, j) = 0.25 * dt * yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0));

0x422010 SUB	SP, SP, #256

0x422014 STP	X29, X30, [SP, #160]

0x422018 STP	X28, X27, [SP, #176]

0x42201c STP	X26, X25, [SP, #192]

0x422020 STP	X24, X23, [SP, #208]

0x422024 STP	X22, X21, [SP, #224]

0x422028 STP	X20, X19, [SP, #240]

0x42202c ADD	X29, SP, #160

0x422030 LDR	W27, [X2]

0x422034 LDR	W8, [X3]

0x422038 ADD	W10, W27, #1

0x42203c ADD	W8, W8, #3

0x422040 SUBS	W8, W8, W10

0x422044 B.LE	422430

0x422048 LDR	W20, [X4]

0x42204c LDR	W9, [X5]

0x422050 ADD	W17, W20, #1

0x422054 ADD	W9, W9, #3

0x422058 CMP	W9, W17

0x42205c B.LE	422430

0x422060 LDR	X18, [X6]

0x422064 LDR	X16, [X29, #96]

0x422068 STUR	X10, [X29, #448]

0x42206c ORR	X19, XZR, X7

0x422070 SUB	X3, X29, #28

0x422074 SUB	X4, X29, #8

0x422078 SUB	X5, X29, #16

0x42207c MOVZ	W2, #34

0x422080 LDR	W1, [X0]

0x422084 LDP	X11, X10, [X29, #136]

0x422088 LDP	X13, X12, [X29, #120]

0x42208c ADRP	X0,

0x422090 ADD	X0, X0, #1088

0x422094 MOVZ	W7, #1

0x422098 LDP	X15, X14, [X29, #104]

0x42209c LDR	X28, [X15, #16]

0x4220a0 STR	X18, [SP, #80]

0x4220a4 LDR	X18, [X6, #16]

0x4220a8 LDR	X23, [X14, #16]

0x4220ac LDR	X25, [X13, #16]

0x4220b0 LDR	X21, [X12, #16]

0x4220b4 LDR	X22, [X11, #16]

0x4220b8 LDR	X24, [X10, #16]

0x4220bc SUB	X6, X29, #24

0x4220c0 STUR	X17, [X29, #440]

0x4220c4 STUR	WZR, [X29, #484]

0x4220c8 STUR	W1, [X29, #460]

0x4220cc STR	X18, [SP, #72]

0x4220d0 LDR	X18, [X16]

0x4220d4 LDR	X16, [X16, #16]

0x4220d8 STR	X16, [SP, #8]

0x4220dc LDR	X16, [X15]

0x4220e0 LDR	X15, [X14]

0x4220e4 LDR	X14, [X13]

0x4220e8 LDR	X13, [X12]

0x4220ec LDR	X12, [X11]

0x4220f0 SUB	W11, W9, W17

0x4220f4 MOVN	X9, #0

0x4220f8 UMADDL	X26, W11, W8, X9

0x4220fc LDR	X9, [X10]

0x422100 MOVZ	W8, #1

0x422104 STUR	X11, [X29, #472]

0x422108 STUR	X8, [X29, #488]

0x42210c STR	X8, [SP]

0x422110 STP	X15, X16, [SP, #16]

0x422114 STP	X14, X18, [SP, #56]

0x422118 STP	X12, X13, [SP, #40]

0x42211c STP	X26, XZR, [X29, #1008]

0x422120 STR	X9, [SP, #32]

0x422124 BL	4033a0

0x422128 LDP	X8, X13, [X29, #1008]

0x42212c CMP	X8, X26

0x422130 CSEL	X8, X8, X26, #11

0x422134 CMP	X13, X8

0x422138 B.GT	422420

0x42213c ADD	X26, X8, #1

0x422140 CNTD	X10, ALL

0x422144 ORR	X9, XZR, X13

0x422148 SUB	X11, X26, X13

0x42214c CMP	X11, X10

0x422150 B.CC	4222e8

0x422154 UDIV	X9, X11, X10

0x422158 LDUR	X8, [X29, #472]

0x42215c PTRUE	P0.D, ALL

0x422160 FMOV	D22, #0.2500000

0x422164 MADD	X12, X9, X10, XZR

0x422168 INDEX	Z0.D, X13, #1

0x42216c ADD	X9, X13, X12

0x422170 LDUR	X13, [X29, #448]

0x422174 DUP	Z2.D, X8

0x422178 LDR	X8, [SP, #24]

0x42217c SUB	X11, X11, X12

0x422180 DUP	Z6.D, X8

0x422184 LDR	X8, [SP, #16]

0x422188 DUP	Z7.D, X8

0x42218c DUP	Z1.D, X10

0x422190 DUP	Z3.D, X13

0x422194 LDUR	X13, [X29, #440]

0x422198 DUP	Z4.D, X13

0x42219c LDR	X13, [SP, #64]

0x4221a0 DUP	Z5.D, X13

0x4221a4 LDR	X13, [SP, #80]

0x4221a8 DUP	Z16.D, X13

0x4221ac LDP	X8, X13, [SP, #40]

0x4221b0 DUP	Z17.D, X13

0x4221b4 LDR	X13, [SP, #56]

0x4221b8 DUP	Z18.D, X8

0x4221bc LDR	X8, [SP, #32]

0x4221c0 DUP	Z20.D, X13

0x4221c4 ADD	W13, W27, #2

0x4221c8 DUP	Z19.D, X8

0x4221cc LDR	X8, [SP, #8]

0x4221d0 DUP	Z21.D, X13

0x4221d4 ADD	W13, W20, #2

0x4221d8 DUP	Z23.D, X13

0x4221dc LDR	X13, [SP, #72]

(172) 0x4221e0 LDR	D28, [X19]

(172) 0x4221e4 MOVPRFX	Z24, Z0

(172) 0x4221e8 SDIV	Z24.D, P0/M, Z24.D, Z2.D

(172) 0x4221ec ADD	Z25.D, Z3.D, Z24.D

(172) 0x4221f0 MOVPRFX	Z26, Z0

(172) 0x4221f4 MLS	Z26.D, P0/M, Z24.D, Z2.D

(172) 0x4221f8 ADD	Z27.D, Z4.D, Z26.D

(172) 0x4221fc MOVPRFX	Z29, Z27

(172) 0x422200 SXTW	Z29.D, P0/M, Z27.D

(172) 0x422204 SUBS	X12, X12, X10

(172) 0x422208 ADD	Z24.D, Z21.D, Z24.D

(172) 0x42220c ADD	Z26.D, Z23.D, Z26.D

(172) 0x422210 ADD	Z0.D, Z0.D, Z1.D

(172) 0x422214 SXTW	Z25.D, P0/M, Z25.D

(172) 0x422218 MOVPRFX	Z30, Z29

(172) 0x42221c MLA	Z30.D, P0/M, Z5.D, Z25.D

(172) 0x422220 LD1D	{Z30.D}, P0/Z, [X8, Z30.D,LSL #3]

(172) 0x422224 MOVPRFX	Z31, Z29

(172) 0x422228 MLA	Z31.D, P0/M, Z6.D, Z25.D

(172) 0x42222c LD1D	{Z31.D}, P0/Z, [X28, Z31.D,LSL #3]

(172) 0x422230 SXTW	Z24.D, P0/M, Z24.D

(172) 0x422234 FMUL	D28, D28, D22

(172) 0x422238 DUP	Z28.D, Z28.D[0]

(172) 0x42223c FMUL	Z28.D, Z28.D, Z30.D

(172) 0x422240 MOVPRFX	Z30, Z29

(172) 0x422244 MLA	Z30.D, P0/M, Z6.D, Z24.D

(172) 0x422248 MAD	Z24.D, P0/M, Z7.D, Z29.D

(172) 0x42224c LD1D	{Z30.D}, P0/Z, [X28, Z30.D,LSL #3]

(172) 0x422250 FADD	Z30.D, Z30.D, Z31.D

(172) 0x422254 MOVPRFX	Z31, Z29

(172) 0x422258 MLA	Z31.D, P0/M, Z7.D, Z25.D

(172) 0x42225c LD1D	{Z31.D}, P0/Z, [X23, Z31.D,LSL #3]

(172) 0x422260 LD1D	{Z24.D}, P0/Z, [X23, Z24.D,LSL #3]

(172) 0x422264 FADD	Z24.D, Z31.D, Z24.D

(172) 0x422268 FADD	Z24.D, Z30.D, Z24.D

(172) 0x42226c MOVPRFX	Z30, Z18

(172) 0x422270 MUL	Z30.D, P0/M, Z30.D, Z25.D

(172) 0x422274 ADR	Z31.D, [Z30, Z27.D,SXTW]

(172) 0x422278 ADR	Z30.D, [Z30, Z26.D,SXTW]

(172) 0x42227c FMUL	Z24.D, Z28.D, Z24.D

(172) 0x422280 MOVPRFX	Z28, Z29

(172) 0x422284 MLA	Z28.D, P0/M, Z16.D, Z25.D

(172) 0x422288 ST1D	{Z24.D}, P0, [X13, Z28.D,LSL #3]

(172) 0x42228c MOVPRFX	Z28, Z29

(172) 0x422290 MLA	Z28.D, P0/M, Z17.D, Z25.D

(172) 0x422294 LDR	D24, [X19]

(172) 0x422298 LD1D	{Z28.D}, P0/Z, [X21, Z28.D,LSL #3]

(172) 0x42229c LD1D	{Z31.D}, P0/Z, [X22, Z31.D,LSL #3]

(172) 0x4222a0 LD1D	{Z30.D}, P0/Z, [X22, Z30.D,LSL #3]

(172) 0x4222a4 FADD	Z30.D, Z30.D, Z31.D

(172) 0x4222a8 MOVPRFX	Z31, Z19

(172) 0x4222ac MUL	Z31.D, P0/M, Z31.D, Z25.D

(172) 0x4222b0 ADR	Z27.D, [Z31, Z27.D,SXTW]

(172) 0x4222b4 ADR	Z26.D, [Z31, Z26.D,SXTW]

(172) 0x4222b8 MAD	Z25.D, P0/M, Z20.D, Z29.D

(172) 0x4222bc FMUL	D24, D24, D22

(172) 0x4222c0 LD1D	{Z27.D}, P0/Z, [X24, Z27.D,LSL #3]

(172) 0x4222c4 LD1D	{Z26.D}, P0/Z, [X24, Z26.D,LSL #3]

(172) 0x4222c8 DUP	Z24.D, Z24.D[0]

(172) 0x4222cc FADD	Z26.D, Z27.D, Z26.D

(172) 0x4222d0 FMUL	Z24.D, Z24.D, Z28.D

(172) 0x4222d4 FADD	Z26.D, Z30.D, Z26.D

(172) 0x4222d8 FMUL	Z24.D, Z24.D, Z26.D

(172) 0x4222dc ST1D	{Z24.D}, P0, [X25, Z25.D,LSL #3]

(172) 0x4222e0 B.NE	4221e0

0x4222e4 CBZ	X11, 422420

0x4222e8 LDP	X3, X2, [X29, #952]

0x4222ec LDP	X5, X4, [SP, #72]

0x4222f0 LDP	X7, X6, [SP, #56]

0x4222f4 FMOV	D0, #0.2500000

0x4222f8 UBFM	X13, X9, #32, #31

0x4222fc SBFM	X11, X3, #61, #31

0x422300 ADD	X10, X22, X11

0x422304 LDP	X27, X15, [SP, #24]

0x422308 ADD	X11, X24, X11

0x42230c ADD	X8, X10, #8

0x422310 ORR	X10, XZR, X25

0x422314 LDP	X25, X20, [SP, #8]

0x422318 ADD	X11, X11, #8

0x42231c STUR	X8, [X29, #464]

0x422320 LDUR	X8, [X29, #472]

0x422324 SUB	X12, XZR, X8,LSL #32

0x422328 SUB	W14, WZR, W8

0x42232c LDP	X8, X30, [SP, #40]

0x422330 HINT	#0

0x422334 HINT	#0

0x422338 HINT	#0

0x42233c HINT	#0

(171) 0x422340 LDUR	X16, [X29, #472]

(171) 0x422344 ADD	W18, W3, W9

(171) 0x422348 LDR	D1, [X19]

(171) 0x42234c SDIV	X16, X9, X16

(171) 0x422350 ADD	X9, X9, #1

(171) 0x422354 CMP	X26, X9

(171) 0x422358 FMUL	D1, D1, D0

(171) 0x42235c ADD	W17, W2, W16

(171) 0x422360 MADD	W18, W14, W16, W18

(171) 0x422364 MADD	X16, X12, X16, X13

(171) 0x422368 SBFM	X18, X18, #0, #31

(171) 0x42236c SBFM	X0, X17, #0, #31

(171) 0x422370 ADD	W17, W17, #1

(171) 0x422374 MADD	X1, X6, X0, X18

(171) 0x422378 SBFM	X17, X17, #0, #31

(171) 0x42237c LDR	D2, [X25, X1,LSL #3]

(171) 0x422380 MADD	X1, X27, X0, X18

(171) 0x422384 LDR	D3, [X28, X1,LSL #3]

(171) 0x422388 MADD	X1, X27, X17, X18

(171) 0x42238c MADD	X17, X20, X17, X18

(171) 0x422390 LDR	D4, [X23, X17,LSL #3]

(171) 0x422394 MADD	X17, X4, X0, X18

(171) 0x422398 FMUL	D1, D1, D2

(171) 0x42239c LDR	D2, [X28, X1,LSL #3]

(171) 0x4223a0 MADD	X1, X20, X0, X18

(171) 0x4223a4 FADD	D2, D2, D3

(171) 0x4223a8 LDR	D3, [X23, X1,LSL #3]

(171) 0x4223ac FADD	D3, D3, D4

(171) 0x4223b0 FADD	D2, D2, D3

(171) 0x4223b4 FMUL	D1, D1, D2

(171) 0x4223b8 STR	D1, [X5, X17,LSL #3]

(171) 0x4223bc MADD	X17, X8, X0, XZR

(171) 0x4223c0 LDR	D6, [X19]

(171) 0x4223c4 ADD	X1, X17, X18

(171) 0x4223c8 ADD	X17, X17, X16,ASR #32

(171) 0x4223cc LDR	D1, [X22, X1,LSL #3]

(171) 0x4223d0 MADD	X1, X30, X0, X18

(171) 0x4223d4 LDR	D2, [X21, X1,LSL #3]

(171) 0x4223d8 LDUR	X1, [X29, #464]

(171) 0x4223dc FMUL	D6, D6, D0

(171) 0x4223e0 LDR	D3, [X1, X17,LSL #3]

(171) 0x4223e4 MADD	X17, X15, X0, XZR

(171) 0x4223e8 ADD	X1, X17, X18

(171) 0x4223ec ADD	X16, X17, X16,ASR #32

(171) 0x4223f0 FMUL	D2, D6, D2

(171) 0x4223f4 LDR	D4, [X24, X1,LSL #3]

(171) 0x4223f8 LDR	D5, [X11, X16,LSL #3]

(171) 0x4223fc MADD	X16, X7, X0, X18

(171) 0x422400 MOVZ	X18, #1

(171) 0x422404 ADD	X13, X13, X18

(171) 0x422408 FADD	D1, D1, D4

(171) 0x42240c FADD	D3, D3, D5

(171) 0x422410 FADD	D1, D3, D1

(171) 0x422414 FMUL	D1, D2, D1

(171) 0x422418 STR	D1, [X10, X16,LSL #3]

(171) 0x42241c B.NE	422340

0x422420 LDUR	W1, [X29, #460]

0x422424 ADRP	X0,

0x422428 ADD	X0, X0, #1112

0x42242c BL	403260

0x422430 LDP	X20, X19, [SP, #240]

0x422434 LDP	X22, X21, [SP, #224]

0x422438 LDP	X24, X23, [SP, #208]

0x42243c LDP	X26, X25, [SP, #192]

0x422440 LDP	X28, X27, [SP, #176]

0x422444 LDP	X29, X30, [SP, #160]

0x422448 ADD	SP, SP, #256

0x42244c RET

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	flux_calc.cpp:36-40
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/flux_calc.cpp:36-40

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.67 to 15.00 cycles (1.64x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.67 to 1.00 cycles (24.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 528 bytes. The binary function is storing 248 bytes.

General properties

nb instructions	151
loop length	604
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

18.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	15.00	15.00	19.00	15.00	1.00	0.75	0.75	0.50	24.67	24.67	24.67	11.00	11.00
cycles	4.00	4.00	15.00	15.00	19.00	15.00	1.00	0.75	0.75	0.50	24.67	24.67	24.67	11.00	11.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	18.38
Overall L1	24.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.67 cycles. At this rate:

22% of peak load performance is reached (21.41 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (10.05 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 422010

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W27, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W10, W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 422430 <.omp_outlined.+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W20, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W17, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 422430 <.omp_outlined.+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X11, X10, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X13, X12, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADRP X0, <46308c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1088	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X15, X14, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X28, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X18, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X17, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR W1, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X18, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X16, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W11, W9, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UMADDL X26, W11, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X11, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X15, X16, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X14, X18, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X12, X13, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X13, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X8, X8, X26, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 422420 <.omp_outlined.+0x410>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X26, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X9, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X26, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4222e8 <.omp_outlined.+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X9, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FMOV D22, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MADD X12, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
INDEX Z0.D, X13, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
ADD X9, X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X13, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z2.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z6.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z7.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z1.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z3.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDUR X13, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z4.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z5.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z16.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X8, X13, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z17.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z18.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z20.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD W13, W27, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z19.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z21.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD W13, W20, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z23.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X11, 422420 <.omp_outlined.+0x410>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X3, X2, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X5, X4, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X7, X6, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
UBFM X13, X9, #32, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X11, X3, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X22, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X27, X15, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X11, X24, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X10, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X25, X20, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X11, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X12, XZR, X8,LSL #32	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SUB W14, WZR, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X8, X30, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
HINT #0
HINT #0
HINT #0
HINT #0
LDUR W1, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463424>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	flux_calc.cpp:36-40
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/flux_calc.cpp:36-40

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.67 to 1.00 cycles (24.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 528 bytes. The binary function is storing 248 bytes.

General properties

nb instructions	151
loop length	604
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

18.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	15.00	15.00	19.00	15.00	1.00	0.75	0.75	0.50	24.67	24.67	24.67	11.00	11.00
cycles	4.00	4.00	15.00	15.00	19.00	15.00	1.00	0.75	0.75	0.50	24.67	24.67	24.67	11.00	11.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	18.38
Overall L1	24.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.67 cycles. At this rate:

22% of peak load performance is reached (21.41 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (10.05 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 422010

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W27, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W10, W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 422430 <.omp_outlined.+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W20, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W17, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 422430 <.omp_outlined.+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X11, X10, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X13, X12, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADRP X0, <46308c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1088	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X15, X14, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X28, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X18, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X17, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR W1, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X18, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X16, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W11, W9, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UMADDL X26, W11, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X11, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X15, X16, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X14, X18, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X12, X13, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X13, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X8, X8, X26, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 422420 <.omp_outlined.+0x410>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X26, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X9, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X26, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4222e8 <.omp_outlined.+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X9, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FMOV D22, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MADD X12, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
INDEX Z0.D, X13, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
ADD X9, X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X13, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z2.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z6.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z7.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z1.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z3.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDUR X13, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z4.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z5.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z16.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X8, X13, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z17.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z18.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z20.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD W13, W27, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z19.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z21.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD W13, W20, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z23.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X11, 422420 <.omp_outlined.+0x410>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X3, X2, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X5, X4, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X7, X6, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
UBFM X13, X9, #32, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X11, X3, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X22, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X27, X15, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X11, X24, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X10, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X25, X20, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X11, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X12, XZR, X8,LSL #32	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SUB W14, WZR, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X8, X30, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
HINT #0
HINT #0
HINT #0
HINT #0
LDUR W1, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463424>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined.#0x422010–	2.91	1.57
○Loop 172 - flux_calc.cpp:36-40 - exec	2.91	1.57
○Loop 171 - flux_calc.cpp:37-40 - exec	0	0

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