OV - exec - Function .omp_outlined.#0x41fff0

	Function: .omp_outlined.#0x41fff0	Module: exec	Source: calc_dt.cpp:49-75 [...]	Coverage: 6.46%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

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69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/calc_dt.cpp: 49 - 75

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49: #pragma omp parallel for simd collapse(2) reduction(min : dt_min_val0)

50:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

51:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

52:       double dsx = celldx[i];

53:       double dsy = celldy[j];

54:       double cc = soundspeed(i, j) * soundspeed(i, j);

55:       cc = cc + 2.0 * viscosity_a(i, j) / density0(i, j);

56:       cc = std::fmax(std::sqrt(cc), g_small);

57:       double dtct = dtc_safe * std::fmin(dsx, dsy) / cc;

58:       double div = 0.0;

59:       double dv1 = (xvel0(i, j) + xvel0(i + 0, j + 1)) * xarea(i, j);

60:       double dv2 = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) * xarea(i + 1, j + 0);

61:       div = div + dv2 - dv1;

62:       double dtut = dtu_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

63:       dv1 = (yvel0(i, j) + yvel0(i + 1, j + 0)) * yarea(i, j);

64:       dv2 = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) * yarea(i + 0, j + 1);

65:       div = div + dv2 - dv1;

66:       double dtvt = dtv_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

67:       div = div / (2.0 * volume(i, j));

68:       double dtdivt;

69:       if (div < -g_small) {

70:         dtdivt = dtdiv_safe * (-1.0 / div);

71:       } else {

72:         dtdivt = g_big;

73:       }

74:       double mins = std::fmin(dtct, std::fmin(dtut, std::fmin(dtvt, std::fmin(dtdivt, g_big))));

75:       dt_min_val0 = std::fmin(mins, dt_min_val0);

0x41fff0 STP	D15, D14, [SP, #864]!

0x41fff4 STP	D13, D12, [SP, #16]

0x41fff8 STP	D11, D10, [SP, #32]

0x41fffc STP	D9, D8, [SP, #48]

0x420000 STP	X29, X30, [SP, #64]

0x420004 STP	X28, X27, [SP, #80]

0x420008 STP	X26, X25, [SP, #96]

0x42000c STP	X24, X23, [SP, #112]

0x420010 STP	X22, X21, [SP, #128]

0x420014 STP	X20, X19, [SP, #144]

0x420018 ADD	X29, SP, #64

0x42001c ADDVL	SP, SP, #58

0x420020 SUB	SP, SP, #224

0x420024 LDR	W20, [X2]

0x420028 LDR	W8, [X3]

0x42002c ADD	W10, W20, #1

0x420030 ADD	W8, W8, #2

0x420034 SUBS	W8, W8, W10

0x420038 B.LE	420748

0x42003c LDR	W11, [X4]

0x420040 LDR	W9, [X5]

0x420044 ADD	W4, W11, #1

0x420048 ADD	W9, W9, #2

0x42004c CMP	W9, W4

0x420050 B.LE	420748

0x420054 LDP	X3, X2, [X29, #96]

0x420058 LDR	X5, [X6, #8]

0x42005c STR	X10, [SP, #120]

0x420060 LDR	X10, [X29, #192]

0x420064 LDP	X15, X14, [X29, #144]

0x420068 STR	W11, [SP, #60]

0x42006c LDP	X1, X18, [X29, #112]

0x420070 LDP	X13, X12, [X29, #160]

0x420074 LDP	X17, X16, [X29, #128]

0x420078 LDR	X6, [X7, #8]

0x42007c MOVZ	W7, #1

0x420080 STR	W20, [SP, #108]

0x420084 STR	X4, [SP, #112]

0x420088 STR	WZR, [SP, #196]

0x42008c STR	X5, [SP, #160]

0x420090 LDR	X5, [X3]

0x420094 LDR	X3, [X3, #16]

0x420098 STR	X10, [SP, #64]

0x42009c LDP	X11, X10, [X29, #176]

0x4200a0 LDR	X24, [X14]

0x4200a4 LDR	X14, [X14, #16]

0x4200a8 LDR	D8, [X18]

0x4200ac LDR	D9, [X15]

0x4200b0 LDR	X20, [X1]

0x4200b4 LDR	X21, [X1, #16]

0x4200b8 LDR	X23, [X13, #16]

0x4200bc LDR	W1, [X0]

0x4200c0 ADRP	X0,

0x4200c4 ADD	X0, X0, #896

0x4200c8 LDR	X25, [X17]

0x4200cc LDR	X27, [X17, #16]

0x4200d0 LDR	X22, [X16]

0x4200d4 LDR	X19, [X16, #16]

0x4200d8 LDR	X26, [X12, #16]

0x4200dc STP	X3, X5, [SP, #88]

0x4200e0 ADD	X5, SP, #208

0x4200e4 LDR	X3, [X2]

0x4200e8 LDR	X2, [X2, #16]

0x4200ec LDR	D10, [X11]

0x4200f0 SUB	W11, W9, W4

0x4200f4 MOVN	X9, #0

0x4200f8 ADD	X4, SP, #216

0x4200fc UMADDL	X28, W11, W8, X9

0x420100 MOVZ	W8, #1

0x420104 LDR	D11, [X10]

0x420108 STR	X11, [SP, #168]

0x42010c STR	W1, [SP, #104]

0x420110 STR	X8, [SP, #200]

0x420114 STP	X14, X2, [SP, #72]

0x420118 MOVZ	W2, #34

0x42011c LDR	X14, [X13]

0x420120 LDR	X13, [X12]

0x420124 STP	X3, X6, [SP, #144]

0x420128 ADD	X3, SP, #196

0x42012c ADD	X6, SP, #200

0x420130 STP	X28, XZR, [SP, #208]

0x420134 STR	X8, [SP]

0x420138 STP	X13, X14, [SP, #128]

0x42013c BL	4033a0

0x420140 LDP	X8, X9, [SP, #208]

0x420144 CMP	X8, X28

0x420148 CSEL	X8, X8, X28, #11

0x42014c CMP	X9, X8

0x420150 STR	X8, [SP, #208]

0x420154 B.LE	420164

0x420158 MOVN	X8, #32784

0x42015c FMOV	D1, X8

0x420160 B	420690

0x420164 ADD	X18, X8, #1

0x420168 CNTD	X10, ALL

0x42016c FNEG	D30, D11

0x420170 MOVN	X13, #32784

0x420174 SUB	X11, X18, X9

0x420178 CMP	X11, X10

0x42017c B.CS	420190

0x420180 LDP	X28, X1, [SP, #112]

0x420184 LDR	X17, [SP, #168]

0x420188 FMOV	D1, X13

0x42018c B	420478

0x420190 DUP	Z0.D, X10

0x420194 SUB	X8, X29, #64

0x420198 PTRUE	P0.D, ALL

0x42019c DUP	Z25.D, Z30.D[0]

0x4201a0 DUP	Z17.D, Z8.D[0]

0x4201a4 DUP	Z21.D, Z9.D[0]

0x4201a8 DUP	Z24.D, Z10.D[0]

0x4201ac STR	Z0, [X8, #511, MUL VL]

0x4201b0 SUB	X8, X29, #64

0x4201b4 UDIV	X12, X11, X10

0x4201b8 LDR	X1, [SP, #120]

0x4201bc LDR	X17, [SP, #168]

0x4201c0 MADD	X12, X12, X10, XZR

0x4201c4 SUB	X11, X11, X12

0x4201c8 INDEX	Z1.D, X9, #1

0x4201cc ADD	X9, X9, X12

0x4201d0 DUP	Z0.D, X1

0x4201d4 STR	Z0, [X8, #510, MUL VL]

0x4201d8 LDR	X28, [SP, #112]

0x4201dc SUB	X8, X29, #64

0x4201e0 DUP	Z0.D, X28

0x4201e4 STR	Z0, [X8, #509, MUL VL]

0x4201e8 LDR	X8, [SP, #96]

0x4201ec DUP	Z3.D, X17

0x4201f0 DUP	Z18.D, X25

0x4201f4 DUP	Z19.D, X22

0x4201f8 DUP	Z20.D, X24

0x4201fc DUP	Z0.D, X8

0x420200 SUB	X8, X29, #64

0x420204 STR	Z0, [X8, #508, MUL VL]

0x420208 LDR	X8, [SP, #144]

0x42020c DUP	Z0.D, X8

0x420210 SUB	X8, X29, #64

0x420214 STR	Z0, [X8, #507, MUL VL]

0x420218 SUB	X8, X29, #64

0x42021c DUP	Z0.D, X20

0x420220 STR	Z0, [X8, #506, MUL VL]

0x420224 STP	D30, D10, [SP, #24]

0x420228 STP	D9, D8, [SP, #40]

0x42022c LDR	X8, [SP, #136]

0x420230 LDR	X16, [SP, #72]

0x420234 DUP	Z30.D, X13

0x420238 DUP	Z22.D, X8

0x42023c LDR	X8, [SP, #128]

0x420240 DUP	Z23.D, X8

0x420244 LDR	W8, [SP, #108]

0x420248 ADD	W14, W8, #2

0x42024c LDR	W8, [SP, #60]

0x420250 DUP	Z26.D, X14

0x420254 ADD	W14, W8, #2

0x420258 LDP	X13, X8, [SP, #152]

0x42025c DUP	Z27.D, X14

0x420260 ADRP	X14, 43e260

0x420264 ADD	X14, X14, #2032

0x420268 LD1RD	{Z28.D}, P0/Z, [X14]

0x42026c ADRP	X14,

0x420270 ADD	X14, X14, #1016

0x420274 LD1RD	{Z29.D}, P0/Z, [X14]

0x420278 ADRP	X14,

0x42027c ADD	X14, X14, #1024

0x420280 LD1RD	{Z31.D}, P0/Z, [X14]

0x420284 LDP	X15, X14, [SP, #80]

(180) 0x420288 SUB	X30, X29, #64

(180) 0x42028c MOVPRFX	Z12, Z1

(180) 0x420290 SDIV	Z12.D, P0/M, Z12.D, Z3.D

(180) 0x420294 MOVPRFX	Z14, Z1

(180) 0x420298 MLS	Z14.D, P0/M, Z12.D, Z3.D

(180) 0x42029c SUBS	X12, X12, X10

(180) 0x4202a0 LDR	Z0, [X30, #510, MUL VL]

(180) 0x4202a4 SUB	X30, X29, #64

(180) 0x4202a8 ADD	Z13.D, Z0.D, Z12.D

(180) 0x4202ac LDR	Z0, [X30, #509, MUL VL]

(180) 0x4202b0 SUB	X30, X29, #64

(180) 0x4202b4 MOVPRFX	Z9, Z13

(180) 0x4202b8 SXTW	Z9.D, P0/M, Z13.D

(180) 0x4202bc ADD	Z12.D, Z26.D, Z12.D

(180) 0x4202c0 MOVPRFX	Z4, Z18

(180) 0x4202c4 MUL	Z4.D, P0/M, Z4.D, Z9.D

(180) 0x4202c8 SXTW	Z12.D, P0/M, Z12.D

(180) 0x4202cc MOVPRFX	Z6, Z18

(180) 0x4202d0 MUL	Z6.D, P0/M, Z6.D, Z12.D

(180) 0x4202d4 ADD	Z15.D, Z0.D, Z14.D

(180) 0x4202d8 MOVPRFX	Z11, Z15

(180) 0x4202dc SXTW	Z11.D, P0/M, Z15.D

(180) 0x4202e0 LD1D	{Z8.D}, P0/Z, [X8, Z15.D,SXTW #3]

(180) 0x4202e4 LD1D	{Z13.D}, P0/Z, [X13, Z13.D,SXTW #3]

(180) 0x4202e8 LDR	Z0, [X30, #508, MUL VL]

(180) 0x4202ec SUB	X30, X29, #64

(180) 0x4202f0 MOVPRFX	Z10, Z11

(180) 0x4202f4 MLA	Z10.D, P0/M, Z0.D, Z9.D

(180) 0x4202f8 LD1D	{Z10.D}, P0/Z, [X14, Z10.D,LSL #3]

(180) 0x4202fc ADR	Z5.D, [Z4, Z15.D,SXTW]

(180) 0x420300 ADR	Z7.D, [Z6, Z15.D,SXTW]

(180) 0x420304 LDR	Z0, [X30, #507, MUL VL]

(180) 0x420308 SUB	X30, X29, #64

(180) 0x42030c FMINNM	Z8.D, P0/M, Z8.D, Z13.D

(180) 0x420310 MAD	Z0.D, P0/M, Z9.D, Z11.D

(180) 0x420314 LD1D	{Z0.D}, P0/Z, [X15, Z0.D,LSL #3]

(180) 0x420318 LDR	Z2, [X30, #506, MUL VL]

(180) 0x42031c SUB	X30, X29, #64

(180) 0x420320 FADD	Z0.D, Z0.D, Z0.D

(180) 0x420324 MAD	Z2.D, P0/M, Z9.D, Z11.D

(180) 0x420328 LD1D	{Z2.D}, P0/Z, [X21, Z2.D,LSL #3]

(180) 0x42032c LD1D	{Z5.D}, P0/Z, [X27, Z5.D,LSL #3]

(180) 0x420330 LD1D	{Z7.D}, P0/Z, [X27, Z7.D,LSL #3]

(180) 0x420334 FADD	Z5.D, Z7.D, Z5.D

(180) 0x420338 MOVPRFX	Z7, Z19

(180) 0x42033c MUL	Z7.D, P0/M, Z7.D, Z9.D

(180) 0x420340 ADR	Z16.D, [Z7, Z15.D,SXTW]

(180) 0x420344 FDIV	Z0.D, P0/M, Z0.D, Z2.D

(180) 0x420348 LD1D	{Z16.D}, P0/Z, [X19, Z16.D,LSL #3]

(180) 0x42034c FMUL	Z5.D, Z5.D, Z16.D

(180) 0x420350 ADD	Z16.D, Z27.D, Z14.D

(180) 0x420354 ADR	Z4.D, [Z4, Z16.D,SXTW]

(180) 0x420358 ADR	Z6.D, [Z6, Z16.D,SXTW]

(180) 0x42035c LD1D	{Z4.D}, P0/Z, [X27, Z4.D,LSL #3]

(180) 0x420360 LD1D	{Z6.D}, P0/Z, [X27, Z6.D,LSL #3]

(180) 0x420364 FADD	Z4.D, Z6.D, Z4.D

(180) 0x420368 ADR	Z6.D, [Z7, Z16.D,SXTW]

(180) 0x42036c MOVPRFX	Z7, Z22

(180) 0x420370 MUL	Z7.D, P0/M, Z7.D, Z9.D

(180) 0x420374 ADR	Z2.D, [Z7, Z15.D,SXTW]

(180) 0x420378 ADR	Z7.D, [Z7, Z16.D,SXTW]

(180) 0x42037c FMLA	Z0.D, P0/M, Z10.D, Z10.D

(180) 0x420380 LD1D	{Z6.D}, P0/Z, [X19, Z6.D,LSL #3]

(180) 0x420384 FSQRT	Z0.D, P0/M, Z0.D

(180) 0x420388 FMUL	Z4.D, Z4.D, Z6.D

(180) 0x42038c MOVPRFX	Z6, Z11

(180) 0x420390 MLA	Z6.D, P0/M, Z20.D, Z9.D

(180) 0x420394 LD1D	{Z6.D}, P0/Z, [X16, Z6.D,LSL #3]

(180) 0x420398 LD1D	{Z2.D}, P0/Z, [X23, Z2.D,LSL #3]

(180) 0x42039c LD1D	{Z7.D}, P0/Z, [X23, Z7.D,LSL #3]

(180) 0x4203a0 MOVPRFX	Z10, Z4

(180) 0x4203a4 FABS	Z10.D, P0/M, Z4.D

(180) 0x4203a8 FADD	Z2.D, Z7.D, Z2.D

(180) 0x4203ac MOVPRFX	Z7, Z11

(180) 0x4203b0 MLA	Z7.D, P0/M, Z23.D, Z9.D

(180) 0x4203b4 LD1D	{Z7.D}, P0/Z, [X26, Z7.D,LSL #3]

(180) 0x4203b8 FMUL	Z2.D, Z2.D, Z7.D

(180) 0x4203bc MOVPRFX	Z7, Z22

(180) 0x4203c0 MUL	Z7.D, P0/M, Z7.D, Z12.D

(180) 0x4203c4 ADR	Z9.D, [Z7, Z15.D,SXTW]

(180) 0x4203c8 ADR	Z7.D, [Z7, Z16.D,SXTW]

(180) 0x4203cc LD1D	{Z16.D}, P0/Z, [X23, Z9.D,LSL #3]

(180) 0x4203d0 LD1D	{Z7.D}, P0/Z, [X23, Z7.D,LSL #3]

(180) 0x4203d4 MOVPRFX	Z9, Z11

(180) 0x4203d8 MLA	Z9.D, P0/M, Z23.D, Z12.D

(180) 0x4203dc LD1D	{Z9.D}, P0/Z, [X26, Z9.D,LSL #3]

(180) 0x4203e0 FADD	Z7.D, Z7.D, Z16.D

(180) 0x4203e4 MOVPRFX	Z16, Z5

(180) 0x4203e8 FABS	Z16.D, P0/M, Z5.D

(180) 0x4203ec FADD	Z5.D, Z5.D, Z2.D

(180) 0x4203f0 FABS	Z2.D, P0/M, Z2.D

(180) 0x4203f4 FMAXNM	Z16.D, P0/M, Z16.D, Z10.D

(180) 0x4203f8 FMAXNM	Z0.D, P0/M, Z0.D, Z28.D

(180) 0x4203fc FMUL	Z7.D, Z7.D, Z9.D

(180) 0x420400 FSUB	Z4.D, Z4.D, Z5.D

(180) 0x420404 FADD	Z9.D, Z6.D, Z6.D

(180) 0x420408 FMUL	Z6.D, Z6.D, Z28.D

(180) 0x42040c FMUL	Z5.D, Z9.D, Z21.D

(180) 0x420410 FADD	Z4.D, Z4.D, Z7.D

(180) 0x420414 FABS	Z7.D, P0/M, Z7.D

(180) 0x420418 FMAXNM	Z16.D, P0/M, Z16.D, Z6.D

(180) 0x42041c FDIV	Z4.D, P0/M, Z4.D, Z9.D

(180) 0x420420 FMAXNM	Z2.D, P0/M, Z2.D, Z7.D

(180) 0x420424 FDIV	Z5.D, P0/M, Z5.D, Z16.D

(180) 0x420428 FMAXNM	Z2.D, P0/M, Z2.D, Z6.D

(180) 0x42042c FMUL	Z6.D, Z9.D, Z24.D

(180) 0x420430 FDIVR	Z2.D, P0/M, Z2.D, Z6.D

(180) 0x420434 FMUL	Z6.D, Z8.D, Z17.D

(180) 0x420438 FDIVR	Z0.D, P0/M, Z0.D, Z6.D

(180) 0x42043c FCMGT	P1.D, P0/Z, Z29.D, Z4.D

(180) 0x420440 FDIVR	Z4.D, P0/M, Z4.D, Z25.D

(180) 0x420444 SEL	Z4.D, P1, Z4.D, Z31.D

(180) 0x420448 FMINNM	Z4.D, P0/M, Z4.D, Z31.D

(180) 0x42044c FMINNM	Z2.D, P0/M, Z2.D, Z4.D

(180) 0x420450 FMINNM	Z2.D, P0/M, Z2.D, Z5.D

(180) 0x420454 FMINNM	Z0.D, P0/M, Z0.D, Z2.D

(180) 0x420458 LDR	Z2, [X30, #511, MUL VL]

(180) 0x42045c FMINNM	Z30.D, P0/M, Z30.D, Z0.D

(180) 0x420460 ADD	Z1.D, Z1.D, Z2.D

(180) 0x420464 B.NE	420288

0x420468 FMINNMV	D1, P0, Z30.D

0x42046c LDP	D9, D8, [SP, #40]

0x420470 LDP	D30, D10, [SP, #24]

0x420474 CBZ	X11, 420690

0x420478 ADRP	X16,

0x42047c SBFM	X12, X28, #61, #31

0x420480 UBFM	X14, X9, #32, #31

0x420484 LDR	D2, [X16, #2032]

0x420488 ADRP	X16,

0x42048c ADD	X11, X19, X12

0x420490 ADD	X10, X27, X12

0x420494 ADD	X12, X23, X12

0x420498 LDR	D3, [X16, #1016]

0x42049c ADRP	X16,

0x4204a0 LDR	D4, [X16, #1024]

0x4204a4 ADD	X8, X11, #8

0x4204a8 LDP	X16, X30, [SP, #88]

0x4204ac ORR	X11, XZR, X20

0x4204b0 LDP	X13, X20, [SP, #72]

0x4204b4 ADD	X10, X10, #8

0x4204b8 ADD	X12, X12, #8

0x4204bc STR	X8, [SP, #120]

0x4204c0 SUB	X8, XZR, X17,LSL #32

0x4204c4 STR	X8, [SP, #112]

0x4204c8 SUB	W8, WZR, W17

0x4204cc STR	W8, [SP, #108]

0x4204d0 HINT	#0

0x4204d4 HINT	#0

0x4204d8 HINT	#0

0x4204dc HINT	#0

(182) 0x4204e0 SDIV	X0, X9, X17

(182) 0x4204e4 ORR	X15, XZR, X18

(182) 0x4204e8 LDR	W18, [SP, #108]

(182) 0x4204ec ADD	W17, W28, W9

(182) 0x4204f0 ORR	X8, XZR, X1

(182) 0x4204f4 LDR	X3, [SP, #144]

(182) 0x4204f8 ADD	X9, X9, #1

(182) 0x4204fc ADD	W1, W8, W0

(182) 0x420500 MADD	W18, W18, W0, W17

(182) 0x420504 SBFM	X17, X18, #0, #31

(182) 0x420508 SBFM	X2, X1, #0, #31

(182) 0x42050c MADD	X3, X3, X2, X17

(182) 0x420510 LDR	D0, [X20, X3,LSL #3]

(182) 0x420514 MADD	X3, X11, X2, X17

(182) 0x420518 LDR	D5, [X21, X3,LSL #3]

(182) 0x42051c MADD	X3, X25, X2, XZR

(182) 0x420520 ADD	X4, X3, X17

(182) 0x420524 LDR	D6, [X27, X4,LSL #3]

(182) 0x420528 ADD	W4, W1, #1

(182) 0x42052c FADD	D0, D0, D0

(182) 0x420530 SBFM	X4, X4, #0, #31

(182) 0x420534 MADD	X5, X25, X4, XZR

(182) 0x420538 FDIV	D0, D0, D5

(182) 0x42053c ADD	X6, X5, X17

(182) 0x420540 LDR	D7, [X27, X6,LSL #3]

(182) 0x420544 MADD	X6, X22, X2, XZR

(182) 0x420548 ADD	X7, X6, X17

(182) 0x42054c LDR	D16, [X19, X7,LSL #3]

(182) 0x420550 MADD	X7, X30, X2, X17

(182) 0x420554 LDR	D17, [X16, X7,LSL #3]

(182) 0x420558 LDR	X7, [SP, #112]

(182) 0x42055c FADD	D5, D7, D6

(182) 0x420560 MADD	X0, X7, X0, X14

(182) 0x420564 FMUL	D5, D5, D16

(182) 0x420568 ADD	X3, X3, X0,ASR #32

(182) 0x42056c FMADD	D0, D17, D17, D0

(182) 0x420570 FABS	D17, D5

(182) 0x420574 LDR	D18, [X10, X3,LSL #3]

(182) 0x420578 ADD	X3, X5, X0,ASR #32

(182) 0x42057c LDR	X5, [SP, #136]

(182) 0x420580 LDR	D19, [X10, X3,LSL #3]

(182) 0x420584 ADD	X3, X6, X0,ASR #32

(182) 0x420588 LDR	X6, [SP, #120]

(182) 0x42058c FSQRT	D0, D0

(182) 0x420590 LDR	D20, [X6, X3,LSL #3]

(182) 0x420594 MADD	X3, X24, X2, X17

(182) 0x420598 LDR	D21, [X13, X3,LSL #3]

(182) 0x42059c LDR	X3, [SP, #152]

(182) 0x4205a0 FADD	D7, D19, D18

(182) 0x4205a4 LDR	D22, [X3, X1,SXTW #3]

(182) 0x4205a8 MADD	X1, X5, X2, XZR

(182) 0x4205ac FMUL	D7, D7, D20

(182) 0x4205b0 ADD	X3, X1, X17

(182) 0x4205b4 ADD	X1, X1, X0,ASR #32

(182) 0x4205b8 FADD	D16, D21, D21

(182) 0x4205bc FMUL	D19, D21, D2

(182) 0x4205c0 FABS	D18, D7

(182) 0x4205c4 LDR	D23, [X23, X3,LSL #3]

(182) 0x4205c8 LDR	X3, [SP, #128]

(182) 0x4205cc LDR	D24, [X12, X1,LSL #3]

(182) 0x4205d0 FMAXNM	D17, D17, D18

(182) 0x4205d4 FMUL	D18, D16, D9

(182) 0x4205d8 FMAXNM	D0, D0, D2

(182) 0x4205dc FMAXNM	D17, D17, D19

(182) 0x4205e0 MADD	X1, X3, X2, X17

(182) 0x4205e4 FDIV	D17, D18, D17

(182) 0x4205e8 LDR	D25, [X26, X1,LSL #3]

(182) 0x4205ec MADD	X1, X5, X4, XZR

(182) 0x4205f0 LDR	X5, [SP, #160]

(182) 0x4205f4 FADD	D18, D24, D23

(182) 0x4205f8 ADD	X2, X1, X17

(182) 0x4205fc MADD	X17, X3, X4, X17

(182) 0x420600 LDR	D26, [X5, X18,SXTW #3]

(182) 0x420604 ADD	X18, X1, X0,ASR #32

(182) 0x420608 LDR	D27, [X23, X2,LSL #3]

(182) 0x42060c LDR	D29, [X26, X17,LSL #3]

(182) 0x420610 LDR	X17, [SP, #168]

(182) 0x420614 ORR	X1, XZR, X8

(182) 0x420618 MOVZ	X8, #1

(182) 0x42061c ADD	X14, X14, X8

(182) 0x420620 LDR	D28, [X12, X18,LSL #3]

(182) 0x420624 FMUL	D18, D18, D25

(182) 0x420628 ORR	X18, XZR, X15

(182) 0x42062c FADD	D5, D5, D18

(182) 0x420630 FABS	D18, D18

(182) 0x420634 FMINNM	D6, D26, D22

(182) 0x420638 FSUB	D5, D7, S5

(182) 0x42063c FMUL	D7, D16, D10

(182) 0x420640 FADD	D20, D28, D27

(182) 0x420644 FMUL	D6, D6, D8

(182) 0x420648 FMUL	D20, D20, D29

(182) 0x42064c FDIV	D0, D6, D0

(182) 0x420650 FADD	D5, D5, D20

(182) 0x420654 FABS	D20, D20

(182) 0x420658 FDIV	D5, D5, D16

(182) 0x42065c FMAXNM	D18, D18, D20

(182) 0x420660 FMAXNM	D18, D18, D19

(182) 0x420664 FDIV	D7, D7, D18

(182) 0x420668 FDIV	D16, D30, D5

(182) 0x42066c FCMP	D5, D3

(182) 0x420670 FCSEL	D5, D16, D4, #11

(182) 0x420674 CMP	X15, X9

(182) 0x420678 FMINNM	D5, D5, D4

(182) 0x42067c FMINNM	D5, D7, D5

(182) 0x420680 FMINNM	D5, D17, D5

(182) 0x420684 FMINNM	D0, D0, D5

(182) 0x420688 FMINNM	D1, D0, D1

(182) 0x42068c B.NE	4204e0

0x420690 LDR	W19, [SP, #104]

0x420694 ADRP	X0,

0x420698 ADD	X0, X0, #920

0x42069c STR	D1, [SP, #184]

0x4206a0 ORR	W1, WZR, W19

0x4206a4 BL	403260

0x4206a8 ADD	X8, SP, #184

0x4206ac ADRP	X6,

0x4206b0 ORR	W1, WZR, W19

0x4206b4 ADRP	X0,

0x4206b8 ADD	X0, X0, #944

0x4206bc STR	X8, [SP, #176]

0x4206c0 ADRP	X5,

0x4206c4 ADD	X5, X5, #4048

0x4206c8 ADD	X4, SP, #176

0x4206cc LDR	X6, [X6, #3960]

0x4206d0 MOVZ	W2, #1

0x4206d4 MOVZ	W3, #8

0x4206d8 BL	4031e0

0x4206dc CMP	W0, #2

0x4206e0 B.EQ	42071c

0x4206e4 CMP	W0, #1

0x4206e8 B.NE	420748

0x4206ec LDR	X8, [SP, #64]

0x4206f0 LDR	D1, [SP, #184]

0x4206f4 ADRP	X2,

0x4206f8 ORR	W1, WZR, W19

0x4206fc ADRP	X0,

0x420700 ADD	X0, X0, #944

0x420704 LDR	D0, [X8]

0x420708 FMINNM	D0, D0, D1

0x42070c STR	D0, [X8]

0x420710 LDR	X2, [X2, #3960]

0x420714 BL	402fb0

0x420718 B	420748

0x42071c LDR	X11, [SP, #64]

0x420720 LDR	X8, [X11]

0x420724 LDR	D0, [SP, #184]

0x420728 ORR	X9, XZR, X8

(181) 0x42072c FMOV	D1, X8

(181) 0x420730 FMINNM	D1, D0, D1

(181) 0x420734 FMOV	X10, D1

(181) 0x420738 CAS	X9, X10, [X11]

(181) 0x42073c CMP	X9, X8

(181) 0x420740 ORR	X8, XZR, X9

(181) 0x420744 B.NE	42072c

0x420748 ADDVL	SP, SP, #6

0x42074c ADD	SP, SP, #224

0x420750 LDP	D9, D8, [SP, #48]

0x420754 LDP	D11, D10, [SP, #32]

0x420758 LDP	D13, D12, [SP, #16]

0x42075c LDP	X20, X19, [SP, #144]

0x420760 LDP	X22, X21, [SP, #128]

0x420764 LDP	X24, X23, [SP, #112]

0x420768 LDP	X26, X25, [SP, #96]

0x42076c LDP	X28, X27, [SP, #80]

0x420770 LDP	X29, X30, [SP, #64]

0x420774 LDP	D15, D14, [SP], #160

0x420778 RET

0x42077c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/calc_dt.cpp:49-75

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 39.67 to 18.00 cycles (2.20x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 42% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 39.67 to 33.96 cycles (1.17x speedup).

Details

35% of VPU instructions are used in vector version (process two or more data elements in vector registers):

31% of VPU loads are used in vector version.
85% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
17% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 39.67 to 2.00 cycles (19.83x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 784 bytes. The binary function is storing 588 bytes.

General properties

nb instructions	249
loop length	996
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

30.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.50	7.50	26.50	26.50	26.50	26.50	7.00	7.00	5.50	5.50	39.67	39.67	39.67	13.50	13.50
cycles	7.50	7.50	26.50	26.50	26.50	26.50	7.00	7.00	5.50	5.50	39.67	39.67	39.67	13.50	13.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	30.50
Overall L1	39.67

Vectorization ratios

INT

all	34%
load	31%
store	85%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	14%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	35%
load	31%
store	85%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 39.67 cycles. At this rate:

20% of peak load performance is reached (19.76 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41fff0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP D15, D14, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL SP, SP, #58	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB SP, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W10, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 420748 <.omp_outlined.+0x758>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W11, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W4, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 420748 <.omp_outlined.+0x758>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X3, X2, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X5, [X6, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X15, X14, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR W11, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X1, X18, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X13, X12, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X17, X16, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X6, [X7, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W20, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #196]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X5, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X11, X10, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X24, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D8, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D9, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X20, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4630c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #896	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X25, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X3, X5, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X5, SP, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SUB W11, W9, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #216	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UMADDL X28, W11, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR X11, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W1, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X14, X2, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X3, X6, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, SP, #196	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #200	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X28, XZR, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X13, X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X8, X8, X28, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR X8, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LE 420164 <.omp_outlined.+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVN X8, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D1, X8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 420690 <.omp_outlined.+0x6a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X18, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FNEG D30, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVN X13, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X18, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 420190 <.omp_outlined.+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X28, X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X17, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D1, X13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 420478 <.omp_outlined.+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
DUP Z0.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z25.D, Z30.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
DUP Z17.D, Z8.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
DUP Z21.D, Z9.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
DUP Z24.D, Z10.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
STR Z0, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UDIV X12, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
LDR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X12, X12, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
INDEX Z1.D, X9, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
ADD X9, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.D, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
STR Z0, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LDR X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.D, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
STR Z0, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z3.D, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z18.D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z19.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z20.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z0.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z0, [X8, #508, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z0.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z0, [X8, #507, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
STR Z0, [X8, #506, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STP D30, D10, [SP, #24]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D9, D8, [SP, #40]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z30.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z22.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z23.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR W8, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W14, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W8, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z26.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD W14, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X13, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z27.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADRP X14, 43e260 <.omp_outlined.+0x640>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, #2032	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z28.D}, P0/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADRP X14, <44126c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, #1016	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z29.D}, P0/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADRP X14, <441278>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, #1024	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z31.D}, P0/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LDP X15, X14, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMINNMV D1, P0, Z30.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2
LDP D9, D8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D30, D10, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
CBZ X11, 420690 <.omp_outlined.+0x6a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X16, <43e478>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X12, X28, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X14, X9, #32, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X16, #2032]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADRP X16, <441488>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X19, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X27, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X23, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X16, #1016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADRP X16, <44149c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X16, #1024]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X8, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X16, X30, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X11, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X13, X20, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X8, XZR, X17,LSL #32	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, WZR, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
LDR W19, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463694>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #920	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D1, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, SP, #184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X6, <4656ac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4636b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #944	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X5, <20041f6c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, #4048	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [X6, #3960]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4031e0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42071c <.omp_outlined.+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 420748 <.omp_outlined.+0x758>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D1, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADRP X2, <4656f4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4636fc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #944	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMINNM D0, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR X2, [X2, #3960]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 402fb0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 420748 <.omp_outlined.+0x758>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ORR X9, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL SP, SP, #6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD SP, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D15, D14, [SP], #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/calc_dt.cpp:49-75

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

35% of VPU instructions are used in vector version (process two or more data elements in vector registers):

31% of VPU loads are used in vector version.
85% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
17% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 39.67 to 2.00 cycles (19.83x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 784 bytes. The binary function is storing 588 bytes.

General properties

nb instructions	249
loop length	996
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

30.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.50	7.50	26.50	26.50	26.50	26.50	7.00	7.00	5.50	5.50	39.67	39.67	39.67	13.50	13.50
cycles	7.50	7.50	26.50	26.50	26.50	26.50	7.00	7.00	5.50	5.50	39.67	39.67	39.67	13.50	13.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	30.50
Overall L1	39.67

Vectorization ratios

INT

all	34%
load	31%
store	85%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	14%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	35%
load	31%
store	85%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 39.67 cycles. At this rate:

20% of peak load performance is reached (19.76 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41fff0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP D15, D14, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL SP, SP, #58	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB SP, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W10, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 420748 <.omp_outlined.+0x758>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W11, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W4, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 420748 <.omp_outlined.+0x758>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X3, X2, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X5, [X6, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X15, X14, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR W11, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X1, X18, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X13, X12, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X17, X16, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X6, [X7, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W20, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #196]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X5, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X11, X10, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X24, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D8, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D9, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X20, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4630c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #896	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X25, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X3, X5, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X5, SP, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SUB W11, W9, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #216	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UMADDL X28, W11, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR X11, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W1, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X14, X2, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X3, X6, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, SP, #196	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #200	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X28, XZR, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X13, X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X8, X8, X28, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR X8, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LE 420164 <.omp_outlined.+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVN X8, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D1, X8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 420690 <.omp_outlined.+0x6a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X18, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FNEG D30, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVN X13, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X18, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 420190 <.omp_outlined.+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X28, X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X17, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D1, X13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 420478 <.omp_outlined.+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
DUP Z0.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z25.D, Z30.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
DUP Z17.D, Z8.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
DUP Z21.D, Z9.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
DUP Z24.D, Z10.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
STR Z0, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UDIV X12, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
LDR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X12, X12, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
INDEX Z1.D, X9, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
ADD X9, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.D, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
STR Z0, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LDR X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.D, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
STR Z0, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z3.D, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z18.D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z19.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z20.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z0.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z0, [X8, #508, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z0.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z0, [X8, #507, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
STR Z0, [X8, #506, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
STP D30, D10, [SP, #24]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D9, D8, [SP, #40]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z30.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z22.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z23.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR W8, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W14, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W8, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z26.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD W14, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X13, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z27.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADRP X14, 43e260 <.omp_outlined.+0x640>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, #2032	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z28.D}, P0/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADRP X14, <44126c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, #1016	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z29.D}, P0/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
ADRP X14, <441278>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, #1024	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z31.D}, P0/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LDP X15, X14, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMINNMV D1, P0, Z30.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2
LDP D9, D8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D30, D10, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
CBZ X11, 420690 <.omp_outlined.+0x6a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X16, <43e478>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X12, X28, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X14, X9, #32, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X16, #2032]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADRP X16, <441488>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X19, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X27, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X23, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X16, #1016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADRP X16, <44149c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X16, #1024]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X8, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X16, X30, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X11, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X13, X20, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X8, XZR, X17,LSL #32	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, WZR, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
LDR W19, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463694>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #920	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D1, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, SP, #184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X6, <4656ac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4636b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #944	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X5, <20041f6c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, #4048	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [X6, #3960]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4031e0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42071c <.omp_outlined.+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 420748 <.omp_outlined.+0x758>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D1, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADRP X2, <4656f4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4636fc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #944	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMINNM D0, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR X2, [X2, #3960]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 402fb0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 420748 <.omp_outlined.+0x758>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ORR X9, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL SP, SP, #6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD SP, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D15, D14, [SP], #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined.#0x41fff0–	6.46	3.49
○Loop 180 - calc_dt.cpp:50-75 - exec	6.46	3.49
○Loop 181 - calc_dt.cpp:49-49 - exec	0	0
○Loop 182 - calc_dt.cpp:50-75 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code