OV - exec - Function .omp

	Function: .omp_outlined..116	Module: exec	Source: update_halo.cpp:666-669	Coverage: 0.04%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 666 - 669

--------------------------------------------------------------------------------

666: #pragma omp parallel for simd

667:       for (int k = (y_min - depth + 1); k < (y_max + 1 + depth + 2); k++) {

668:         for (int j = 0; j < depth; ++j) {

669:           field.mass_flux_y(1 - j, k) = field.mass_flux_y(1 + 2 + j, k);

0x4329b0 SUB	SP, SP, #128

0x4329b4 STP	X29, X30, [SP, #32]

0x4329b8 STP	X28, X27, [SP, #48]

0x4329bc STP	X26, X25, [SP, #64]

0x4329c0 STP	X24, X23, [SP, #80]

0x4329c4 STP	X22, X21, [SP, #96]

0x4329c8 STP	X20, X19, [SP, #112]

0x4329cc ADD	X29, SP, #32

0x4329d0 LDR	W20, [X3]

0x4329d4 LDR	W8, [X4]

0x4329d8 LDR	W22, [X2]

0x4329dc ADD	W8, W20, W8

0x4329e0 SUB	W9, W22, W20

0x4329e4 ADD	W8, W8, #1

0x4329e8 SUBS	W24, W8, W9

0x4329ec B.LT	432a64

0x4329f0 LDR	W19, [X0]

0x4329f4 LDR	X23, [X5, #336]

0x4329f8 LDR	X21, [X5, #352]

0x4329fc MOVZ	W8, #1

0x432a00 ADRP	X0,

0x432a04 ADD	X0, X0, #2768

0x432a08 ADD	X3, SP, #16

0x432a0c SUB	X4, X29, #4

0x432a10 STP	W24, WZR, [X29, #504]

0x432a14 SUB	X5, X29, #8

0x432a18 SUB	X6, X29, #12

0x432a1c MOVZ	W2, #34

0x432a20 STUR	W8, [X29, #500]

0x432a24 STR	WZR, [SP, #16]

0x432a28 STR	W8, [SP]

0x432a2c MOVZ	W7, #1

0x432a30 ORR	W1, WZR, W19

0x432a34 BL	402dc0

0x432a38 LDP	W8, W9, [X29, #504]

0x432a3c CMP	W8, W24

0x432a40 CSEL	W8, W8, W24, #3

0x432a44 ADD	W10, W8, #1

0x432a48 CMP	W9, W10

0x432a4c CCMP	W20, #1, #8, #3

0x432a50 B.GE	432a84

(693) 0x432a54 ORR	W1, WZR, W19

(693) 0x432a58 ADRP	X0,

(693) 0x432a5c ADD	X0, X0, #2792

(693) 0x432a60 BL	403260

(693) 0x432a64 LDP	X20, X19, [SP, #112]

(693) 0x432a68 LDP	X22, X21, [SP, #96]

(693) 0x432a6c LDP	X24, X23, [SP, #80]

(693) 0x432a70 LDP	X26, X25, [SP, #64]

(693) 0x432a74 LDP	X28, X27, [SP, #48]

(693) 0x432a78 LDP	X29, X30, [SP, #32]

(693) 0x432a7c ADD	SP, SP, #128

(693) 0x432a80 RET

(693) 0x432a84 ADD	X15, X21, #24

(693) 0x432a88 UBFM	X16, X20, #61, #60

(693) 0x432a8c ADD	W14, W9, W22

(693) 0x432a90 ADD	X6, X21, #16

(693) 0x432a94 MOVZ	W18, #16

(693) 0x432a98 RDVL	X5, #1

(693) 0x432a9c SUB	X11, X20, #1

(693) 0x432aa0 ORR	W10, WZR, WZR

(693) 0x432aa4 RDVL	X2, #62

(693) 0x432aa8 PTRUE	P0.B, ALL

(693) 0x432aac ADD	X0, X15, X16

(693) 0x432ab0 ADD	X12, X21, #8

(693) 0x432ab4 UBFM	X13, X23, #61, #60

(693) 0x432ab8 SUB	X16, X21, X16

(693) 0x432abc SUB	X17, XZR, X11,LSL #3

(693) 0x432ac0 ADD	X3, X21, #48

(693) 0x432ac4 ADD	X1, X16, #16

(693) 0x432ac8 CNTW	X16, ALL

(693) 0x432acc SUB	W14, W14, W20

(693) 0x432ad0 ADD	W14, W14, #1

(693) 0x432ad4 CMP	X16, #16

(693) 0x432ad8 ADDVL	X4, X15, #1

(693) 0x432adc SUB	X5, X6, X5

(693) 0x432ae0 CSEL	X18, X16, X18, #8

(693) 0x432ae4 CMP	X15, X6

(693) 0x432ae8 ADDVL	X6, X6, #62

(693) 0x432aec CCMP	X1, X0, #2, #3

(693) 0x432af0 RDVL	X1, #2

(693) 0x432af4 ORR	W7, WZR, W14

(693) 0x432af8 CSINC	W0, WZR, WZR, #2

(693) 0x432afc B	432b14

(693) 0x432b00 CMP	W9, W8

(693) 0x432b04 ADD	W9, W9, #1

(693) 0x432b08 ADD	W10, W10, #1

(693) 0x432b0c ADD	W7, W7, #1

(693) 0x432b10 B.EQ	432a54

(693) 0x432b14 SBFM	X22, X7, #0, #31

(693) 0x432b18 CMP	X18, X20

(693) 0x432b1c MADD	X22, X13, X22, XZR

(693) 0x432b20 B.HI	432b44

(693) 0x432b24 ADD	W23, W14, W10

(693) 0x432b28 ANDS	XZR, X11, #4227

(693) 0x432b2c SBFM	X23, X23, #0, #31

(693) 0x432b30 MADD	X23, X13, X23, X12

(693) 0x432b34 ADD	X24, X23, X17

(693) 0x432b38 CCMP	X24, X23, #2, #0

(693) 0x432b3c CSINC	W23, W0, WZR, #9

(693) 0x432b40 TBZ	W23, #0, 432be0

(693) 0x432b44 ORR	X23, XZR, XZR

(693) 0x432b48 SUB	W24, W20, W23

(693) 0x432b4c ANDS	X25, X24, #4160

(693) 0x432b50 ORR	X24, XZR, X23

(693) 0x432b54 B.EQ	432b7c

(693) 0x432b58 SUB	X24, X22, X23,LSL #3

(693) 0x432b5c ADD	X26, X15, X22

(693) 0x432b60 ADD	X27, X12, X24

(693) 0x432b64 ORR	X24, XZR, X23

  (695) 0x432b68 LDR	D0, [X26, X24,LSL #3]

  (695) 0x432b6c ADD	X24, X24, #1

  (695) 0x432b70 SUBS	X25, X25, #1

  (695) 0x432b74 STR	D0, [X27], #504

  (695) 0x432b78 B.NE	432b68

(693) 0x432b7c ORN	X23, XZR, X23

(693) 0x432b80 ADD	X23, X23, X20

(693) 0x432b84 CMP	X23, #3

(693) 0x432b88 B.CC	432b00

(693) 0x432b8c UBFM	X25, X24, #61, #60

(693) 0x432b90 SUB	X24, X20, X24

(693) 0x432b94 ADD	X23, X22, X25

(693) 0x432b98 SUB	X22, X22, X25

(693) 0x432b9c ADD	X23, X3, X23

(693) 0x432ba0 ADD	X22, X21, X22

  (694) 0x432ba4 LDUR	D0, [X23, #488]

  (694) 0x432ba8 SUBS	X24, X24, #4

  (694) 0x432bac STR	D0, [X22, #8]

  (694) 0x432bb0 LDUR	D0, [X23, #496]

  (694) 0x432bb4 STR	D0, [X22]

  (694) 0x432bb8 LDUR	D0, [X23, #504]

  (694) 0x432bbc STUR	D0, [X22, #504]

  (694) 0x432bc0 LDR	D0, [X23], #32

  (694) 0x432bc4 STUR	D0, [X22, #496]

  (694) 0x432bc8 SUB	X22, X22, #32

  (694) 0x432bcc B.NE	432ba4

(693) 0x432bd0 B	432b00

0x432bd4 HINT	#0

0x432bd8 HINT	#0

0x432bdc HINT	#0

(693) 0x432be0 UDIV	X23, X20, X16

(693) 0x432be4 ORR	X26, XZR, X6

(693) 0x432be8 ORR	X27, XZR, X5

(693) 0x432bec ORR	X28, XZR, X4

(693) 0x432bf0 ORR	X30, XZR, X15

(693) 0x432bf4 UMSUBL	X24, W23, W16, X20

(693) 0x432bf8 UMADDL	X23, W23, W16, XZR

(693) 0x432bfc ORR	X25, XZR, X23

  (696) 0x432c00 LD1B	{Z0.B}, P0/Z, [X30, X22]

  (696) 0x432c04 LD1B	{Z1.B}, P0/Z, [X28, X22]

  (696) 0x432c08 ADD	X30, X30, X1

  (696) 0x432c0c ADD	X28, X28, X1

  (696) 0x432c10 SUBS	X25, X25, X16

  (696) 0x432c14 REV	Z0.D, Z0.D

  (696) 0x432c18 ST1B	{Z0.B}, P0, [X27, X22]

  (696) 0x432c1c REV	Z0.D, Z1.D

  (696) 0x432c20 ADD	X27, X27, X2

  (696) 0x432c24 ST1B	{Z0.B}, P0, [X26, X22]

  (696) 0x432c28 ADD	X26, X26, X2

  (696) 0x432c2c B.NE	432c00

(693) 0x432c30 CBNZ	X24, 432b48

0x432c34 B	432b00

0x432c38 HINT	#0

0x432c3c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:666-669
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:666-669.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.67 to 0.72 cycles (7.88x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	47
loop length	188
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.50	5.50	5.50	5.50	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.50	5.50	5.50	5.50	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.25
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4329b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 432a64 <.omp_outlined..116+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <464a00>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2768	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 432a84 <.omp_outlined..116+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 432b00 <.omp_outlined..116+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	update_halo.cpp:666-669
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:666-669.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	47
loop length	188
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.50	5.50	5.50	5.50	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.50	5.50	5.50	5.50	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.25
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4329b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 432a64 <.omp_outlined..116+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <464a00>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2768	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 432a84 <.omp_outlined..116+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 432b00 <.omp_outlined..116+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..116–	0.04	0.02
▼Loop 693 - update_halo.cpp:666-669 - exec–	0	0
○Loop 695 - update_halo.cpp:668-669 - exec	0.04	0.02
○Loop 696 - update_halo.cpp:668-669 - exec	0	0
○Loop 694 - update_halo.cpp:668-669 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code