OV - exec - Function .omp

	Function: .omp_outlined..112	Module: exec	Source: update_halo.cpp:646-649 [...]	Coverage: 0.01%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 646 - 649

--------------------------------------------------------------------------------

646: #pragma omp parallel for simd

647:       for (int j = (x_min - depth + 1); j < (x_max + depth + 2); j++) {

648:         for (int k = 0; k < depth; ++k) {

649:           field.mass_flux_y(j, 1 - k) = -field.mass_flux_y(j, 1 + 2 + k);

0x432690 SUB	SP, SP, #96

0x432694 STP	X29, X30, [SP, #16]

0x432698 STR	X25, [SP, #32]

0x43269c STP	X24, X23, [SP, #48]

0x4326a0 STP	X22, X21, [SP, #64]

0x4326a4 STP	X20, X19, [SP, #80]

0x4326a8 ADD	X29, SP, #16

0x4326ac LDR	W24, [X2]

0x4326b0 LDR	W20, [X3]

0x4326b4 LDR	W8, [X4]

0x4326b8 SUB	W21, W24, W20

0x4326bc ADD	W8, W8, W20

0x4326c0 SUBS	W25, W8, W21

0x4326c4 B.LT	43273c

0x4326c8 LDR	W19, [X0]

0x4326cc LDR	X22, [X5, #336]

0x4326d0 LDR	X23, [X5, #352]

0x4326d4 MOVZ	W8, #1

0x4326d8 ADRP	X0,

0x4326dc ADD	X0, X0, #2624

0x4326e0 ADD	X3, SP, #8

0x4326e4 ADD	X4, X29, #28

0x4326e8 STP	W25, WZR, [X29, #24]

0x4326ec ADD	X5, X29, #24

0x4326f0 SUB	X6, X29, #4

0x4326f4 MOVZ	W2, #34

0x4326f8 STUR	W8, [X29, #508]

0x4326fc STR	WZR, [SP, #8]

0x432700 STR	W8, [SP]

0x432704 MOVZ	W7, #1

0x432708 ORR	W1, WZR, W19

0x43270c BL	402dc0

0x432710 LDP	W8, W9, [X29, #24]

0x432714 CMP	W8, W25

0x432718 CSEL	W8, W8, W25, #3

0x43271c ADD	W10, W8, #1

0x432720 CMP	W9, W10

0x432724 CCMP	W20, #1, #8, #3

0x432728 B.GE	432758

(686) 0x43272c ORR	W1, WZR, W19

(686) 0x432730 ADRP	X0,

(686) 0x432734 ADD	X0, X0, #2648

(686) 0x432738 BL	403260

(686) 0x43273c LDP	X20, X19, [SP, #80]

(686) 0x432740 LDP	X22, X21, [SP, #64]

(686) 0x432744 LDP	X24, X23, [SP, #48]

(686) 0x432748 LDR	X25, [SP, #32]

(686) 0x43274c LDP	X29, X30, [SP, #16]

(686) 0x432750 ADD	SP, SP, #96

(686) 0x432754 RET

(686) 0x432758 ADD	W11, W9, W24

(686) 0x43275c UBFM	X12, X22, #60, #59

(686) 0x432760 ADD	X15, X22, X22,LSL #1

(686) 0x432764 AND	X10, X20, #6079

(686) 0x432768 UBFM	X14, X22, #59, #58

(686) 0x43276c SUB	X13, XZR, X12

(686) 0x432770 SUB	W11, W11, W20

(686) 0x432774 UBFM	X15, X15, #61, #60

(686) 0x432778 ADD	W11, W11, #1

(686) 0x43277c B	432790

(686) 0x432780 CMP	W9, W8

(686) 0x432784 ORR	W9, WZR, W17

(686) 0x432788 ADD	W11, W11, #1

(686) 0x43278c B.EQ	43272c

(686) 0x432790 CMP	W20, #1

(686) 0x432794 B.NE	4327a0

(686) 0x432798 ORR	X16, XZR, XZR

(686) 0x43279c B	4327d8

(686) 0x4327a0 ADD	X17, X23, W11,SXTW #3

(686) 0x4327a4 ORR	X16, XZR, XZR

(686) 0x4327a8 ORR	X18, XZR, X17

  (685) 0x4327ac LDR	D0, [X17, X15]

  (685) 0x4327b0 ADD	X16, X16, #2

  (685) 0x4327b4 CMP	X10, X16

  (685) 0x4327b8 FNEG	D0, D0

  (685) 0x4327bc STR	D0, [X18, X22,LSL #3]

  (685) 0x4327c0 LDR	D0, [X17, X14]

  (685) 0x4327c4 ADD	X17, X17, X12

  (685) 0x4327c8 FNEG	D0, D0

  (685) 0x4327cc STR	D0, [X18]

  (685) 0x4327d0 ADD	X18, X18, X13

  (685) 0x4327d4 B.NE	4327ac

(686) 0x4327d8 ADD	W17, W9, #1

(686) 0x4327dc TBZ	W20, #0, 432780

0x4327e0 ADD	W18, W17, W21

0x4327e4 ADD	X0, X16, #3

0x4327e8 MSUB	X16, X22, X16, X22

0x4327ec MADD	X0, X0, X22, XZR

0x4327f0 ADD	X18, X23, W18,SXTW #3

0x4327f4 LDR	D0, [X18, X0,LSL #3]

0x4327f8 FNEG	D0, D0

0x4327fc STR	D0, [X18, X16,LSL #3]

0x432800 B	432780

0x432804 HINT	#0

0x432808 HINT	#0

0x43280c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:646-649
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:646-649

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 1.17 cycles (5.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 15% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 6.50 to 0.85 cycles (7.61x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.50 to 0.50 cycles (13.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 48 bytes. The binary function is storing 100 bytes.

General properties

nb instructions	51
loop length	204
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	6.50	6.50	6.50	6.50	0.50	0.50	0.50	0.50	6.00	6.00	6.00	4.50	4.50
cycles	2.00	2.00	6.50	6.50	6.50	6.50	0.50	0.50	0.50	0.50	6.00	6.00	6.00	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Overall L1	6.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.50 cycles. At this rate:

7% of peak load performance is reached (7.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
32% of peak store performance is reached (15.38 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 432690

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W21, W24, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W25, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43273c <.omp_outlined..112+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4646d8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2624	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W25, WZR, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X5, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #508]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W25, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 432758 <.omp_outlined..112+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W18, W17, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X16, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB X16, X22, X16, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X0, X0, X22, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X18, X23, W18,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR D0, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FNEG D0, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D0, [X18, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 432780 <.omp_outlined..112+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	update_halo.cpp:646-649
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:646-649

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 1.17 cycles (5.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.50 to 0.50 cycles (13.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 48 bytes. The binary function is storing 100 bytes.

General properties

nb instructions	51
loop length	204
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	6.50	6.50	6.50	6.50	0.50	0.50	0.50	0.50	6.00	6.00	6.00	4.50	4.50
cycles	2.00	2.00	6.50	6.50	6.50	6.50	0.50	0.50	0.50	0.50	6.00	6.00	6.00	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Overall L1	6.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.50 cycles. At this rate:

7% of peak load performance is reached (7.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
32% of peak store performance is reached (15.38 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 432690

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W21, W24, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W25, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43273c <.omp_outlined..112+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4646d8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2624	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W25, WZR, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X5, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #508]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W25, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 432758 <.omp_outlined..112+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W18, W17, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X16, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB X16, X22, X16, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X0, X0, X22, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X18, X23, W18,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR D0, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FNEG D0, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D0, [X18, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 432780 <.omp_outlined..112+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..112–	0.01	0
▼Loop 686 - update_halo.cpp:646-649 - exec–	0	0
○Loop 685 - update_halo.cpp:648-649 - exec	0.01	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code