OV - exec - Function .omp

	Function: .omp_outlined..110	Module: exec	Source: update_halo.cpp:633-636	Coverage: 0.01%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 633 - 636

--------------------------------------------------------------------------------

633: #pragma omp parallel for simd

634:       for (int k = (y_min - depth + 1); k < (y_max + 1 + depth + 2); k++) {

635:         for (int j = 0; j < depth; ++j) {

636:           field.vol_flux_y(x_max + 2 + j, k) = field.vol_flux_y(x_max - j, k);

0x4323c0 SUB	SP, SP, #144

0x4323c4 STP	X29, X30, [SP, #48]

0x4323c8 STP	X28, X27, [SP, #64]

0x4323cc STP	X26, X25, [SP, #80]

0x4323d0 STP	X24, X23, [SP, #96]

0x4323d4 STP	X22, X21, [SP, #112]

0x4323d8 STP	X20, X19, [SP, #128]

0x4323dc ADD	X29, SP, #48

0x4323e0 LDR	W20, [X3]

0x4323e4 LDR	W8, [X4]

0x4323e8 LDR	W24, [X2]

0x4323ec ADD	W8, W20, W8

0x4323f0 SUB	W9, W24, W20

0x4323f4 ADD	W8, W8, #1

0x4323f8 SUBS	W25, W8, W9

0x4323fc B.LT	43266c

0x432400 LDR	W19, [X0]

0x432404 LDR	X21, [X5, #312]

0x432408 LDR	X23, [X5, #328]

0x43240c MOVZ	W8, #1

0x432410 ADRP	X0,

0x432414 ADD	X0, X0, #2552

0x432418 SUB	X3, X29, #16

0x43241c SUB	X4, X29, #4

0x432420 LDRSW	X22, [X6]

0x432424 SUB	X5, X29, #8

0x432428 SUB	X6, X29, #12

0x43242c MOVZ	W2, #34

0x432430 STP	W25, WZR, [X29, #504]

0x432434 STP	WZR, W8, [X29, #496]

0x432438 STR	W8, [SP]

0x43243c MOVZ	W7, #1

0x432440 ORR	W1, WZR, W19

0x432444 BL	402dc0

0x432448 LDP	W8, W9, [X29, #504]

0x43244c CMP	W8, W25

0x432450 CSEL	W8, W8, W25, #3

0x432454 ADD	W10, W8, #1

0x432458 CMP	W9, W10

0x43245c CCMP	W20, #1, #8, #3

0x432460 B.LT	43265c

0x432464 UBFM	X15, X22, #61, #60

0x432468 ADD	W12, W22, #2

0x43246c UBFM	X13, X20, #61, #60

0x432470 CNTW	X11, ALL

0x432474 STR	W19, [SP, #12]

0x432478 MOVZ	W18, #16

0x43247c ADD	W16, W9, W24

0x432480 ORR	W10, WZR, WZR

0x432484 RDVL	X2, #2

0x432488 ADD	X14, X15, #8

0x43248c SBFM	X12, X12, #61, #31

0x432490 ADD	X0, X23, X13

0x432494 ADD	X15, X23, X15

0x432498 SUB	X4, X23, #8

0x43249c PTRUE	P0.B, ALL

0x4324a0 SUB	X1, X14, X13

0x4324a4 CMP	X11, #16

0x4324a8 SUB	X13, X20, #1

0x4324ac ADD	X19, X23, X12

0x4324b0 ADD	X5, X23, X14

0x4324b4 UBFM	X14, X21, #61, #60

0x4324b8 CSEL	X18, X11, X18, #8

0x4324bc ADD	X12, X0, X12

0x4324c0 SUB	W17, W16, W20

0x4324c4 ADD	W17, W17, #1

0x4324c8 ADD	X3, X19, #16

0x4324cc ADD	X0, X23, X1

0x4324d0 CMP	X19, X5

0x4324d4 CCMP	X0, X12, #2, #3

0x4324d8 CSINC	W0, WZR, WZR, #2

0x4324dc RDVL	X12, #1

0x4324e0 SUB	X16, XZR, X13,LSL #3

0x4324e4 RDVL	X1, #62

0x4324e8 ADDVL	X7, X19, #1

0x4324ec ORR	W23, WZR, W17

0x4324f0 SUB	X12, X5, X12

0x4324f4 STR	X12, [SP, #24]

0x4324f8 ADDVL	X12, X5, #62

0x4324fc STR	X12, [SP, #16]

0x432500 B	432518

(679) 0x432504 CMP	W9, W8

(679) 0x432508 ADD	W9, W9, #1

(679) 0x43250c ADD	W10, W10, #1

(679) 0x432510 ADD	W23, W23, #1

(679) 0x432514 B.EQ	432658

(679) 0x432518 SBFM	X25, X23, #0, #31

(679) 0x43251c CMP	X18, X20

(679) 0x432520 MADD	X24, X14, X25, XZR

(679) 0x432524 B.HI	432548

(679) 0x432528 ADD	W12, W17, W10

(679) 0x43252c ANDS	XZR, X13, #4227

(679) 0x432530 SBFM	X12, X12, #0, #31

(679) 0x432534 MADD	X12, X14, X12, X15

(679) 0x432538 ADD	X5, X12, X16

(679) 0x43253c CCMP	X5, X12, #2, #0

(679) 0x432540 CSINC	W12, W0, WZR, #9

(679) 0x432544 TBZ	W12, #0, 432600

(679) 0x432548 ORR	X26, XZR, XZR

(679) 0x43254c SUB	W12, W20, W26

(679) 0x432550 ORR	X27, XZR, X26

(679) 0x432554 ANDS	X12, X12, #4160

(679) 0x432558 B.EQ	432580

(679) 0x43255c SUB	X6, X24, X26,LSL #3

(679) 0x432560 ADD	X5, X19, X24

(679) 0x432564 ORR	X27, XZR, X26

(679) 0x432568 ADD	X6, X15, X6

  (681) 0x43256c LDR	D0, [X6], #504

  (681) 0x432570 SUBS	X12, X12, #1

  (681) 0x432574 STR	D0, [X5, X27,LSL #3]

  (681) 0x432578 ADD	X27, X27, #1

  (681) 0x43257c B.NE	43256c

(679) 0x432580 ORN	X12, XZR, X26

(679) 0x432584 ADD	X12, X12, X20

(679) 0x432588 CMP	X12, #3

(679) 0x43258c B.CC	432504

0x432590 MADD	X12, X21, X25, X22

0x432594 UBFM	X6, X27, #61, #60

0x432598 SUB	X25, X20, X27

0x43259c UBFM	X5, X12, #61, #60

0x4325a0 ADD	X12, X24, X6

0x4325a4 SUB	X5, X5, X6

0x4325a8 ADD	X12, X3, X12

0x4325ac ADD	X5, X4, X5

0x4325b0 HINT	#0

0x4325b4 HINT	#0

0x4325b8 HINT	#0

0x4325bc HINT	#0

(680) 0x4325c0 LDR	D0, [X5, #8]

(680) 0x4325c4 SUB	X25, X25, #4

(680) 0x4325c8 STUR	D0, [X12, #496]

(680) 0x4325cc LDR	D0, [X5]

(680) 0x4325d0 STUR	D0, [X12, #504]

(680) 0x4325d4 LDUR	D0, [X5, #504]

(680) 0x4325d8 STR	D0, [X12]

(680) 0x4325dc LDUR	D0, [X5, #496]

(680) 0x4325e0 SUB	X5, X5, #32

(680) 0x4325e4 STR	D0, [X12, #8]

(680) 0x4325e8 ADD	X12, X12, #32

(680) 0x4325ec CBNZ	X25, 4325c0

0x4325f0 B	432504

0x4325f4 HINT	#0

0x4325f8 HINT	#0

0x4325fc HINT	#0

(679) 0x432600 UDIV	X12, X20, X11

(679) 0x432604 LDP	X6, X5, [SP, #16]

(679) 0x432608 ORR	X30, XZR, X7

(679) 0x43260c UMADDL	X26, W12, W11, XZR

(679) 0x432610 UMSUBL	X27, W12, W11, X20

(679) 0x432614 ORR	X12, XZR, X19

(679) 0x432618 ORR	X28, XZR, X26

(679) 0x43261c HINT	#0

  (682) 0x432620 LD1B	{Z0.B}, P0/Z, [X5, X24]

  (682) 0x432624 LD1B	{Z1.B}, P0/Z, [X6, X24]

  (682) 0x432628 ADD	X5, X5, X1

  (682) 0x43262c ADD	X6, X6, X1

  (682) 0x432630 SUBS	X28, X28, X11

  (682) 0x432634 REV	Z0.D, Z0.D

  (682) 0x432638 REV	Z1.D, Z1.D

  (682) 0x43263c ST1B	{Z0.B}, P0, [X12, X24]

  (682) 0x432640 ADD	X12, X12, X2

  (682) 0x432644 ST1B	{Z1.B}, P0, [X30, X24]

  (682) 0x432648 ADD	X30, X30, X2

  (682) 0x43264c B.NE	432620

(679) 0x432650 CBNZ	X27, 43254c

0x432654 B	432504

0x432658 LDR	W19, [SP, #12]

0x43265c ORR	W1, WZR, W19

0x432660 ADRP	X0,

0x432664 ADD	X0, X0, #2576

0x432668 BL	403260

0x43266c LDP	X20, X19, [SP, #128]

0x432670 LDP	X22, X21, [SP, #112]

0x432674 LDP	X24, X23, [SP, #96]

0x432678 LDP	X26, X25, [SP, #80]

0x43267c LDP	X28, X27, [SP, #64]

0x432680 LDP	X29, X30, [SP, #48]

0x432684 ADD	SP, SP, #144

0x432688 RET

0x43268c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:633-636
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:633-636.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.75 to 1.00 cycles (17.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 20% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 17.75 to 10.87 cycles (1.63x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 17.75 to 1.00 cycles (17.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 144 bytes. The binary function is storing 136 bytes.

General properties

nb instructions	112
loop length	448
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	17.75	17.75	17.75	17.75	0.00	0.00	0.00	0.00	9.00	9.00	9.00	6.00	6.00
cycles	4.00	4.00	17.75	17.75	17.75	17.75	0.00	0.00	0.00	0.00	9.00	9.00	9.00	6.00	6.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.00
Overall L1	17.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.75 cycles. At this rate:

8% of peak load performance is reached (8.11 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.66 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4323c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W24, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W24, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W25, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43266c <.omp_outlined..110+0x2ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <464410>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2552	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDRSW X22, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W25, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W25, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LT 43265c <.omp_outlined..110+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X15, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W22, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X13, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR W19, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W16, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W10, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RDVL X2, #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X14, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X12, X12, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X23, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X23, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X23, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X1, X14, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB X13, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X19, X23, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X23, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X14, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X18, X11, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W17, W16, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W17, W17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X19, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X23, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X19, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X0, X12, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W0, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RDVL X12, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X16, XZR, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RDVL X1, #62	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X7, X19, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR W23, WZR, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X5, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADDVL X12, X5, #62	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 432518 <.omp_outlined..110+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X12, X21, X25, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X6, X27, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X25, X20, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X5, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X24, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X5, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X3, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X4, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
B 432504 <.omp_outlined..110+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 432504 <.omp_outlined..110+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <464660>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2576	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	update_halo.cpp:633-636
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:633-636.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 17.75 to 1.00 cycles (17.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 144 bytes. The binary function is storing 136 bytes.

General properties

nb instructions	112
loop length	448
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	17.75	17.75	17.75	17.75	0.00	0.00	0.00	0.00	9.00	9.00	9.00	6.00	6.00
cycles	4.00	4.00	17.75	17.75	17.75	17.75	0.00	0.00	0.00	0.00	9.00	9.00	9.00	6.00	6.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.00
Overall L1	17.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.75 cycles. At this rate:

8% of peak load performance is reached (8.11 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.66 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4323c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W24, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W24, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W25, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43266c <.omp_outlined..110+0x2ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <464410>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2552	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDRSW X22, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W25, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W25, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LT 43265c <.omp_outlined..110+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X15, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W22, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X13, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR W19, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W16, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W10, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RDVL X2, #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X14, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X12, X12, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X23, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X23, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X23, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X1, X14, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB X13, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X19, X23, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X23, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X14, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X18, X11, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W17, W16, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W17, W17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X19, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X23, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X19, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X0, X12, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W0, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RDVL X12, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X16, XZR, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RDVL X1, #62	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X7, X19, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR W23, WZR, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X5, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADDVL X12, X5, #62	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 432518 <.omp_outlined..110+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X12, X21, X25, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X6, X27, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X25, X20, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X5, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X24, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X5, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X3, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X4, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
B 432504 <.omp_outlined..110+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 432504 <.omp_outlined..110+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <464660>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2576	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..110–	0.01	0
○Loop 680 - update_halo.cpp:635-636 - exec	0	0
▼Loop 679 - update_halo.cpp:634-636 - exec–	0	0
○Loop 681 - update_halo.cpp:635-636 - exec	0.01	0
○Loop 682 - update_halo.cpp:635-636 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code