OV - exec - Function .omp

	Function: .omp_outlined..108	Module: exec	Source: update_halo.cpp:623-626	Coverage: 0.02%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 623 - 626

--------------------------------------------------------------------------------

623: #pragma omp parallel for simd

624:       for (int k = (y_min - depth + 1); k < (y_max + 1 + depth + 2); k++) {

625:         for (int j = 0; j < depth; ++j) {

626:           field.vol_flux_y(1 - j, k) = field.vol_flux_y(1 + 2 + j, k);

0x432130 SUB	SP, SP, #128

0x432134 STP	X29, X30, [SP, #32]

0x432138 STP	X28, X27, [SP, #48]

0x43213c STP	X26, X25, [SP, #64]

0x432140 STP	X24, X23, [SP, #80]

0x432144 STP	X22, X21, [SP, #96]

0x432148 STP	X20, X19, [SP, #112]

0x43214c ADD	X29, SP, #32

0x432150 LDR	W20, [X3]

0x432154 LDR	W8, [X4]

0x432158 LDR	W22, [X2]

0x43215c ADD	W8, W20, W8

0x432160 SUB	W9, W22, W20

0x432164 ADD	W8, W8, #1

0x432168 SUBS	W24, W8, W9

0x43216c B.LT	4321e4

0x432170 LDR	W19, [X0]

0x432174 LDR	X23, [X5, #312]

0x432178 LDR	X21, [X5, #328]

0x43217c MOVZ	W8, #1

0x432180 ADRP	X0,

0x432184 ADD	X0, X0, #2480

0x432188 ADD	X3, SP, #16

0x43218c SUB	X4, X29, #4

0x432190 STP	W24, WZR, [X29, #504]

0x432194 SUB	X5, X29, #8

0x432198 SUB	X6, X29, #12

0x43219c MOVZ	W2, #34

0x4321a0 STUR	W8, [X29, #500]

0x4321a4 STR	WZR, [SP, #16]

0x4321a8 STR	W8, [SP]

0x4321ac MOVZ	W7, #1

0x4321b0 ORR	W1, WZR, W19

0x4321b4 BL	402dc0

0x4321b8 LDP	W8, W9, [X29, #504]

0x4321bc CMP	W8, W24

0x4321c0 CSEL	W8, W8, W24, #3

0x4321c4 ADD	W10, W8, #1

0x4321c8 CMP	W9, W10

0x4321cc CCMP	W20, #1, #8, #3

0x4321d0 B.GE	432204

(673) 0x4321d4 ORR	W1, WZR, W19

(673) 0x4321d8 ADRP	X0,

(673) 0x4321dc ADD	X0, X0, #2504

(673) 0x4321e0 BL	403260

(673) 0x4321e4 LDP	X20, X19, [SP, #112]

(673) 0x4321e8 LDP	X22, X21, [SP, #96]

(673) 0x4321ec LDP	X24, X23, [SP, #80]

(673) 0x4321f0 LDP	X26, X25, [SP, #64]

(673) 0x4321f4 LDP	X28, X27, [SP, #48]

(673) 0x4321f8 LDP	X29, X30, [SP, #32]

(673) 0x4321fc ADD	SP, SP, #128

(673) 0x432200 RET

(673) 0x432204 ADD	X15, X21, #24

(673) 0x432208 UBFM	X16, X20, #61, #60

(673) 0x43220c ADD	W14, W9, W22

(673) 0x432210 ADD	X6, X21, #16

(673) 0x432214 MOVZ	W18, #16

(673) 0x432218 RDVL	X5, #1

(673) 0x43221c SUB	X11, X20, #1

(673) 0x432220 ORR	W10, WZR, WZR

(673) 0x432224 RDVL	X2, #62

(673) 0x432228 PTRUE	P0.B, ALL

(673) 0x43222c ADD	X0, X15, X16

(673) 0x432230 ADD	X12, X21, #8

(673) 0x432234 UBFM	X13, X23, #61, #60

(673) 0x432238 SUB	X16, X21, X16

(673) 0x43223c SUB	X17, XZR, X11,LSL #3

(673) 0x432240 ADD	X3, X21, #48

(673) 0x432244 ADD	X1, X16, #16

(673) 0x432248 CNTW	X16, ALL

(673) 0x43224c SUB	W14, W14, W20

(673) 0x432250 ADD	W14, W14, #1

(673) 0x432254 CMP	X16, #16

(673) 0x432258 ADDVL	X4, X15, #1

(673) 0x43225c SUB	X5, X6, X5

(673) 0x432260 CSEL	X18, X16, X18, #8

(673) 0x432264 CMP	X15, X6

(673) 0x432268 ADDVL	X6, X6, #62

(673) 0x43226c CCMP	X1, X0, #2, #3

(673) 0x432270 RDVL	X1, #2

(673) 0x432274 ORR	W7, WZR, W14

(673) 0x432278 CSINC	W0, WZR, WZR, #2

(673) 0x43227c B	432294

(673) 0x432280 CMP	W9, W8

(673) 0x432284 ADD	W9, W9, #1

(673) 0x432288 ADD	W10, W10, #1

(673) 0x43228c ADD	W7, W7, #1

(673) 0x432290 B.EQ	4321d4

(673) 0x432294 SBFM	X22, X7, #0, #31

(673) 0x432298 CMP	X18, X20

(673) 0x43229c MADD	X22, X13, X22, XZR

(673) 0x4322a0 B.HI	4322c4

(673) 0x4322a4 ADD	W23, W14, W10

(673) 0x4322a8 ANDS	XZR, X11, #4227

(673) 0x4322ac SBFM	X23, X23, #0, #31

(673) 0x4322b0 MADD	X23, X13, X23, X12

(673) 0x4322b4 ADD	X24, X23, X17

(673) 0x4322b8 CCMP	X24, X23, #2, #0

(673) 0x4322bc CSINC	W23, W0, WZR, #9

(673) 0x4322c0 TBZ	W23, #0, 432360

(673) 0x4322c4 ORR	X23, XZR, XZR

(673) 0x4322c8 SUB	W24, W20, W23

(673) 0x4322cc ANDS	X25, X24, #4160

(673) 0x4322d0 ORR	X24, XZR, X23

(673) 0x4322d4 B.EQ	4322fc

(673) 0x4322d8 SUB	X24, X22, X23,LSL #3

(673) 0x4322dc ADD	X26, X15, X22

(673) 0x4322e0 ADD	X27, X12, X24

(673) 0x4322e4 ORR	X24, XZR, X23

  (675) 0x4322e8 LDR	D0, [X26, X24,LSL #3]

  (675) 0x4322ec ADD	X24, X24, #1

  (675) 0x4322f0 SUBS	X25, X25, #1

  (675) 0x4322f4 STR	D0, [X27], #504

  (675) 0x4322f8 B.NE	4322e8

(673) 0x4322fc ORN	X23, XZR, X23

(673) 0x432300 ADD	X23, X23, X20

(673) 0x432304 CMP	X23, #3

(673) 0x432308 B.CC	432280

(673) 0x43230c UBFM	X25, X24, #61, #60

(673) 0x432310 SUB	X24, X20, X24

(673) 0x432314 ADD	X23, X22, X25

(673) 0x432318 SUB	X22, X22, X25

(673) 0x43231c ADD	X23, X3, X23

(673) 0x432320 ADD	X22, X21, X22

  (674) 0x432324 LDUR	D0, [X23, #488]

  (674) 0x432328 SUBS	X24, X24, #4

  (674) 0x43232c STR	D0, [X22, #8]

  (674) 0x432330 LDUR	D0, [X23, #496]

  (674) 0x432334 STR	D0, [X22]

  (674) 0x432338 LDUR	D0, [X23, #504]

  (674) 0x43233c STUR	D0, [X22, #504]

  (674) 0x432340 LDR	D0, [X23], #32

  (674) 0x432344 STUR	D0, [X22, #496]

  (674) 0x432348 SUB	X22, X22, #32

  (674) 0x43234c B.NE	432324

(673) 0x432350 B	432280

0x432354 HINT	#0

0x432358 HINT	#0

0x43235c HINT	#0

(673) 0x432360 UDIV	X23, X20, X16

(673) 0x432364 ORR	X26, XZR, X6

(673) 0x432368 ORR	X27, XZR, X5

(673) 0x43236c ORR	X28, XZR, X4

(673) 0x432370 ORR	X30, XZR, X15

(673) 0x432374 UMSUBL	X24, W23, W16, X20

(673) 0x432378 UMADDL	X23, W23, W16, XZR

(673) 0x43237c ORR	X25, XZR, X23

  (676) 0x432380 LD1B	{Z0.B}, P0/Z, [X30, X22]

  (676) 0x432384 LD1B	{Z1.B}, P0/Z, [X28, X22]

  (676) 0x432388 ADD	X30, X30, X1

  (676) 0x43238c ADD	X28, X28, X1

  (676) 0x432390 SUBS	X25, X25, X16

  (676) 0x432394 REV	Z0.D, Z0.D

  (676) 0x432398 ST1B	{Z0.B}, P0, [X27, X22]

  (676) 0x43239c REV	Z0.D, Z1.D

  (676) 0x4323a0 ADD	X27, X27, X2

  (676) 0x4323a4 ST1B	{Z0.B}, P0, [X26, X22]

  (676) 0x4323a8 ADD	X26, X26, X2

  (676) 0x4323ac B.NE	432380

(673) 0x4323b0 CBNZ	X24, 4322c8

0x4323b4 B	432280

0x4323b8 HINT	#0

0x4323bc HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:623-626
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:623-626.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.67 to 0.72 cycles (7.88x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	47
loop length	188
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.50	5.50	5.50	5.50	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.50	5.50	5.50	5.50	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.25
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 432130

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4321e4 <.omp_outlined..108+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <464180>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2480	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 432204 <.omp_outlined..108+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 432280 <.omp_outlined..108+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	update_halo.cpp:623-626
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:623-626.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	47
loop length	188
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.50	5.50	5.50	5.50	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.50	5.50	5.50	5.50	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.25
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 432130

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4321e4 <.omp_outlined..108+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <464180>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2480	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 432204 <.omp_outlined..108+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 432280 <.omp_outlined..108+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..108–	0.02	0.01
▼Loop 673 - update_halo.cpp:623-626 - exec–	0	0
○Loop 675 - update_halo.cpp:625-626 - exec	0.02	0.01
○Loop 674 - update_halo.cpp:625-626 - exec	0	0
○Loop 676 - update_halo.cpp:625-626 - exec	0	0

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ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code