OV - exec - Function .omp

	Function: .omp_outlined..100	Module: exec	Source: update_halo.cpp:580-583	Coverage: 0.02%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 580 - 583

--------------------------------------------------------------------------------

580: #pragma omp parallel for simd

581:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

582:         for (int j = 0; j < depth; ++j) {

583:           field.mass_flux_x(1 - j, k) = -field.mass_flux_x(1 + 2 + j, k);

0x431840 SUB	SP, SP, #128

0x431844 STP	X29, X30, [SP, #32]

0x431848 STP	X28, X27, [SP, #48]

0x43184c STP	X26, X25, [SP, #64]

0x431850 STP	X24, X23, [SP, #80]

0x431854 STP	X22, X21, [SP, #96]

0x431858 STP	X20, X19, [SP, #112]

0x43185c ADD	X29, SP, #32

0x431860 LDR	W22, [X2]

0x431864 LDR	W20, [X3]

0x431868 LDR	W8, [X4]

0x43186c SUB	W9, W22, W20

0x431870 ADD	W8, W8, W20

0x431874 SUBS	W24, W8, W9

0x431878 B.LT	4318f0

0x43187c LDR	W19, [X0]

0x431880 LDR	X23, [X5, #288]

0x431884 LDR	X21, [X5, #304]

0x431888 MOVZ	W8, #1

0x43188c ADRP	X0,

0x431890 ADD	X0, X0, #2192

0x431894 ADD	X3, SP, #16

0x431898 SUB	X4, X29, #4

0x43189c STP	W24, WZR, [X29, #504]

0x4318a0 SUB	X5, X29, #8

0x4318a4 SUB	X6, X29, #12

0x4318a8 MOVZ	W2, #34

0x4318ac STUR	W8, [X29, #500]

0x4318b0 STR	WZR, [SP, #16]

0x4318b4 STR	W8, [SP]

0x4318b8 MOVZ	W7, #1

0x4318bc ORR	W1, WZR, W19

0x4318c0 BL	402dc0

0x4318c4 LDP	W8, W9, [X29, #504]

0x4318c8 CMP	W8, W24

0x4318cc CSEL	W8, W8, W24, #3

0x4318d0 ADD	W10, W8, #1

0x4318d4 CMP	W9, W10

0x4318d8 CCMP	W20, #1, #8, #3

0x4318dc B.GE	431910

(653) 0x4318e0 ORR	W1, WZR, W19

(653) 0x4318e4 ADRP	X0,

(653) 0x4318e8 ADD	X0, X0, #2216

(653) 0x4318ec BL	403260

(653) 0x4318f0 LDP	X20, X19, [SP, #112]

(653) 0x4318f4 LDP	X22, X21, [SP, #96]

(653) 0x4318f8 LDP	X24, X23, [SP, #80]

(653) 0x4318fc LDP	X26, X25, [SP, #64]

(653) 0x431900 LDP	X28, X27, [SP, #48]

(653) 0x431904 LDP	X29, X30, [SP, #32]

(653) 0x431908 ADD	SP, SP, #128

(653) 0x43190c RET

(653) 0x431910 ADD	X15, X21, #24

(653) 0x431914 UBFM	X16, X20, #61, #60

(653) 0x431918 ADD	W14, W9, W22

(653) 0x43191c ADD	X6, X21, #16

(653) 0x431920 MOVZ	W0, #12

(653) 0x431924 RDVL	X5, #1

(653) 0x431928 SUB	X11, X20, #1

(653) 0x43192c ORR	W10, WZR, WZR

(653) 0x431930 RDVL	X18, #2

(653) 0x431934 RDVL	X1, #62

(653) 0x431938 ADD	X2, X15, X16

(653) 0x43193c ADD	X12, X21, #8

(653) 0x431940 UBFM	X13, X23, #61, #60

(653) 0x431944 SUB	X16, X21, X16

(653) 0x431948 SUB	X17, XZR, X11,LSL #3

(653) 0x43194c ADD	X3, X16, #16

(653) 0x431950 CNTW	X16, ALL

(653) 0x431954 CMP	X16, #12

(653) 0x431958 SUB	W14, W14, W20

(653) 0x43195c ADD	W14, W14, #1

(653) 0x431960 ADDVL	X4, X15, #1

(653) 0x431964 SUB	X5, X6, X5

(653) 0x431968 CSEL	X0, X16, X0, #8

(653) 0x43196c CMP	X15, X6

(653) 0x431970 ADDVL	X6, X6, #62

(653) 0x431974 CCMP	X3, X2, #2, #3

(653) 0x431978 PTRUE	P0.B, ALL

(653) 0x43197c PTRUE	P1.D, ALL

(653) 0x431980 ADD	X3, X21, #48

(653) 0x431984 CSINC	W2, WZR, WZR, #2

(653) 0x431988 ORR	W7, WZR, W14

(653) 0x43198c B	4319b4

0x431990 HINT	#0

0x431994 HINT	#0

0x431998 HINT	#0

0x43199c HINT	#0

(653) 0x4319a0 CMP	W9, W8

(653) 0x4319a4 ADD	W9, W9, #1

(653) 0x4319a8 ADD	W10, W10, #1

(653) 0x4319ac ADD	W7, W7, #1

(653) 0x4319b0 B.EQ	4318e0

(653) 0x4319b4 SBFM	X22, X7, #0, #31

(653) 0x4319b8 CMP	X0, X20

(653) 0x4319bc MADD	X22, X13, X22, XZR

(653) 0x4319c0 B.HI	4319e4

(653) 0x4319c4 ADD	W23, W14, W10

(653) 0x4319c8 ANDS	XZR, X11, #4227

(653) 0x4319cc SBFM	X23, X23, #0, #31

(653) 0x4319d0 MADD	X23, X13, X23, X12

(653) 0x4319d4 ADD	X24, X23, X17

(653) 0x4319d8 CCMP	X24, X23, #2, #0

(653) 0x4319dc CSINC	W23, W2, WZR, #9

(653) 0x4319e0 TBZ	W23, #0, 431a88

(653) 0x4319e4 ORR	X23, XZR, XZR

(653) 0x4319e8 SUB	W24, W20, W23

(653) 0x4319ec ANDS	X25, X24, #4160

(653) 0x4319f0 ORR	X24, XZR, X23

(653) 0x4319f4 B.EQ	431a20

(653) 0x4319f8 SUB	X24, X22, X23,LSL #3

(653) 0x4319fc ADD	X26, X15, X22

(653) 0x431a00 ADD	X27, X12, X24

(653) 0x431a04 ORR	X24, XZR, X23

  (655) 0x431a08 LDR	D0, [X26, X24,LSL #3]

  (655) 0x431a0c ADD	X24, X24, #1

  (655) 0x431a10 SUBS	X25, X25, #1

  (655) 0x431a14 FNEG	D0, D0

  (655) 0x431a18 STR	D0, [X27], #504

  (655) 0x431a1c B.NE	431a08

(653) 0x431a20 ORN	X23, XZR, X23

(653) 0x431a24 ADD	X23, X23, X20

(653) 0x431a28 CMP	X23, #3

(653) 0x431a2c B.CC	4319a0

(653) 0x431a30 UBFM	X25, X24, #61, #60

(653) 0x431a34 SUB	X24, X20, X24

(653) 0x431a38 ADD	X23, X22, X25

(653) 0x431a3c SUB	X22, X22, X25

(653) 0x431a40 ADD	X23, X3, X23

(653) 0x431a44 ADD	X22, X21, X22

  (654) 0x431a48 LDUR	D0, [X23, #488]

  (654) 0x431a4c SUBS	X24, X24, #4

  (654) 0x431a50 FNEG	D0, D0

  (654) 0x431a54 STR	D0, [X22, #8]

  (654) 0x431a58 LDUR	D0, [X23, #496]

  (654) 0x431a5c FNEG	D0, D0

  (654) 0x431a60 STR	D0, [X22]

  (654) 0x431a64 LDUR	D0, [X23, #504]

  (654) 0x431a68 FNEG	D0, D0

  (654) 0x431a6c STUR	D0, [X22, #504]

  (654) 0x431a70 LDR	D0, [X23], #32

  (654) 0x431a74 FNEG	D0, D0

  (654) 0x431a78 STUR	D0, [X22, #496]

  (654) 0x431a7c SUB	X22, X22, #32

  (654) 0x431a80 B.NE	431a48

(653) 0x431a84 B	4319a0

(653) 0x431a88 UDIV	X23, X20, X16

(653) 0x431a8c ORR	X26, XZR, X6

(653) 0x431a90 ORR	X27, XZR, X5

(653) 0x431a94 ORR	X28, XZR, X4

(653) 0x431a98 ORR	X30, XZR, X15

(653) 0x431a9c UMSUBL	X24, W23, W16, X20

(653) 0x431aa0 UMADDL	X23, W23, W16, XZR

(653) 0x431aa4 ORR	X25, XZR, X23

  (656) 0x431aa8 LD1B	{Z0.B}, P0/Z, [X30, X22]

  (656) 0x431aac LD1B	{Z1.B}, P0/Z, [X28, X22]

  (656) 0x431ab0 ADD	X30, X30, X18

  (656) 0x431ab4 ADD	X28, X28, X18

  (656) 0x431ab8 SUBS	X25, X25, X16

  (656) 0x431abc FNEG	Z0.D, P1/M, Z0.D

  (656) 0x431ac0 FNEG	Z1.D, P1/M, Z1.D

  (656) 0x431ac4 REV	Z0.D, Z0.D

  (656) 0x431ac8 ST1B	{Z0.B}, P0, [X27, X22]

  (656) 0x431acc REV	Z0.D, Z1.D

  (656) 0x431ad0 ADD	X27, X27, X1

  (656) 0x431ad4 ST1B	{Z0.B}, P0, [X26, X22]

  (656) 0x431ad8 ADD	X26, X26, X1

  (656) 0x431adc B.NE	431aa8

(653) 0x431ae0 CBNZ	X24, 4319e8

0x431ae4 B	4319a0

0x431ae8 HINT	#0

0x431aec HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:580-583
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:580-583.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.67 to 0.71 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	47
loop length	188
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 431840

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4318f0 <.omp_outlined..100+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <46488c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 431910 <.omp_outlined..100+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
B 4319a0 <.omp_outlined..100+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	update_halo.cpp:580-583
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:580-583.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	47
loop length	188
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 431840

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4318f0 <.omp_outlined..100+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <46488c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 431910 <.omp_outlined..100+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
B 4319a0 <.omp_outlined..100+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..100–	0.02	0.01
▼Loop 653 - update_halo.cpp:580-583 - exec–	0.02	0.01
○Loop 655 - update_halo.cpp:582-583 - exec	0	0
○Loop 656 - update_halo.cpp:582-583 - exec	0	0
○Loop 654 - update_halo.cpp:582-583 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code