OV - exec - Function .omp

	Function: .omp_outlined..94	Module: exec	Source: update_halo.cpp:547-550 [...]	Coverage: 0.01%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 547 - 550

--------------------------------------------------------------------------------

547: #pragma omp parallel for simd

548:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

549:         for (int j = 0; j < depth; ++j) {

550:           field.vol_flux_x(x_max + j + 1 + 2, k) = -field.vol_flux_x(x_max + 1 - j, k);

0x4310d0 SUB	SP, SP, #128

0x4310d4 STP	X29, X30, [SP, #32]

0x4310d8 STP	X28, X27, [SP, #48]

0x4310dc STP	X26, X25, [SP, #64]

0x4310e0 STP	X24, X23, [SP, #80]

0x4310e4 STP	X22, X21, [SP, #96]

0x4310e8 STP	X20, X19, [SP, #112]

0x4310ec ADD	X29, SP, #32

0x4310f0 LDR	W25, [X2]

0x4310f4 LDR	W20, [X3]

0x4310f8 LDR	W8, [X4]

0x4310fc SUB	W21, W25, W20

0x431100 ADD	W8, W8, W20

0x431104 SUBS	W26, W8, W21

0x431108 B.LT	431184

0x43110c LDR	W19, [X0]

0x431110 LDR	X22, [X5, #264]

0x431114 LDR	X23, [X5, #280]

0x431118 MOVZ	W8, #1

0x43111c ADRP	X0,

0x431120 ADD	X0, X0, #1976

0x431124 ADD	X3, SP, #16

0x431128 SUB	X4, X29, #4

0x43112c LDR	W24, [X6]

0x431130 SUB	X5, X29, #8

0x431134 SUB	X6, X29, #12

0x431138 MOVZ	W2, #34

0x43113c STP	W26, WZR, [X29, #504]

0x431140 STUR	W8, [X29, #500]

0x431144 STR	WZR, [SP, #16]

0x431148 MOVZ	W7, #1

0x43114c ORR	W1, WZR, W19

0x431150 STR	W8, [SP]

0x431154 BL	402dc0

0x431158 LDP	W8, W9, [X29, #504]

0x43115c CMP	W8, W26

0x431160 CSEL	W8, W8, W26, #3

0x431164 ADD	W10, W8, #1

0x431168 CMP	W9, W10

0x43116c CCMP	W20, #1, #8, #3

0x431170 B.GE	4311a4

(637) 0x431174 ORR	W1, WZR, W19

(637) 0x431178 ADRP	X0,

(637) 0x43117c ADD	X0, X0, #2000

(637) 0x431180 BL	403260

(637) 0x431184 LDP	X20, X19, [SP, #112]

(637) 0x431188 LDP	X22, X21, [SP, #96]

(637) 0x43118c LDP	X24, X23, [SP, #80]

(637) 0x431190 LDP	X26, X25, [SP, #64]

(637) 0x431194 LDP	X28, X27, [SP, #48]

(637) 0x431198 LDP	X29, X30, [SP, #32]

(637) 0x43119c ADD	SP, SP, #128

(637) 0x4311a0 RET

(637) 0x4311a4 ADD	W11, W24, #1

(637) 0x4311a8 UBFM	X0, X20, #61, #60

(637) 0x4311ac ADD	W12, W24, #3

(637) 0x4311b0 SUB	X18, X20, #1

(637) 0x4311b4 ADD	W15, W9, W25

(637) 0x4311b8 ORR	W10, WZR, WZR

(637) 0x4311bc PTRUE	P0.D, ALL

(637) 0x4311c0 UBFM	X14, X22, #61, #60

(637) 0x4311c4 SBFM	X16, X11, #61, #31

(637) 0x4311c8 ADD	X2, X23, X0

(637) 0x4311cc SBFM	X17, X12, #61, #31

(637) 0x4311d0 SUB	W5, W11, W18

(637) 0x4311d4 ADD	X13, X23, X16

(637) 0x4311d8 STR	X13, [SP, #8]

(637) 0x4311dc ADD	X16, X16, #8

(637) 0x4311e0 ADD	X1, X23, X17

(637) 0x4311e4 ADD	X2, X2, X17

(637) 0x4311e8 SUB	X17, X16, X0

(637) 0x4311ec ADD	X4, X23, X16

(637) 0x4311f0 CNTW	X16, ALL

(637) 0x4311f4 CMP	X16, #24

(637) 0x4311f8 ADD	X3, X23, X17

(637) 0x4311fc MOVZ	W17, #24

(637) 0x431200 CSEL	X17, X16, X17, #8

(637) 0x431204 ADD	W0, W12, W18

(637) 0x431208 ANDS	XZR, X18, #6112

(637) 0x43120c SUB	W15, W15, W20

(637) 0x431210 ADD	W15, W15, #1

(637) 0x431214 CCMP	W5, W11, #0, #0

(637) 0x431218 SUB	X18, XZR, X18,LSL #3

(637) 0x43121c CCMP	W0, W12, #8, #13

(637) 0x431220 CSINC	W0, WZR, WZR, #10

(637) 0x431224 CMP	X1, X4

(637) 0x431228 MOVZ	W4, #1

(637) 0x43122c CCMP	X3, X2, #2, #3

(637) 0x431230 CNTD	X3, ALL

(637) 0x431234 CSINC	W1, WZR, WZR, #2

(637) 0x431238 SUB	X4, X4, X3

(637) 0x43123c B	431250

(637) 0x431240 CMP	W9, W8

(637) 0x431244 ORR	W9, WZR, W5

(637) 0x431248 ADD	W10, W10, #1

(637) 0x43124c B.EQ	431174

(637) 0x431250 ADD	W5, W9, #1

(637) 0x431254 CMP	X17, X20

(637) 0x431258 ADD	W6, W5, W21

(637) 0x43125c SBFM	X6, X6, #0, #31

(637) 0x431260 MADD	X6, X22, X6, XZR

(637) 0x431264 ADD	X6, X23, X6,LSL #3

(637) 0x431268 B.HI	431290

(637) 0x43126c LDR	X13, [SP, #8]

(637) 0x431270 ADD	W7, W15, W10

(637) 0x431274 SBFM	X7, X7, #0, #31

(637) 0x431278 MADD	X7, X14, X7, X13

(637) 0x43127c ADD	X25, X7, X18

(637) 0x431280 CMP	X25, X7

(637) 0x431284 CSINC	W7, W0, WZR, #9

(637) 0x431288 ORR	W7, W7, W1

(637) 0x43128c TBZ	W7, #0, 431380

(637) 0x431290 ORR	X25, XZR, XZR

(637) 0x431294 SUB	W7, W20, W25

(637) 0x431298 ANDS	X26, X7, #4160

(637) 0x43129c ORR	X7, XZR, X25

(637) 0x4312a0 B.EQ	4312cc

(637) 0x4312a4 SUB	W27, W11, W25

(637) 0x4312a8 ORR	X7, XZR, X25

  (639) 0x4312ac LDR	D0, [X6, X27,SXTW #3]

  (639) 0x4312b0 ADD	W28, W12, W7

  (639) 0x4312b4 ADD	X7, X7, #1

  (639) 0x4312b8 SUB	W27, W27, #1

  (639) 0x4312bc SUBS	X26, X26, #1

  (639) 0x4312c0 FNEG	D0, D0

  (639) 0x4312c4 STR	D0, [X6, X28,SXTW #3]

  (639) 0x4312c8 B.NE	4312ac

(637) 0x4312cc ORN	X25, XZR, X25

(637) 0x4312d0 ADD	X25, X25, X20

(637) 0x4312d4 CMP	X25, #3

(637) 0x4312d8 B.CC	431240

(637) 0x4312dc MOVN	W2, #1

(637) 0x4312e0 ORR	W13, WZR, W19

(637) 0x4312e4 ORN	W26, WZR, W7

(637) 0x4312e8 SUB	W27, WZR, W7

(637) 0x4312ec SUB	X28, X20, X7

(637) 0x4312f0 SUB	W25, W2, W7

(637) 0x4312f4 HINT	#0

(637) 0x4312f8 HINT	#0

(637) 0x4312fc HINT	#0

  (638) 0x431300 ADD	W30, W24, W27

  (638) 0x431304 SUB	W27, W27, #4

  (638) 0x431308 SUBS	X28, X28, #4

  (638) 0x43130c ADD	W19, W30, #1

  (638) 0x431310 LDR	D0, [X6, X19,SXTW #3]

  (638) 0x431314 ADD	W19, W24, W7

  (638) 0x431318 ADD	W7, W7, #4

  (638) 0x43131c ADD	W2, W19, #3

  (638) 0x431320 FNEG	D0, D0

  (638) 0x431324 STR	D0, [X6, X2,SXTW #3]

  (638) 0x431328 ADD	W2, W19, #4

  (638) 0x43132c LDR	D0, [X6, X30,SXTW #3]

  (638) 0x431330 ADD	W30, W24, W25

  (638) 0x431334 SUB	W25, W25, #4

  (638) 0x431338 FNEG	D0, D0

  (638) 0x43133c STR	D0, [X6, X2,SXTW #3]

  (638) 0x431340 ADD	W2, W24, W26

  (638) 0x431344 SUB	W26, W26, #4

  (638) 0x431348 LDR	D0, [X6, X2,SXTW #3]

  (638) 0x43134c ADD	W2, W19, #5

  (638) 0x431350 FNEG	D0, D0

  (638) 0x431354 STR	D0, [X6, X2,SXTW #3]

  (638) 0x431358 ADD	W2, W19, #6

  (638) 0x43135c LDR	D0, [X6, X30,SXTW #3]

  (638) 0x431360 FNEG	D0, D0

  (638) 0x431364 STR	D0, [X6, X2,SXTW #3]

  (638) 0x431368 B.NE	431300

(637) 0x43136c ORR	W19, WZR, W13

(637) 0x431370 B	431240

0x431374 HINT	#0

0x431378 HINT	#0

0x43137c HINT	#0

(637) 0x431380 UDIV	X25, X20, X16

(637) 0x431384 ORR	X7, XZR, XZR

(637) 0x431388 SUB	X27, XZR, X3

(637) 0x43138c ORR	W28, WZR, W11

(637) 0x431390 UMSUBL	X26, W25, W16, X20

(637) 0x431394 UMADDL	X25, W25, W16, XZR

(637) 0x431398 HINT	#0

(637) 0x43139c HINT	#0

  (640) 0x4313a0 ADD	X30, X6, W28,SXTW #3

  (640) 0x4313a4 SUB	W28, W28, W16

  (640) 0x4313a8 ADD	X30, X30, X4,LSL #3

  (640) 0x4313ac LD1D	{Z0.D}, P0/Z, [X30, MUL VL]

  (640) 0x4313b0 LD1D	{Z1.D}, P0/Z, [X30, X27,LSL #3]

  (640) 0x4313b4 ADD	W30, W12, W7

  (640) 0x4313b8 ADD	X7, X7, X16

  (640) 0x4313bc ADD	X30, X6, W30,SXTW #3

  (640) 0x4313c0 CMP	X25, X7

  (640) 0x4313c4 REV	Z0.D, Z0.D

  (640) 0x4313c8 REV	Z1.D, Z1.D

  (640) 0x4313cc FNEG	Z0.D, P0/M, Z0.D

  (640) 0x4313d0 FNEG	Z1.D, P0/M, Z1.D

  (640) 0x4313d4 ST1D	{Z0.D}, P0, [X30, MUL VL]

  (640) 0x4313d8 ST1D	{Z1.D}, P0, [X30, X3,LSL #3]

  (640) 0x4313dc B.NE	4313a0

(637) 0x4313e0 CBNZ	X26, 431294

0x4313e4 B	431240

0x4313e8 HINT	#0

0x4313ec HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:547-550
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:547-550

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 6.00 to 0.75 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.00 to 0.50 cycles (12.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	47
loop length	188
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	6.00	6.00	6.00	5.00	5.00
cycles	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	6.00	6.00	6.00	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.25
Overall L1	6.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

7% of peak load performance is reached (7.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
40% of peak store performance is reached (19.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4310d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W21, W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W26, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 431184 <.omp_outlined..94+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <46411c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1976	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W26, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 4311a4 <.omp_outlined..94+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 431240 <.omp_outlined..94+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	update_halo.cpp:547-550
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:547-550

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.00 to 0.50 cycles (12.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	47
loop length	188
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	6.00	6.00	6.00	5.00	5.00
cycles	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	6.00	6.00	6.00	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.25
Overall L1	6.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

7% of peak load performance is reached (7.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
40% of peak store performance is reached (19.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4310d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W21, W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W26, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 431184 <.omp_outlined..94+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <46411c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1976	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W26, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 4311a4 <.omp_outlined..94+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 431240 <.omp_outlined..94+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..94–	0.01	0
▼Loop 637 - update_halo.cpp:547-550 - exec–	0	0
○Loop 639 - update_halo.cpp:549-550 - exec	0.01	0
○Loop 638 - update_halo.cpp:549-550 - exec	0	0
○Loop 640 - update_halo.cpp:549-550 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code