OV - exec - Function .omp

	Function: .omp_outlined..62	Module: exec	Source: update_halo.cpp:375-378 [...]	Coverage: 0.01%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

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69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 375 - 378

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375: #pragma omp parallel for simd

376:       for (int k = (y_min - depth + 1); k < (y_max + 1 + depth + 2); k++) {

377:         for (int j = 0; j < depth; ++j) {

378:           field.xvel0(x_max + 2 + 1 + j, k) = -field.xvel0(x_max + 1 - j, k);

0x42ea90 SUB	SP, SP, #144

0x42ea94 STP	X29, X30, [SP, #48]

0x42ea98 STP	X28, X27, [SP, #64]

0x42ea9c STP	X26, X25, [SP, #80]

0x42eaa0 STP	X24, X23, [SP, #96]

0x42eaa4 STP	X22, X21, [SP, #112]

0x42eaa8 STP	X20, X19, [SP, #128]

0x42eaac ADD	X29, SP, #48

0x42eab0 LDR	W20, [X3]

0x42eab4 LDR	W8, [X4]

0x42eab8 LDR	W25, [X2]

0x42eabc ADD	W8, W20, W8

0x42eac0 SUB	W21, W25, W20

0x42eac4 ADD	W8, W8, #1

0x42eac8 SUBS	W26, W8, W21

0x42eacc B.LT	42eb44

0x42ead0 LDR	W19, [X0]

0x42ead4 LDR	X22, [X5, #168]

0x42ead8 LDR	X23, [X5, #184]

0x42eadc MOVZ	W8, #1

0x42eae0 ADRP	X0,

0x42eae4 ADD	X0, X0, #824

0x42eae8 SUB	X3, X29, #16

0x42eaec SUB	X4, X29, #4

0x42eaf0 LDR	W24, [X6]

0x42eaf4 SUB	X5, X29, #8

0x42eaf8 SUB	X6, X29, #12

0x42eafc MOVZ	W2, #34

0x42eb00 STP	W26, WZR, [X29, #504]

0x42eb04 STP	WZR, W8, [X29, #496]

0x42eb08 STR	W8, [SP]

0x42eb0c MOVZ	W7, #1

0x42eb10 ORR	W1, WZR, W19

0x42eb14 BL	402dc0

0x42eb18 LDP	W8, W9, [X29, #504]

0x42eb1c CMP	W8, W26

0x42eb20 CSEL	W8, W8, W26, #3

0x42eb24 ADD	W10, W8, #1

0x42eb28 CMP	W9, W10

0x42eb2c CCMP	W20, #1, #8, #3

0x42eb30 B.GE	42eb64

(552) 0x42eb34 ORR	W1, WZR, W19

(552) 0x42eb38 ADRP	X0,

(552) 0x42eb3c ADD	X0, X0, #848

(552) 0x42eb40 BL	403260

(552) 0x42eb44 LDP	X20, X19, [SP, #128]

(552) 0x42eb48 LDP	X22, X21, [SP, #112]

(552) 0x42eb4c LDP	X24, X23, [SP, #96]

(552) 0x42eb50 LDP	X26, X25, [SP, #80]

(552) 0x42eb54 LDP	X28, X27, [SP, #64]

(552) 0x42eb58 LDP	X29, X30, [SP, #48]

(552) 0x42eb5c ADD	SP, SP, #144

(552) 0x42eb60 RET

(552) 0x42eb64 ADD	W11, W24, #1

(552) 0x42eb68 UBFM	X18, X20, #61, #60

(552) 0x42eb6c ADD	W15, W24, #3

(552) 0x42eb70 SUB	X0, X20, #1

(552) 0x42eb74 ADD	W14, W9, W25

(552) 0x42eb78 ORR	W10, WZR, WZR

(552) 0x42eb7c PTRUE	P0.D, ALL

(552) 0x42eb80 UBFM	X13, X22, #61, #60

(552) 0x42eb84 SBFM	X16, X11, #61, #31

(552) 0x42eb88 ADD	X1, X23, X18

(552) 0x42eb8c SBFM	X17, X15, #61, #31

(552) 0x42eb90 ADD	X12, X23, X16

(552) 0x42eb94 STP	X12, X11, [SP, #16]

(552) 0x42eb98 ADD	X16, X16, #8

(552) 0x42eb9c ADD	X15, X23, X17

(552) 0x42eba0 ADD	X1, X1, X17

(552) 0x42eba4 SUB	X17, X16, X18

(552) 0x42eba8 ADD	X3, X23, X16

(552) 0x42ebac CNTW	X16, ALL

(552) 0x42ebb0 CMP	X16, #20

(552) 0x42ebb4 ADD	X2, X23, X17

(552) 0x42ebb8 MOVZ	W17, #20

(552) 0x42ebbc SUB	W18, W11, W0

(552) 0x42ebc0 CSEL	X17, X16, X17, #8

(552) 0x42ebc4 ANDS	XZR, X0, #6112

(552) 0x42ebc8 SUB	W14, W14, W20

(552) 0x42ebcc ADD	W12, W14, #1

(552) 0x42ebd0 SUB	X0, XZR, X0,LSL #3

(552) 0x42ebd4 CCMP	W18, W11, #0, #0

(552) 0x42ebd8 ADD	X11, X15, #16

(552) 0x42ebdc ORR	W5, WZR, W12

(552) 0x42ebe0 STR	X11, [SP, #8]

(552) 0x42ebe4 CNTD	X11, ALL

(552) 0x42ebe8 CSINC	W18, WZR, WZR, #13

(552) 0x42ebec CMP	X15, X3

(552) 0x42ebf0 MOVZ	W3, #1

(552) 0x42ebf4 CCMP	X2, X1, #2, #3

(552) 0x42ebf8 ORR	W2, WZR, W12

(552) 0x42ebfc SUB	X4, X3, X11

(552) 0x42ec00 CSINC	W1, WZR, WZR, #2

(552) 0x42ec04 B	42ec1c

(552) 0x42ec08 CMP	W9, W8

(552) 0x42ec0c ORR	W9, WZR, W6

(552) 0x42ec10 ADD	W10, W10, #1

(552) 0x42ec14 ADD	W5, W5, #1

(552) 0x42ec18 B.EQ	42eb34

(552) 0x42ec1c ADD	W6, W9, #1

(552) 0x42ec20 SBFM	X25, X5, #0, #31

(552) 0x42ec24 CMP	X17, X20

(552) 0x42ec28 ADD	W3, W6, W21

(552) 0x42ec2c MADD	X26, X13, X25, X15

(552) 0x42ec30 SBFM	X3, X3, #0, #31

(552) 0x42ec34 MADD	X3, X22, X3, XZR

(552) 0x42ec38 ADD	X7, X23, X3,LSL #3

(552) 0x42ec3c B.LS	42ec48

(552) 0x42ec40 ORR	X27, XZR, XZR

(552) 0x42ec44 B	42ed20

(552) 0x42ec48 LDR	X12, [SP, #16]

(552) 0x42ec4c ADD	W3, W2, W10

(552) 0x42ec50 ORR	W14, WZR, W19

(552) 0x42ec54 SBFM	X3, X3, #0, #31

(552) 0x42ec58 MADD	X3, X13, X3, X12

(552) 0x42ec5c ADD	X19, X3, X0

(552) 0x42ec60 CMP	X19, X3

(552) 0x42ec64 CSINC	W3, W18, WZR, #9

(552) 0x42ec68 ORR	W3, W3, W1

(552) 0x42ec6c TBZ	W3, #0, 42ec80

0x42ec70 ORR	X27, XZR, XZR

0x42ec74 ORR	W19, WZR, W14

0x42ec78 B	42ed20

0x42ec7c HINT	#0

(552) 0x42ec80 UDIV	X3, X20, X16

(552) 0x42ec84 CNTD	X12, ALL

(552) 0x42ec88 ORR	W11, WZR, W1

(552) 0x42ec8c ORR	X1, XZR, X0

(552) 0x42ec90 ORR	W0, WZR, W18

(552) 0x42ec94 ORR	W18, WZR, W2

(552) 0x42ec98 ORR	W2, WZR, W24

(552) 0x42ec9c ORR	X28, XZR, XZR

(552) 0x42eca0 ADDVL	X19, X26, #1

(552) 0x42eca4 UMSUBL	X30, W3, W16, X20

(552) 0x42eca8 UMADDL	X27, W3, W16, XZR

(552) 0x42ecac SUB	X3, XZR, X12

(552) 0x42ecb0 LDR	X12, [SP, #24]

(552) 0x42ecb4 ORR	W24, WZR, W12

(552) 0x42ecb8 HINT	#0

(552) 0x42ecbc HINT	#0

  (551) 0x42ecc0 ADD	X12, X7, W24,SXTW #3

  (551) 0x42ecc4 SUB	W24, W24, W16

  (551) 0x42ecc8 ADD	X12, X12, X4,LSL #3

  (551) 0x42eccc LD1D	{Z0.D}, P0/Z, [X12, MUL VL]

  (551) 0x42ecd0 LD1D	{Z1.D}, P0/Z, [X12, X3,LSL #3]

  (551) 0x42ecd4 REV	Z0.D, Z0.D

  (551) 0x42ecd8 REV	Z1.D, Z1.D

  (551) 0x42ecdc FNEG	Z0.D, P0/M, Z0.D

  (551) 0x42ece0 FNEG	Z1.D, P0/M, Z1.D

  (551) 0x42ece4 ST1D	{Z0.D}, P0, [X26, X28,LSL #3]

  (551) 0x42ece8 ST1D	{Z1.D}, P0, [X19, X28,LSL #3]

  (551) 0x42ecec ADD	X28, X28, X16

  (551) 0x42ecf0 CMP	X27, X28

  (551) 0x42ecf4 B.NE	42ecc0

(552) 0x42ecf8 ORR	W24, WZR, W2

(552) 0x42ecfc ORR	W19, WZR, W14

(552) 0x42ed00 ORR	W2, WZR, W18

(552) 0x42ed04 ORR	W18, WZR, W0

(552) 0x42ed08 ORR	X0, XZR, X1

(552) 0x42ed0c ORR	W1, WZR, W11

(552) 0x42ed10 CBZ	X30, 42ec08

0x42ed14 HINT	#0

0x42ed18 HINT	#0

0x42ed1c HINT	#0

(552) 0x42ed20 SUB	W12, W20, W27

(552) 0x42ed24 ORR	X28, XZR, X27

(552) 0x42ed28 ANDS	X30, X12, #4160

(552) 0x42ed2c B.EQ	42ed5c

(552) 0x42ed30 LDR	X11, [SP, #24]

(552) 0x42ed34 ORR	X28, XZR, X27

(552) 0x42ed38 SUB	W3, W11, W27

(552) 0x42ed3c HINT	#0

  (554) 0x42ed40 LDR	D0, [X7, X3,SXTW #3]

  (554) 0x42ed44 SUB	W3, W3, #1

  (554) 0x42ed48 SUBS	X30, X30, #1

  (554) 0x42ed4c FNEG	D0, D0

  (554) 0x42ed50 STR	D0, [X26, X28,LSL #3]

  (554) 0x42ed54 ADD	X28, X28, #1

  (554) 0x42ed58 B.NE	42ed40

(552) 0x42ed5c ORN	X12, XZR, X27

(552) 0x42ed60 ADD	X12, X12, X20

(552) 0x42ed64 CMP	X12, #3

(552) 0x42ed68 B.CC	42ec08

0x42ed6c MADD	X12, X13, X25, XZR

0x42ed70 LDR	X11, [SP, #8]

0x42ed74 SUB	X25, X20, X28

0x42ed78 SUB	W26, W24, W28

0x42ed7c ADD	X12, X12, X28,LSL #3

0x42ed80 ADD	X27, X11, X12

(553) 0x42ed84 ADD	W12, W26, #1

(553) 0x42ed88 SUB	X25, X25, #4

(553) 0x42ed8c LDR	D0, [X7, X12,SXTW #3]

(553) 0x42ed90 SUB	W12, W26, #1

(553) 0x42ed94 FNEG	D0, D0

(553) 0x42ed98 STUR	D0, [X27, #496]

(553) 0x42ed9c LDR	D0, [X7, X26,SXTW #3]

(553) 0x42eda0 FNEG	D0, D0

(553) 0x42eda4 STUR	D0, [X27, #504]

(553) 0x42eda8 LDR	D0, [X7, X12,SXTW #3]

(553) 0x42edac SUB	W12, W26, #2

(553) 0x42edb0 SUB	W26, W26, #4

(553) 0x42edb4 FNEG	D0, D0

(553) 0x42edb8 STR	D0, [X27]

(553) 0x42edbc LDR	D0, [X7, X12,SXTW #3]

(553) 0x42edc0 FNEG	D0, D0

(553) 0x42edc4 STR	D0, [X27, #8]

(553) 0x42edc8 ADD	X27, X27, #32

(553) 0x42edcc CBNZ	X25, 42ed84

0x42edd0 B	42ec08

0x42edd4 HINT	#0

0x42edd8 HINT	#0

0x42eddc HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:375-378
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:375-378

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 7.25 to 0.94 cycles (7.73x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.25 to 0.50 cycles (14.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	58
loop length	232
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	2.50	2.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.38
Overall L1	7.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.25 cycles. At this rate:

7% of peak load performance is reached (7.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42ea90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W21, W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W26, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42eb44 <.omp_outlined..62+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <464ae0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #824	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W26, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42eb64 <.omp_outlined..62+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42ed20 <.omp_outlined..62+0x290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
MADD X12, X13, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X11, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X25, X20, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42ec08 <.omp_outlined..62+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	update_halo.cpp:375-378
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:375-378

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.25 to 0.50 cycles (14.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	58
loop length	232
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	2.50	2.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.38
Overall L1	7.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.25 cycles. At this rate:

7% of peak load performance is reached (7.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42ea90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W21, W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W26, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42eb44 <.omp_outlined..62+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <464ae0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #824	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W26, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42eb64 <.omp_outlined..62+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42ed20 <.omp_outlined..62+0x290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
MADD X12, X13, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X11, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X25, X20, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42ec08 <.omp_outlined..62+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..62–	0.01	0
▼Loop 552 - update_halo.cpp:375-378 - exec–	0.01	0
○Loop 554 - update_halo.cpp:377-378 - exec	0	0
○Loop 551 - update_halo.cpp:377-378 - exec	0	0
○Loop 553 - update_halo.cpp:377-378 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code