OV - exec - Function .omp

	Function: .omp_outlined..44	Module: exec	Source: update_halo.cpp:279-282	Coverage: 0.01%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 279 - 282

--------------------------------------------------------------------------------

279: #pragma omp parallel for simd

280:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

281:         for (int j = 0; j < depth; ++j) {

282:           field.viscosity(1 - j, k) = field.viscosity(2 + j, k);

0x42d550 SUB	SP, SP, #128

0x42d554 STP	X29, X30, [SP, #32]

0x42d558 STP	X28, X27, [SP, #48]

0x42d55c STP	X26, X25, [SP, #64]

0x42d560 STP	X24, X23, [SP, #80]

0x42d564 STP	X22, X21, [SP, #96]

0x42d568 STP	X20, X19, [SP, #112]

0x42d56c ADD	X29, SP, #32

0x42d570 LDR	W22, [X2]

0x42d574 LDR	W20, [X3]

0x42d578 LDR	W8, [X4]

0x42d57c SUB	W9, W22, W20

0x42d580 ADD	W8, W8, W20

0x42d584 SUBS	W24, W8, W9

0x42d588 B.LT	42d600

0x42d58c LDR	W19, [X0]

0x42d590 LDR	X23, [X5, #120]

0x42d594 LDR	X21, [X5, #136]

0x42d598 MOVZ	W8, #1

0x42d59c ADRP	X0,

0x42d5a0 ADD	X0, X0, #176

0x42d5a4 ADD	X3, SP, #16

0x42d5a8 SUB	X4, X29, #4

0x42d5ac STP	W24, WZR, [X29, #504]

0x42d5b0 SUB	X5, X29, #8

0x42d5b4 SUB	X6, X29, #12

0x42d5b8 MOVZ	W2, #34

0x42d5bc STUR	W8, [X29, #500]

0x42d5c0 STR	WZR, [SP, #16]

0x42d5c4 STR	W8, [SP]

0x42d5c8 MOVZ	W7, #1

0x42d5cc ORR	W1, WZR, W19

0x42d5d0 BL	402dc0

0x42d5d4 LDP	W8, W9, [X29, #504]

0x42d5d8 CMP	W8, W24

0x42d5dc CSEL	W8, W8, W24, #3

0x42d5e0 ADD	W10, W8, #1

0x42d5e4 CMP	W9, W10

0x42d5e8 CCMP	W20, #1, #8, #3

0x42d5ec B.GE	42d620

(487) 0x42d5f0 ORR	W1, WZR, W19

(487) 0x42d5f4 ADRP	X0,

(487) 0x42d5f8 ADD	X0, X0, #200

(487) 0x42d5fc BL	403260

(487) 0x42d600 LDP	X20, X19, [SP, #112]

(487) 0x42d604 LDP	X22, X21, [SP, #96]

(487) 0x42d608 LDP	X24, X23, [SP, #80]

(487) 0x42d60c LDP	X26, X25, [SP, #64]

(487) 0x42d610 LDP	X28, X27, [SP, #48]

(487) 0x42d614 LDP	X29, X30, [SP, #32]

(487) 0x42d618 ADD	SP, SP, #128

(487) 0x42d61c RET

(487) 0x42d620 ADD	W15, W9, W22

(487) 0x42d624 CNTW	X11, ALL

(487) 0x42d628 SUB	X2, X20, #1

(487) 0x42d62c ADD	X14, X21, #16

(487) 0x42d630 MOVZ	W17, #12

(487) 0x42d634 RDVL	X4, #1

(487) 0x42d638 ORR	W10, WZR, WZR

(487) 0x42d63c ADD	X12, X21, #8

(487) 0x42d640 UBFM	X13, X23, #61, #60

(487) 0x42d644 RDVL	X18, #2

(487) 0x42d648 RDVL	X0, #62

(487) 0x42d64c ADD	X1, X21, #24

(487) 0x42d650 CMP	X11, #12

(487) 0x42d654 SUB	W16, W15, W20

(487) 0x42d658 SUB	X15, XZR, X2,LSL #3

(487) 0x42d65c UBFM	X2, X2, #61, #63

(487) 0x42d660 CSEL	X17, X11, X17, #8

(487) 0x42d664 ADDVL	X3, X14, #1

(487) 0x42d668 SUB	X4, X14, X4

(487) 0x42d66c ADD	W16, W16, #1

(487) 0x42d670 ADDVL	X5, X14, #62

(487) 0x42d674 PTRUE	P0.B, ALL

(487) 0x42d678 ORR	W6, WZR, W16

(487) 0x42d67c B	42d694

(487) 0x42d680 CMP	W9, W8

(487) 0x42d684 ADD	W9, W9, #1

(487) 0x42d688 ADD	W10, W10, #1

(487) 0x42d68c ADD	W6, W6, #1

(487) 0x42d690 B.EQ	42d5f0

(487) 0x42d694 SBFM	X7, X6, #0, #31

(487) 0x42d698 CMP	X17, X20

(487) 0x42d69c MADD	X7, X13, X7, XZR

(487) 0x42d6a0 B.HI	42d6c0

(487) 0x42d6a4 ADD	W22, W16, W10

(487) 0x42d6a8 SBFM	X22, X22, #0, #31

(487) 0x42d6ac MADD	X22, X13, X22, X12

(487) 0x42d6b0 ADD	X23, X22, X15

(487) 0x42d6b4 CMP	X23, X22

(487) 0x42d6b8 CCMP	X2, #0, #0, #9

(487) 0x42d6bc B.EQ	42d760

(487) 0x42d6c0 ORR	X22, XZR, XZR

(487) 0x42d6c4 SUB	W23, W20, W22

(487) 0x42d6c8 ANDS	X24, X23, #4160

(487) 0x42d6cc ORR	X23, XZR, X22

(487) 0x42d6d0 B.EQ	42d6f8

(487) 0x42d6d4 SUB	X23, X7, X22,LSL #3

(487) 0x42d6d8 ADD	X25, X14, X7

(487) 0x42d6dc ADD	X26, X12, X23

(487) 0x42d6e0 ORR	X23, XZR, X22

  (489) 0x42d6e4 LDR	D0, [X25, X23,LSL #3]

  (489) 0x42d6e8 ADD	X23, X23, #1

  (489) 0x42d6ec SUBS	X24, X24, #1

  (489) 0x42d6f0 STR	D0, [X26], #504

  (489) 0x42d6f4 B.NE	42d6e4

(487) 0x42d6f8 ORN	X22, XZR, X22

(487) 0x42d6fc ADD	X22, X22, X20

(487) 0x42d700 CMP	X22, #3

(487) 0x42d704 B.CC	42d680

(487) 0x42d708 UBFM	X24, X23, #61, #60

(487) 0x42d70c SUB	X23, X20, X23

(487) 0x42d710 SUB	X22, X7, X24

(487) 0x42d714 ADD	X7, X7, X24

(487) 0x42d718 ADD	X22, X21, X22

(487) 0x42d71c ADD	X7, X1, X7

  (488) 0x42d720 LDUR	D0, [X7, #504]

  (488) 0x42d724 SUBS	X23, X23, #4

  (488) 0x42d728 STR	D0, [X22, #8]

  (488) 0x42d72c LDR	D0, [X7]

  (488) 0x42d730 STR	D0, [X22]

  (488) 0x42d734 LDR	D0, [X7, #8]

  (488) 0x42d738 STUR	D0, [X22, #504]

  (488) 0x42d73c LDR	D0, [X7, #16]

  (488) 0x42d740 ADD	X7, X7, #32

  (488) 0x42d744 STUR	D0, [X22, #496]

  (488) 0x42d748 SUB	X22, X22, #32

  (488) 0x42d74c B.NE	42d720

(487) 0x42d750 B	42d680

0x42d754 HINT	#0

0x42d758 HINT	#0

0x42d75c HINT	#0

(487) 0x42d760 UDIV	X22, X20, X11

(487) 0x42d764 ORR	X25, XZR, X5

(487) 0x42d768 ORR	X26, XZR, X4

(487) 0x42d76c ORR	X27, XZR, X3

(487) 0x42d770 ORR	X28, XZR, X14

(487) 0x42d774 UMSUBL	X23, W22, W11, X20

(487) 0x42d778 UMADDL	X22, W22, W11, XZR

(487) 0x42d77c ORR	X24, XZR, X22

  (490) 0x42d780 LD1B	{Z0.B}, P0/Z, [X28, X7]

  (490) 0x42d784 LD1B	{Z1.B}, P0/Z, [X27, X7]

  (490) 0x42d788 ADD	X28, X28, X18

  (490) 0x42d78c ADD	X27, X27, X18

  (490) 0x42d790 SUBS	X24, X24, X11

  (490) 0x42d794 REV	Z0.D, Z0.D

  (490) 0x42d798 ST1B	{Z0.B}, P0, [X26, X7]

  (490) 0x42d79c REV	Z0.D, Z1.D

  (490) 0x42d7a0 ADD	X26, X26, X0

  (490) 0x42d7a4 ST1B	{Z0.B}, P0, [X25, X7]

  (490) 0x42d7a8 ADD	X25, X25, X0

  (490) 0x42d7ac B.NE	42d780

(487) 0x42d7b0 CBNZ	X23, 42d6c4

0x42d7b4 B	42d680

0x42d7b8 HINT	#0

0x42d7bc HINT	#0

0x43800c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:279-282
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:279-282.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.67 to 0.71 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	47
loop length	188
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42d550

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42d600 <.omp_outlined..44+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <46459c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42d620 <.omp_outlined..44+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 42d680 <.omp_outlined..44+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	update_halo.cpp:279-282
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:279-282.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	47
loop length	188
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42d550

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42d600 <.omp_outlined..44+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <46459c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42d620 <.omp_outlined..44+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 42d680 <.omp_outlined..44+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..44–	0.01	0
▼Loop 487 - update_halo.cpp:279-282 - exec–	0	0
○Loop 489 - update_halo.cpp:281-282 - exec	0.01	0
○Loop 488 - update_halo.cpp:281-282 - exec	0	0
○Loop 490 - update_halo.cpp:281-282 - exec	0	0

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ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code