OV - exec - Function .omp

	Function: .omp_outlined..38	Module: exec	Source: update_halo.cpp:246-249 [...]	Coverage: 0.02%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

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69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 246 - 249

--------------------------------------------------------------------------------

246: #pragma omp parallel for simd

247:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

248:         for (int j = 0; j < depth; ++j) {

249:           field.pressure(x_max + 2 + j, k) = field.pressure(x_max + 1 - j, k);

0x42ce60 SUB	SP, SP, #144

0x42ce64 STP	X29, X30, [SP, #48]

0x42ce68 STP	X28, X27, [SP, #64]

0x42ce6c STP	X26, X25, [SP, #80]

0x42ce70 STP	X24, X23, [SP, #96]

0x42ce74 STP	X22, X21, [SP, #112]

0x42ce78 STP	X20, X19, [SP, #128]

0x42ce7c ADD	X29, SP, #48

0x42ce80 LDR	W25, [X2]

0x42ce84 LDR	W20, [X3]

0x42ce88 LDR	W8, [X4]

0x42ce8c SUB	W21, W25, W20

0x42ce90 ADD	W8, W8, W20

0x42ce94 SUBS	W26, W8, W21

0x42ce98 B.LT	42cf10

0x42ce9c LDR	W19, [X0]

0x42cea0 LDR	X22, [X5, #96]

0x42cea4 LDR	X23, [X5, #112]

0x42cea8 MOVZ	W8, #1

0x42ceac ADRP	X0,

0x42ceb0 ADD	X0, X0, #4056

0x42ceb4 SUB	X3, X29, #16

0x42ceb8 SUB	X4, X29, #4

0x42cebc LDR	W24, [X6]

0x42cec0 SUB	X5, X29, #8

0x42cec4 SUB	X6, X29, #12

0x42cec8 MOVZ	W2, #34

0x42cecc STP	W26, WZR, [X29, #504]

0x42ced0 STP	WZR, W8, [X29, #496]

0x42ced4 STR	W8, [SP]

0x42ced8 MOVZ	W7, #1

0x42cedc ORR	W1, WZR, W19

0x42cee0 BL	402dc0

0x42cee4 LDP	W8, W9, [X29, #504]

0x42cee8 CMP	W8, W26

0x42ceec CSEL	W8, W8, W26, #3

0x42cef0 ADD	W10, W8, #1

0x42cef4 CMP	W9, W10

0x42cef8 CCMP	W20, #1, #8, #3

0x42cefc B.GE	42cf30

(466) 0x42cf00 ORR	W1, WZR, W19

(466) 0x42cf04 ADRP	X0,

(466) 0x42cf08 ADD	X0, X0, #4080

(466) 0x42cf0c BL	403260

(466) 0x42cf10 LDP	X20, X19, [SP, #128]

(466) 0x42cf14 LDP	X22, X21, [SP, #112]

(466) 0x42cf18 LDP	X24, X23, [SP, #96]

(466) 0x42cf1c LDP	X26, X25, [SP, #80]

(466) 0x42cf20 LDP	X28, X27, [SP, #64]

(466) 0x42cf24 LDP	X29, X30, [SP, #48]

(466) 0x42cf28 ADD	SP, SP, #144

(466) 0x42cf2c RET

(466) 0x42cf30 ADD	W11, W24, #1

(466) 0x42cf34 UBFM	X18, X20, #61, #60

(466) 0x42cf38 ADD	W15, W24, #2

(466) 0x42cf3c SUB	X0, X20, #1

(466) 0x42cf40 ADD	W14, W9, W25

(466) 0x42cf44 ORR	W10, WZR, WZR

(466) 0x42cf48 PTRUE	P0.D, ALL

(466) 0x42cf4c UBFM	X13, X22, #61, #60

(466) 0x42cf50 SBFM	X16, X11, #61, #31

(466) 0x42cf54 ADD	X1, X23, X18

(466) 0x42cf58 SBFM	X17, X15, #61, #31

(466) 0x42cf5c ADD	X12, X23, X16

(466) 0x42cf60 STP	X12, X11, [SP, #16]

(466) 0x42cf64 ADD	X16, X16, #8

(466) 0x42cf68 ADD	X15, X23, X17

(466) 0x42cf6c ADD	X1, X1, X17

(466) 0x42cf70 SUB	X17, X16, X18

(466) 0x42cf74 ADD	X3, X23, X16

(466) 0x42cf78 CNTW	X16, ALL

(466) 0x42cf7c CMP	X16, #28

(466) 0x42cf80 ADD	X2, X23, X17

(466) 0x42cf84 MOVZ	W17, #28

(466) 0x42cf88 SUB	W18, W11, W0

(466) 0x42cf8c CSEL	X17, X16, X17, #8

(466) 0x42cf90 ANDS	XZR, X0, #6112

(466) 0x42cf94 SUB	W14, W14, W20

(466) 0x42cf98 ADD	W12, W14, #1

(466) 0x42cf9c SUB	X0, XZR, X0,LSL #3

(466) 0x42cfa0 CCMP	W18, W11, #0, #0

(466) 0x42cfa4 ADD	X11, X15, #16

(466) 0x42cfa8 ORR	W5, WZR, W12

(466) 0x42cfac STR	X11, [SP, #8]

(466) 0x42cfb0 CNTD	X11, ALL

(466) 0x42cfb4 CSINC	W18, WZR, WZR, #13

(466) 0x42cfb8 CMP	X15, X3

(466) 0x42cfbc MOVZ	W3, #1

(466) 0x42cfc0 CCMP	X2, X1, #2, #3

(466) 0x42cfc4 ORR	W2, WZR, W12

(466) 0x42cfc8 SUB	X4, X3, X11

(466) 0x42cfcc CSINC	W1, WZR, WZR, #2

(466) 0x42cfd0 B	42cff4

0x42cfd4 HINT	#0

0x42cfd8 HINT	#0

0x42cfdc HINT	#0

(466) 0x42cfe0 CMP	W9, W8

(466) 0x42cfe4 ORR	W9, WZR, W6

(466) 0x42cfe8 ADD	W10, W10, #1

(466) 0x42cfec ADD	W5, W5, #1

(466) 0x42cff0 B.EQ	42cf00

(466) 0x42cff4 ADD	W6, W9, #1

(466) 0x42cff8 SBFM	X25, X5, #0, #31

(466) 0x42cffc CMP	X17, X20

(466) 0x42d000 ADD	W3, W6, W21

(466) 0x42d004 MADD	X26, X13, X25, X15

(466) 0x42d008 SBFM	X3, X3, #0, #31

(466) 0x42d00c MADD	X3, X22, X3, XZR

(466) 0x42d010 ADD	X7, X23, X3,LSL #3

(466) 0x42d014 B.LS	42d020

(466) 0x42d018 ORR	X27, XZR, XZR

(466) 0x42d01c B	42d0ec

(466) 0x42d020 LDR	X12, [SP, #16]

(466) 0x42d024 ADD	W3, W2, W10

(466) 0x42d028 ORR	W14, WZR, W19

(466) 0x42d02c SBFM	X3, X3, #0, #31

(466) 0x42d030 MADD	X3, X13, X3, X12

(466) 0x42d034 ADD	X19, X3, X0

(466) 0x42d038 CMP	X19, X3

(466) 0x42d03c CSINC	W3, W18, WZR, #9

(466) 0x42d040 ORR	W3, W3, W1

(466) 0x42d044 TBZ	W3, #0, 42d060

0x42d048 ORR	X27, XZR, XZR

0x42d04c ORR	W19, WZR, W14

0x42d050 B	42d0ec

0x42d054 HINT	#0

0x42d058 HINT	#0

0x42d05c HINT	#0

(466) 0x42d060 UDIV	X3, X20, X16

(466) 0x42d064 CNTD	X12, ALL

(466) 0x42d068 ORR	W11, WZR, W1

(466) 0x42d06c ORR	X1, XZR, X0

(466) 0x42d070 ORR	W0, WZR, W18

(466) 0x42d074 ORR	W18, WZR, W2

(466) 0x42d078 ORR	W2, WZR, W24

(466) 0x42d07c ORR	X28, XZR, XZR

(466) 0x42d080 ADDVL	X19, X26, #1

(466) 0x42d084 UMSUBL	X30, W3, W16, X20

(466) 0x42d088 UMADDL	X27, W3, W16, XZR

(466) 0x42d08c SUB	X3, XZR, X12

(466) 0x42d090 LDR	X12, [SP, #24]

(466) 0x42d094 ORR	W24, WZR, W12

(466) 0x42d098 HINT	#0

(466) 0x42d09c HINT	#0

  (465) 0x42d0a0 ADD	X12, X7, W24,SXTW #3

  (465) 0x42d0a4 SUB	W24, W24, W16

  (465) 0x42d0a8 ADD	X12, X12, X4,LSL #3

  (465) 0x42d0ac LD1D	{Z0.D}, P0/Z, [X12, MUL VL]

  (465) 0x42d0b0 LD1D	{Z1.D}, P0/Z, [X12, X3,LSL #3]

  (465) 0x42d0b4 REV	Z0.D, Z0.D

  (465) 0x42d0b8 REV	Z1.D, Z1.D

  (465) 0x42d0bc ST1D	{Z0.D}, P0, [X26, X28,LSL #3]

  (465) 0x42d0c0 ST1D	{Z1.D}, P0, [X19, X28,LSL #3]

  (465) 0x42d0c4 ADD	X28, X28, X16

  (465) 0x42d0c8 CMP	X27, X28

  (465) 0x42d0cc B.NE	42d0a0

(466) 0x42d0d0 ORR	W24, WZR, W2

(466) 0x42d0d4 ORR	W19, WZR, W14

(466) 0x42d0d8 ORR	W2, WZR, W18

(466) 0x42d0dc ORR	W18, WZR, W0

(466) 0x42d0e0 ORR	X0, XZR, X1

(466) 0x42d0e4 ORR	W1, WZR, W11

(466) 0x42d0e8 CBZ	X30, 42cfe0

(466) 0x42d0ec SUB	W12, W20, W27

(466) 0x42d0f0 ORR	X28, XZR, X27

(466) 0x42d0f4 ANDS	X30, X12, #4160

(466) 0x42d0f8 B.EQ	42d120

(466) 0x42d0fc LDR	X12, [SP, #24]

(466) 0x42d100 ORR	X28, XZR, X27

(466) 0x42d104 SUB	W3, W12, W27

  (468) 0x42d108 LDR	D0, [X7, X3,SXTW #3]

  (468) 0x42d10c SUB	W3, W3, #1

  (468) 0x42d110 SUBS	X30, X30, #1

  (468) 0x42d114 STR	D0, [X26, X28,LSL #3]

  (468) 0x42d118 ADD	X28, X28, #1

  (468) 0x42d11c B.NE	42d108

(466) 0x42d120 ORN	X12, XZR, X27

(466) 0x42d124 ADD	X12, X12, X20

(466) 0x42d128 CMP	X12, #3

(466) 0x42d12c B.CC	42cfe0

0x42d130 MADD	X12, X13, X25, XZR

0x42d134 LDR	X14, [SP, #8]

0x42d138 SUB	X25, X20, X28

0x42d13c SUB	W26, W24, W28

0x42d140 ADD	X12, X12, X28,LSL #3

0x42d144 ADD	X27, X14, X12

(467) 0x42d148 ADD	W12, W26, #1

(467) 0x42d14c SUB	X25, X25, #4

(467) 0x42d150 LDR	D0, [X7, X12,SXTW #3]

(467) 0x42d154 SUB	W12, W26, #1

(467) 0x42d158 STUR	D0, [X27, #496]

(467) 0x42d15c LDR	D0, [X7, X26,SXTW #3]

(467) 0x42d160 STUR	D0, [X27, #504]

(467) 0x42d164 LDR	D0, [X7, X12,SXTW #3]

(467) 0x42d168 SUB	W12, W26, #2

(467) 0x42d16c SUB	W26, W26, #4

(467) 0x42d170 STR	D0, [X27]

(467) 0x42d174 LDR	D0, [X7, X12,SXTW #3]

(467) 0x42d178 STR	D0, [X27, #8]

(467) 0x42d17c ADD	X27, X27, #32

(467) 0x42d180 CBNZ	X25, 42d148

0x42d184 B	42cfe0

0x42d188 HINT	#0

0x42d18c HINT	#0

0x437848 HINT	#0

0x43784c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:246-249
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:246-249

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 7.00 to 0.91 cycles (7.72x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 0.50 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	7.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

7% of peak load performance is reached (7.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
34% of peak store performance is reached (16.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42ce60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W21, W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W26, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42cf10 <.omp_outlined..38+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <463eac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #4056	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W26, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42cf30 <.omp_outlined..38+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42d0ec <.omp_outlined..38+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
MADD X12, X13, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X14, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X25, X20, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42cfe0 <.omp_outlined..38+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	update_halo.cpp:246-249
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:246-249

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 0.50 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	7.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

7% of peak load performance is reached (7.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
34% of peak store performance is reached (16.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42ce60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W21, W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W26, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42cf10 <.omp_outlined..38+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <463eac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #4056	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W26, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42cf30 <.omp_outlined..38+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42d0ec <.omp_outlined..38+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
MADD X12, X13, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X14, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X25, X20, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42cfe0 <.omp_outlined..38+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..38–	0.02	0.01
▼Loop 466 - update_halo.cpp:246-249 - exec–	0	0
○Loop 468 - update_halo.cpp:248-249 - exec	0.02	0.01
○Loop 465 - update_halo.cpp:248-249 - exec	0	0
○Loop 467 - update_halo.cpp:248-249 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code