OV - exec - Function .omp

	Function: .omp_outlined..30	Module: exec	Source: update_halo.cpp:203-206 [...]	Coverage: 0.01%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 203 - 206

--------------------------------------------------------------------------------

203: #pragma omp parallel for simd

204:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

205:         for (int j = 0; j < depth; ++j) {

206:           field.energy1(x_max + 2 + j, k) = field.energy1(x_max + 1 - j, k);

0x42c500 SUB	SP, SP, #144

0x42c504 STP	X29, X30, [SP, #48]

0x42c508 STP	X28, X27, [SP, #64]

0x42c50c STP	X26, X25, [SP, #80]

0x42c510 STP	X24, X23, [SP, #96]

0x42c514 STP	X22, X21, [SP, #112]

0x42c518 STP	X20, X19, [SP, #128]

0x42c51c ADD	X29, SP, #48

0x42c520 LDR	W25, [X2]

0x42c524 LDR	W20, [X3]

0x42c528 LDR	W8, [X4]

0x42c52c SUB	W21, W25, W20

0x42c530 ADD	W8, W8, W20

0x42c534 SUBS	W26, W8, W21

0x42c538 B.LT	42c5b0

0x42c53c LDR	W19, [X0]

0x42c540 LDR	X22, [X5, #72]

0x42c544 LDR	X23, [X5, #88]

0x42c548 MOVZ	W8, #1

0x42c54c ADRP	X0,

0x42c550 ADD	X0, X0, #3768

0x42c554 SUB	X3, X29, #16

0x42c558 SUB	X4, X29, #4

0x42c55c LDR	W24, [X6]

0x42c560 SUB	X5, X29, #8

0x42c564 SUB	X6, X29, #12

0x42c568 MOVZ	W2, #34

0x42c56c STP	W26, WZR, [X29, #504]

0x42c570 STP	WZR, W8, [X29, #496]

0x42c574 STR	W8, [SP]

0x42c578 MOVZ	W7, #1

0x42c57c ORR	W1, WZR, W19

0x42c580 BL	402dc0

0x42c584 LDP	W8, W9, [X29, #504]

0x42c588 CMP	W8, W26

0x42c58c CSEL	W8, W8, W26, #3

0x42c590 ADD	W10, W8, #1

0x42c594 CMP	W9, W10

0x42c598 CCMP	W20, #1, #8, #3

0x42c59c B.GE	42c5d0

(436) 0x42c5a0 ORR	W1, WZR, W19

(436) 0x42c5a4 ADRP	X0,

(436) 0x42c5a8 ADD	X0, X0, #3792

(436) 0x42c5ac BL	403260

(436) 0x42c5b0 LDP	X20, X19, [SP, #128]

(436) 0x42c5b4 LDP	X22, X21, [SP, #112]

(436) 0x42c5b8 LDP	X24, X23, [SP, #96]

(436) 0x42c5bc LDP	X26, X25, [SP, #80]

(436) 0x42c5c0 LDP	X28, X27, [SP, #64]

(436) 0x42c5c4 LDP	X29, X30, [SP, #48]

(436) 0x42c5c8 ADD	SP, SP, #144

(436) 0x42c5cc RET

(436) 0x42c5d0 ADD	W11, W24, #1

(436) 0x42c5d4 UBFM	X18, X20, #61, #60

(436) 0x42c5d8 ADD	W15, W24, #2

(436) 0x42c5dc SUB	X0, X20, #1

(436) 0x42c5e0 ADD	W14, W9, W25

(436) 0x42c5e4 ORR	W10, WZR, WZR

(436) 0x42c5e8 PTRUE	P0.D, ALL

(436) 0x42c5ec UBFM	X13, X22, #61, #60

(436) 0x42c5f0 SBFM	X16, X11, #61, #31

(436) 0x42c5f4 ADD	X1, X23, X18

(436) 0x42c5f8 SBFM	X17, X15, #61, #31

(436) 0x42c5fc ADD	X12, X23, X16

(436) 0x42c600 STP	X12, X11, [SP, #16]

(436) 0x42c604 ADD	X16, X16, #8

(436) 0x42c608 ADD	X15, X23, X17

(436) 0x42c60c ADD	X1, X1, X17

(436) 0x42c610 SUB	X17, X16, X18

(436) 0x42c614 ADD	X3, X23, X16

(436) 0x42c618 CNTW	X16, ALL

(436) 0x42c61c CMP	X16, #28

(436) 0x42c620 ADD	X2, X23, X17

(436) 0x42c624 MOVZ	W17, #28

(436) 0x42c628 SUB	W18, W11, W0

(436) 0x42c62c CSEL	X17, X16, X17, #8

(436) 0x42c630 ANDS	XZR, X0, #6112

(436) 0x42c634 SUB	W14, W14, W20

(436) 0x42c638 ADD	W12, W14, #1

(436) 0x42c63c SUB	X0, XZR, X0,LSL #3

(436) 0x42c640 CCMP	W18, W11, #0, #0

(436) 0x42c644 ADD	X11, X15, #16

(436) 0x42c648 ORR	W5, WZR, W12

(436) 0x42c64c STR	X11, [SP, #8]

(436) 0x42c650 CNTD	X11, ALL

(436) 0x42c654 CSINC	W18, WZR, WZR, #13

(436) 0x42c658 CMP	X15, X3

(436) 0x42c65c MOVZ	W3, #1

(436) 0x42c660 CCMP	X2, X1, #2, #3

(436) 0x42c664 ORR	W2, WZR, W12

(436) 0x42c668 SUB	X4, X3, X11

(436) 0x42c66c CSINC	W1, WZR, WZR, #2

(436) 0x42c670 B	42c694

0x42c674 HINT	#0

0x42c678 HINT	#0

0x42c67c HINT	#0

(436) 0x42c680 CMP	W9, W8

(436) 0x42c684 ORR	W9, WZR, W6

(436) 0x42c688 ADD	W10, W10, #1

(436) 0x42c68c ADD	W5, W5, #1

(436) 0x42c690 B.EQ	42c5a0

(436) 0x42c694 ADD	W6, W9, #1

(436) 0x42c698 SBFM	X25, X5, #0, #31

(436) 0x42c69c CMP	X17, X20

(436) 0x42c6a0 ADD	W3, W6, W21

(436) 0x42c6a4 MADD	X26, X13, X25, X15

(436) 0x42c6a8 SBFM	X3, X3, #0, #31

(436) 0x42c6ac MADD	X3, X22, X3, XZR

(436) 0x42c6b0 ADD	X7, X23, X3,LSL #3

(436) 0x42c6b4 B.LS	42c6c0

(436) 0x42c6b8 ORR	X27, XZR, XZR

(436) 0x42c6bc B	42c78c

(436) 0x42c6c0 LDR	X12, [SP, #16]

(436) 0x42c6c4 ADD	W3, W2, W10

(436) 0x42c6c8 ORR	W14, WZR, W19

(436) 0x42c6cc SBFM	X3, X3, #0, #31

(436) 0x42c6d0 MADD	X3, X13, X3, X12

(436) 0x42c6d4 ADD	X19, X3, X0

(436) 0x42c6d8 CMP	X19, X3

(436) 0x42c6dc CSINC	W3, W18, WZR, #9

(436) 0x42c6e0 ORR	W3, W3, W1

(436) 0x42c6e4 TBZ	W3, #0, 42c700

0x42c6e8 ORR	X27, XZR, XZR

0x42c6ec ORR	W19, WZR, W14

0x42c6f0 B	42c78c

0x42c6f4 HINT	#0

0x42c6f8 HINT	#0

0x42c6fc HINT	#0

(436) 0x42c700 UDIV	X3, X20, X16

(436) 0x42c704 CNTD	X12, ALL

(436) 0x42c708 ORR	W11, WZR, W1

(436) 0x42c70c ORR	X1, XZR, X0

(436) 0x42c710 ORR	W0, WZR, W18

(436) 0x42c714 ORR	W18, WZR, W2

(436) 0x42c718 ORR	W2, WZR, W24

(436) 0x42c71c ORR	X28, XZR, XZR

(436) 0x42c720 ADDVL	X19, X26, #1

(436) 0x42c724 UMSUBL	X30, W3, W16, X20

(436) 0x42c728 UMADDL	X27, W3, W16, XZR

(436) 0x42c72c SUB	X3, XZR, X12

(436) 0x42c730 LDR	X12, [SP, #24]

(436) 0x42c734 ORR	W24, WZR, W12

(436) 0x42c738 HINT	#0

(436) 0x42c73c HINT	#0

  (435) 0x42c740 ADD	X12, X7, W24,SXTW #3

  (435) 0x42c744 SUB	W24, W24, W16

  (435) 0x42c748 ADD	X12, X12, X4,LSL #3

  (435) 0x42c74c LD1D	{Z0.D}, P0/Z, [X12, MUL VL]

  (435) 0x42c750 LD1D	{Z1.D}, P0/Z, [X12, X3,LSL #3]

  (435) 0x42c754 REV	Z0.D, Z0.D

  (435) 0x42c758 REV	Z1.D, Z1.D

  (435) 0x42c75c ST1D	{Z0.D}, P0, [X26, X28,LSL #3]

  (435) 0x42c760 ST1D	{Z1.D}, P0, [X19, X28,LSL #3]

  (435) 0x42c764 ADD	X28, X28, X16

  (435) 0x42c768 CMP	X27, X28

  (435) 0x42c76c B.NE	42c740

(436) 0x42c770 ORR	W24, WZR, W2

(436) 0x42c774 ORR	W19, WZR, W14

(436) 0x42c778 ORR	W2, WZR, W18

(436) 0x42c77c ORR	W18, WZR, W0

(436) 0x42c780 ORR	X0, XZR, X1

(436) 0x42c784 ORR	W1, WZR, W11

(436) 0x42c788 CBZ	X30, 42c680

(436) 0x42c78c SUB	W12, W20, W27

(436) 0x42c790 ORR	X28, XZR, X27

(436) 0x42c794 ANDS	X30, X12, #4160

(436) 0x42c798 B.EQ	42c7c0

(436) 0x42c79c LDR	X12, [SP, #24]

(436) 0x42c7a0 ORR	X28, XZR, X27

(436) 0x42c7a4 SUB	W3, W12, W27

  (438) 0x42c7a8 LDR	D0, [X7, X3,SXTW #3]

  (438) 0x42c7ac SUB	W3, W3, #1

  (438) 0x42c7b0 SUBS	X30, X30, #1

  (438) 0x42c7b4 STR	D0, [X26, X28,LSL #3]

  (438) 0x42c7b8 ADD	X28, X28, #1

  (438) 0x42c7bc B.NE	42c7a8

(436) 0x42c7c0 ORN	X12, XZR, X27

(436) 0x42c7c4 ADD	X12, X12, X20

(436) 0x42c7c8 CMP	X12, #3

(436) 0x42c7cc B.CC	42c680

0x42c7d0 MADD	X12, X13, X25, XZR

0x42c7d4 LDR	X14, [SP, #8]

0x42c7d8 SUB	X25, X20, X28

0x42c7dc SUB	W26, W24, W28

0x42c7e0 ADD	X12, X12, X28,LSL #3

0x42c7e4 ADD	X27, X14, X12

(437) 0x42c7e8 ADD	W12, W26, #1

(437) 0x42c7ec SUB	X25, X25, #4

(437) 0x42c7f0 LDR	D0, [X7, X12,SXTW #3]

(437) 0x42c7f4 SUB	W12, W26, #1

(437) 0x42c7f8 STUR	D0, [X27, #496]

(437) 0x42c7fc LDR	D0, [X7, X26,SXTW #3]

(437) 0x42c800 STUR	D0, [X27, #504]

(437) 0x42c804 LDR	D0, [X7, X12,SXTW #3]

(437) 0x42c808 SUB	W12, W26, #2

(437) 0x42c80c SUB	W26, W26, #4

(437) 0x42c810 STR	D0, [X27]

(437) 0x42c814 LDR	D0, [X7, X12,SXTW #3]

(437) 0x42c818 STR	D0, [X27, #8]

(437) 0x42c81c ADD	X27, X27, #32

(437) 0x42c820 CBNZ	X25, 42c7e8

0x42c824 B	42c680

0x42c828 HINT	#0

0x42c82c HINT	#0

0x436dc8 HINT	#0

0x436dcc HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:203-206
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:203-206

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 7.00 to 0.91 cycles (7.72x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 0.50 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	7.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

7% of peak load performance is reached (7.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
34% of peak store performance is reached (16.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42c500

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W21, W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W26, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42c5b0 <.omp_outlined..30+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <46354c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3768	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W26, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42c5d0 <.omp_outlined..30+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42c78c <.omp_outlined..30+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
MADD X12, X13, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X14, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X25, X20, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42c680 <.omp_outlined..30+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	update_halo.cpp:203-206
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:203-206

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 0.50 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	7.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

7% of peak load performance is reached (7.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
34% of peak store performance is reached (16.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42c500

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W21, W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W26, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42c5b0 <.omp_outlined..30+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <46354c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3768	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W26, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42c5d0 <.omp_outlined..30+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42c78c <.omp_outlined..30+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
MADD X12, X13, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X14, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X25, X20, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42c680 <.omp_outlined..30+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..30–	0.01	0
▼Loop 436 - update_halo.cpp:203-206 - exec–	0	0
○Loop 438 - update_halo.cpp:205-206 - exec	0.01	0
○Loop 435 - update_halo.cpp:205-206 - exec	0	0
○Loop 437 - update_halo.cpp:205-206 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code