OV - exec - Function .omp

	Function: .omp_outlined..28	Module: exec	Source: update_halo.cpp:193-196	Coverage: 0.02%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 193 - 196

--------------------------------------------------------------------------------

193: #pragma omp parallel for simd

194:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

195:         for (int j = 0; j < depth; ++j) {

196:           field.energy1(1 - j, k) = field.energy1(2 + j, k);

0x42c290 SUB	SP, SP, #128

0x42c294 STP	X29, X30, [SP, #32]

0x42c298 STP	X28, X27, [SP, #48]

0x42c29c STP	X26, X25, [SP, #64]

0x42c2a0 STP	X24, X23, [SP, #80]

0x42c2a4 STP	X22, X21, [SP, #96]

0x42c2a8 STP	X20, X19, [SP, #112]

0x42c2ac ADD	X29, SP, #32

0x42c2b0 LDR	W22, [X2]

0x42c2b4 LDR	W20, [X3]

0x42c2b8 LDR	W8, [X4]

0x42c2bc SUB	W9, W22, W20

0x42c2c0 ADD	W8, W8, W20

0x42c2c4 SUBS	W24, W8, W9

0x42c2c8 B.LT	42c340

0x42c2cc LDR	W19, [X0]

0x42c2d0 LDR	X23, [X5, #72]

0x42c2d4 LDR	X21, [X5, #88]

0x42c2d8 MOVZ	W8, #1

0x42c2dc ADRP	X0,

0x42c2e0 ADD	X0, X0, #3696

0x42c2e4 ADD	X3, SP, #16

0x42c2e8 SUB	X4, X29, #4

0x42c2ec STP	W24, WZR, [X29, #504]

0x42c2f0 SUB	X5, X29, #8

0x42c2f4 SUB	X6, X29, #12

0x42c2f8 MOVZ	W2, #34

0x42c2fc STUR	W8, [X29, #500]

0x42c300 STR	WZR, [SP, #16]

0x42c304 STR	W8, [SP]

0x42c308 MOVZ	W7, #1

0x42c30c ORR	W1, WZR, W19

0x42c310 BL	402dc0

0x42c314 LDP	W8, W9, [X29, #504]

0x42c318 CMP	W8, W24

0x42c31c CSEL	W8, W8, W24, #3

0x42c320 ADD	W10, W8, #1

0x42c324 CMP	W9, W10

0x42c328 CCMP	W20, #1, #8, #3

0x42c32c B.GE	42c360

(427) 0x42c330 ORR	W1, WZR, W19

(427) 0x42c334 ADRP	X0,

(427) 0x42c338 ADD	X0, X0, #3720

(427) 0x42c33c BL	403260

(427) 0x42c340 LDP	X20, X19, [SP, #112]

(427) 0x42c344 LDP	X22, X21, [SP, #96]

(427) 0x42c348 LDP	X24, X23, [SP, #80]

(427) 0x42c34c LDP	X26, X25, [SP, #64]

(427) 0x42c350 LDP	X28, X27, [SP, #48]

(427) 0x42c354 LDP	X29, X30, [SP, #32]

(427) 0x42c358 ADD	SP, SP, #128

(427) 0x42c35c RET

(427) 0x42c360 ADD	W15, W9, W22

(427) 0x42c364 CNTW	X11, ALL

(427) 0x42c368 SUB	X2, X20, #1

(427) 0x42c36c ADD	X14, X21, #16

(427) 0x42c370 MOVZ	W17, #12

(427) 0x42c374 RDVL	X4, #1

(427) 0x42c378 ORR	W10, WZR, WZR

(427) 0x42c37c ADD	X12, X21, #8

(427) 0x42c380 UBFM	X13, X23, #61, #60

(427) 0x42c384 RDVL	X18, #2

(427) 0x42c388 RDVL	X0, #62

(427) 0x42c38c ADD	X1, X21, #24

(427) 0x42c390 CMP	X11, #12

(427) 0x42c394 SUB	W16, W15, W20

(427) 0x42c398 SUB	X15, XZR, X2,LSL #3

(427) 0x42c39c UBFM	X2, X2, #61, #63

(427) 0x42c3a0 CSEL	X17, X11, X17, #8

(427) 0x42c3a4 ADDVL	X3, X14, #1

(427) 0x42c3a8 SUB	X4, X14, X4

(427) 0x42c3ac ADD	W16, W16, #1

(427) 0x42c3b0 ADDVL	X5, X14, #62

(427) 0x42c3b4 PTRUE	P0.B, ALL

(427) 0x42c3b8 ORR	W6, WZR, W16

(427) 0x42c3bc B	42c3d4

(427) 0x42c3c0 CMP	W9, W8

(427) 0x42c3c4 ADD	W9, W9, #1

(427) 0x42c3c8 ADD	W10, W10, #1

(427) 0x42c3cc ADD	W6, W6, #1

(427) 0x42c3d0 B.EQ	42c330

(427) 0x42c3d4 SBFM	X7, X6, #0, #31

(427) 0x42c3d8 CMP	X17, X20

(427) 0x42c3dc MADD	X7, X13, X7, XZR

(427) 0x42c3e0 B.HI	42c400

(427) 0x42c3e4 ADD	W22, W16, W10

(427) 0x42c3e8 SBFM	X22, X22, #0, #31

(427) 0x42c3ec MADD	X22, X13, X22, X12

(427) 0x42c3f0 ADD	X23, X22, X15

(427) 0x42c3f4 CMP	X23, X22

(427) 0x42c3f8 CCMP	X2, #0, #0, #9

(427) 0x42c3fc B.EQ	42c4a0

(427) 0x42c400 ORR	X22, XZR, XZR

(427) 0x42c404 SUB	W23, W20, W22

(427) 0x42c408 ANDS	X24, X23, #4160

(427) 0x42c40c ORR	X23, XZR, X22

(427) 0x42c410 B.EQ	42c438

(427) 0x42c414 SUB	X23, X7, X22,LSL #3

(427) 0x42c418 ADD	X25, X14, X7

(427) 0x42c41c ADD	X26, X12, X23

(427) 0x42c420 ORR	X23, XZR, X22

  (429) 0x42c424 LDR	D0, [X25, X23,LSL #3]

  (429) 0x42c428 ADD	X23, X23, #1

  (429) 0x42c42c SUBS	X24, X24, #1

  (429) 0x42c430 STR	D0, [X26], #504

  (429) 0x42c434 B.NE	42c424

(427) 0x42c438 ORN	X22, XZR, X22

(427) 0x42c43c ADD	X22, X22, X20

(427) 0x42c440 CMP	X22, #3

(427) 0x42c444 B.CC	42c3c0

(427) 0x42c448 UBFM	X24, X23, #61, #60

(427) 0x42c44c SUB	X23, X20, X23

(427) 0x42c450 SUB	X22, X7, X24

(427) 0x42c454 ADD	X7, X7, X24

(427) 0x42c458 ADD	X22, X21, X22

(427) 0x42c45c ADD	X7, X1, X7

  (428) 0x42c460 LDUR	D0, [X7, #504]

  (428) 0x42c464 SUBS	X23, X23, #4

  (428) 0x42c468 STR	D0, [X22, #8]

  (428) 0x42c46c LDR	D0, [X7]

  (428) 0x42c470 STR	D0, [X22]

  (428) 0x42c474 LDR	D0, [X7, #8]

  (428) 0x42c478 STUR	D0, [X22, #504]

  (428) 0x42c47c LDR	D0, [X7, #16]

  (428) 0x42c480 ADD	X7, X7, #32

  (428) 0x42c484 STUR	D0, [X22, #496]

  (428) 0x42c488 SUB	X22, X22, #32

  (428) 0x42c48c B.NE	42c460

(427) 0x42c490 B	42c3c0

0x42c494 HINT	#0

0x42c498 HINT	#0

0x42c49c HINT	#0

(427) 0x42c4a0 UDIV	X22, X20, X11

(427) 0x42c4a4 ORR	X25, XZR, X5

(427) 0x42c4a8 ORR	X26, XZR, X4

(427) 0x42c4ac ORR	X27, XZR, X3

(427) 0x42c4b0 ORR	X28, XZR, X14

(427) 0x42c4b4 UMSUBL	X23, W22, W11, X20

(427) 0x42c4b8 UMADDL	X22, W22, W11, XZR

(427) 0x42c4bc ORR	X24, XZR, X22

  (430) 0x42c4c0 LD1B	{Z0.B}, P0/Z, [X28, X7]

  (430) 0x42c4c4 LD1B	{Z1.B}, P0/Z, [X27, X7]

  (430) 0x42c4c8 ADD	X28, X28, X18

  (430) 0x42c4cc ADD	X27, X27, X18

  (430) 0x42c4d0 SUBS	X24, X24, X11

  (430) 0x42c4d4 REV	Z0.D, Z0.D

  (430) 0x42c4d8 ST1B	{Z0.B}, P0, [X26, X7]

  (430) 0x42c4dc REV	Z0.D, Z1.D

  (430) 0x42c4e0 ADD	X26, X26, X0

  (430) 0x42c4e4 ST1B	{Z0.B}, P0, [X25, X7]

  (430) 0x42c4e8 ADD	X25, X25, X0

  (430) 0x42c4ec B.NE	42c4c0

(427) 0x42c4f0 CBNZ	X23, 42c404

0x42c4f4 B	42c3c0

0x42c4f8 HINT	#0

0x42c4fc HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:193-196
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:193-196.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.67 to 0.71 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	46
loop length	184
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42c290

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42c340 <.omp_outlined..28+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4632dc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3696	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42c360 <.omp_outlined..28+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 42c3c0 <.omp_outlined..28+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	update_halo.cpp:193-196
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:193-196.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	46
loop length	184
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42c290

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42c340 <.omp_outlined..28+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4632dc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3696	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402dc0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42c360 <.omp_outlined..28+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 42c3c0 <.omp_outlined..28+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..28–	0.02	0.01
▼Loop 427 - update_halo.cpp:193-196 - exec–	0	0
○Loop 429 - update_halo.cpp:195-196 - exec	0.02	0.01
○Loop 430 - update_halo.cpp:195-196 - exec	0	0
○Loop 428 - update_halo.cpp:195-196 - exec	0	0

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Vectorization

Details

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code