OV - exec - Function .omp

	Function: .omp_outlined..16	Module: exec	Source: advec_mom.cpp:157-160 [...]	Coverage: 1.56%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

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69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 157 - 160

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157: #pragma omp parallel for simd collapse(2)

158:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

159:         for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

160:           node_flux(i, j) = 0.25 * (mass_flux_y(i - 1, j + 0) + mass_flux_y(i, j) + mass_flux_y(i - 1, j + 1) + mass_flux_y(i + 0, j + 1));

0x41db20 SUB	SP, SP, #144

0x41db24 STP	X29, X30, [SP, #48]

0x41db28 STP	X28, X27, [SP, #64]

0x41db2c STP	X26, X25, [SP, #80]

0x41db30 STP	X24, X23, [SP, #96]

0x41db34 STP	X22, X21, [SP, #112]

0x41db38 STP	X20, X19, [SP, #128]

0x41db3c ADD	X29, SP, #48

0x41db40 LDR	W8, [X3]

0x41db44 LDR	W20, [X2]

0x41db48 LDR	W21, [X4]

0x41db4c ADD	W8, W8, #4

0x41db50 LDR	W9, [X5]

0x41db54 ADD	W28, W21, #1

0x41db58 ADD	W9, W9, #3

0x41db5c CMP	W8, W20

0x41db60 CCMP	W9, W28, #4, #10

0x41db64 B.LE	41dd50

0x41db68 SUB	W26, W20, #1

0x41db6c SUB	W27, W9, W28

0x41db70 LDR	W1, [X0]

0x41db74 LDR	X22, [X6]

0x41db78 LDR	X23, [X6, #16]

0x41db7c MOVN	X9, #0

0x41db80 ADRP	X0,

0x41db84 ADD	X0, X0, #32

0x41db88 LDR	X24, [X7]

0x41db8c ADD	X3, SP, #20

0x41db90 SUB	W8, W8, W26

0x41db94 LDR	X25, [X7, #16]

0x41db98 SUB	X4, X29, #8

0x41db9c STP	W1, WZR, [SP, #16]

0x41dba0 UMADDL	X19, W27, W8, X9

0x41dba4 MOVZ	W8, #1

0x41dba8 SUB	X5, X29, #16

0x41dbac ADD	X6, SP, #24

0x41dbb0 MOVZ	W2, #34

0x41dbb4 MOVZ	W7, #1

0x41dbb8 STR	X8, [SP, #24]

0x41dbbc STR	X8, [SP]

0x41dbc0 STP	X19, XZR, [X29, #1008]

0x41dbc4 BL	4033a0

0x41dbc8 LDP	X8, X13, [X29, #1008]

0x41dbcc CMP	X8, X19

0x41dbd0 CSEL	X8, X8, X19, #11

0x41dbd4 CMP	X13, X8

0x41dbd8 B.GT	41dd40

0x41dbdc ADD	X8, X8, #1

0x41dbe0 CNTD	X10, ALL

0x41dbe4 ORR	X9, XZR, X13

0x41dbe8 SUB	X11, X8, X13

0x41dbec CMP	X11, X10

0x41dbf0 B.CC	41dcc4

0x41dbf4 UDIV	X9, X11, X10

0x41dbf8 PTRUE	P0.D, ALL

0x41dbfc FDUP	Z16.D, #80

0x41dc00 MADD	X12, X9, X10, XZR

0x41dc04 INDEX	Z0.D, X13, #1

0x41dc08 SUB	X11, X11, X12

0x41dc0c DUP	Z1.D, X10

0x41dc10 ADD	X9, X13, X12

0x41dc14 DUP	Z2.D, X27

0x41dc18 DUP	Z3.D, X26

0x41dc1c DUP	Z4.D, X28

0x41dc20 DUP	Z5.D, X21

0x41dc24 DUP	Z6.D, X24

0x41dc28 DUP	Z7.D, X20

0x41dc2c DUP	Z17.D, X22

0x41dc30 HINT	#0

0x41dc34 HINT	#0

0x41dc38 HINT	#0

0x41dc3c HINT	#0

(338) 0x41dc40 MOVPRFX	Z18, Z0

(338) 0x41dc44 SDIV	Z18.D, P0/M, Z18.D, Z2.D

(338) 0x41dc48 ADD	Z19.D, Z3.D, Z18.D

(338) 0x41dc4c MOVPRFX	Z20, Z0

(338) 0x41dc50 MLS	Z20.D, P0/M, Z18.D, Z2.D

(338) 0x41dc54 ADD	Z18.D, Z7.D, Z18.D

(338) 0x41dc58 SUBS	X12, X12, X10

(338) 0x41dc5c ADD	Z21.D, Z4.D, Z20.D

(338) 0x41dc60 ADD	Z20.D, Z5.D, Z20.D

(338) 0x41dc64 ADD	Z0.D, Z0.D, Z1.D

(338) 0x41dc68 SXTW	Z18.D, P0/M, Z18.D

(338) 0x41dc6c SXTW	Z19.D, P0/M, Z19.D

(338) 0x41dc70 MOVPRFX	Z22, Z6

(338) 0x41dc74 MUL	Z22.D, P0/M, Z22.D, Z19.D

(338) 0x41dc78 ADR	Z23.D, [Z22, Z20.D,SXTW]

(338) 0x41dc7c LD1D	{Z23.D}, P0/Z, [X25, Z23.D,LSL #3]

(338) 0x41dc80 MUL	Z18.D, P0/M, Z18.D, Z6.D

(338) 0x41dc84 ADR	Z22.D, [Z22, Z21.D,SXTW]

(338) 0x41dc88 LD1D	{Z22.D}, P0/Z, [X25, Z22.D,LSL #3]

(338) 0x41dc8c FADD	Z22.D, Z22.D, Z23.D

(338) 0x41dc90 MOVPRFX	Z23, Z21

(338) 0x41dc94 SXTW	Z23.D, P0/M, Z21.D

(338) 0x41dc98 ADR	Z20.D, [Z18, Z20.D,SXTW]

(338) 0x41dc9c ADR	Z18.D, [Z18, Z21.D,SXTW]

(338) 0x41dca0 MAD	Z19.D, P0/M, Z17.D, Z23.D

(338) 0x41dca4 LD1D	{Z20.D}, P0/Z, [X25, Z20.D,LSL #3]

(338) 0x41dca8 LD1D	{Z18.D}, P0/Z, [X25, Z18.D,LSL #3]

(338) 0x41dcac FADD	Z18.D, Z20.D, Z18.D

(338) 0x41dcb0 FADD	Z18.D, Z22.D, Z18.D

(338) 0x41dcb4 FMUL	Z18.D, Z18.D, Z16.D

(338) 0x41dcb8 ST1D	{Z18.D}, P0, [X23, Z19.D,LSL #3]

(338) 0x41dcbc B.NE	41dc40

0x41dcc0 CBZ	X11, 41dd40

0x41dcc4 SUB	W10, WZR, W27

0x41dcc8 FMOV	D0, #0.2500000

(337) 0x41dccc SDIV	X11, X9, X27

(337) 0x41dcd0 ADD	W13, W21, W9

(337) 0x41dcd4 ADD	X9, X9, #1

(337) 0x41dcd8 CMP	X8, X9

(337) 0x41dcdc ADD	W12, W26, W11

(337) 0x41dce0 MADD	W13, W10, W11, W13

(337) 0x41dce4 ADD	W11, W20, W11

(337) 0x41dce8 SBFM	X12, X12, #0, #31

(337) 0x41dcec ADD	W14, W13, #1

(337) 0x41dcf0 SBFM	X13, X13, #0, #31

(337) 0x41dcf4 SBFM	X11, X11, #0, #31

(337) 0x41dcf8 MADD	X15, X24, X12, XZR

(337) 0x41dcfc SBFM	X14, X14, #0, #31

(337) 0x41dd00 MADD	X11, X24, X11, XZR

(337) 0x41dd04 ADD	X16, X15, X13

(337) 0x41dd08 ADD	X15, X15, X14

(337) 0x41dd0c ADD	X13, X11, X13

(337) 0x41dd10 ADD	X11, X11, X14

(337) 0x41dd14 LDR	D1, [X25, X16,LSL #3]

(337) 0x41dd18 LDR	D2, [X25, X15,LSL #3]

(337) 0x41dd1c LDR	D3, [X25, X13,LSL #3]

(337) 0x41dd20 FADD	D1, D2, D1

(337) 0x41dd24 LDR	D2, [X25, X11,LSL #3]

(337) 0x41dd28 MADD	X11, X22, X12, X14

(337) 0x41dd2c FADD	D2, D3, D2

(337) 0x41dd30 FADD	D1, D1, D2

(337) 0x41dd34 FMUL	D1, D1, D0

(337) 0x41dd38 STR	D1, [X23, X11,LSL #3]

(337) 0x41dd3c B.NE	41dccc

0x41dd40 LDR	W1, [SP, #16]

0x41dd44 ADRP	X0,

0x41dd48 ADD	X0, X0, #56

0x41dd4c BL	403260

0x41dd50 LDP	X20, X19, [SP, #128]

0x41dd54 LDP	X22, X21, [SP, #112]

0x41dd58 LDP	X24, X23, [SP, #96]

0x41dd5c LDP	X26, X25, [SP, #80]

0x41dd60 LDP	X28, X27, [SP, #64]

0x41dd64 LDP	X29, X30, [SP, #48]

0x41dd68 ADD	SP, SP, #144

0x41dd6c RET

0x42b77c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	advec_mom.cpp:157-160
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:157-160

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.00 to 9.00 cycles (1.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 13.00 to 9.00 cycles (1.44x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.00 to 1.00 cycles (13.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 168 bytes. The binary function is storing 136 bytes.

General properties

nb instructions	88
loop length	352
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	11.75	11.75	13.00	11.50	1.00	1.00	0.50	0.50	9.00	9.00	9.00	5.00	5.00
cycles	3.50	3.50	11.75	11.75	13.00	11.50	1.00	1.00	0.50	0.50	9.00	9.00	9.00	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	10.38
Overall L1	13.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.00 cycles. At this rate:

13% of peak load performance is reached (12.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.46 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41db20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W21, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W28, W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W9, W28, #4, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LE 41dd50 <.omp_outlined..16+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W26, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W27, W9, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <463b80>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X24, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X25, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W1, WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UMADDL X19, W27, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X19, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X13, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X8, X8, X19, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 41dd40 <.omp_outlined..16+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X9, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X8, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 41dcc4 <.omp_outlined..16+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X9, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FDUP Z16.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
MADD X12, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
INDEX Z0.D, X13, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD X9, X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z2.D, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z3.D, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z4.D, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z5.D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z6.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z7.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z17.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
HINT #0
HINT #0
HINT #0
HINT #0
CBZ X11, 41dd40 <.omp_outlined..16+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W10, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR W1, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463d44>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	advec_mom.cpp:157-160
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:157-160

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.00 to 9.00 cycles (1.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.00 to 1.00 cycles (13.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 168 bytes. The binary function is storing 136 bytes.

General properties

nb instructions	88
loop length	352
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	11.75	11.75	13.00	11.50	1.00	1.00	0.50	0.50	9.00	9.00	9.00	5.00	5.00
cycles	3.50	3.50	11.75	11.75	13.00	11.50	1.00	1.00	0.50	0.50	9.00	9.00	9.00	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	10.38
Overall L1	13.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.00 cycles. At this rate:

13% of peak load performance is reached (12.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.46 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41db20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W21, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W28, W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W9, W28, #4, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LE 41dd50 <.omp_outlined..16+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W26, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W27, W9, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <463b80>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X24, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X25, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W1, WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UMADDL X19, W27, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X19, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X13, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X8, X8, X19, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 41dd40 <.omp_outlined..16+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X9, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X8, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 41dcc4 <.omp_outlined..16+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X9, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FDUP Z16.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
MADD X12, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
INDEX Z0.D, X13, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD X9, X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z2.D, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z3.D, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z4.D, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z5.D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z6.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z7.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z17.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
HINT #0
HINT #0
HINT #0
HINT #0
CBZ X11, 41dd40 <.omp_outlined..16+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W10, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR W1, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463d44>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..16–	1.56	0.84
○Loop 338 - advec_mom.cpp:158-160 - exec	1.56	0.84
○Loop 337 - advec_mom.cpp:158-160 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code