OV - exec - Function .omp

	Function: .omp_outlined..8	Module: exec	Source: advec_cell.cpp:136-140 [...]	Coverage: 1.12%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 136 - 140

--------------------------------------------------------------------------------

136: #pragma omp parallel for simd collapse(2)

137:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

138:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

139:           pre_vol(i, j) = volume(i, j) + (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j));

140:           post_vol(i, j) = pre_vol(i, j) - (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j));

0x41b310 SUB	SP, SP, #192

0x41b314 STP	X29, X30, [SP, #96]

0x41b318 STP	X28, X27, [SP, #112]

0x41b31c STP	X26, X25, [SP, #128]

0x41b320 STP	X24, X23, [SP, #144]

0x41b324 STP	X22, X21, [SP, #160]

0x41b328 STP	X20, X19, [SP, #176]

0x41b32c ADD	X29, SP, #96

0x41b330 LDR	W8, [X3]

0x41b334 LDR	W20, [X2]

0x41b338 LDR	W9, [X5]

0x41b33c ADD	W8, W8, #4

0x41b340 LDR	W14, [X4]

0x41b344 ADD	W9, W9, #4

0x41b348 CMP	W8, W20

0x41b34c CCMP	W9, W14, #8, #10

0x41b350 B.LT	41b5e0

0x41b354 LDP	X11, X10, [X29, #104]

0x41b358 LDR	X12, [X29, #96]

0x41b35c LDR	X13, [X6]

0x41b360 SUB	W23, W20, #1

0x41b364 SUB	X3, X29, #28

0x41b368 SUB	X4, X29, #8

0x41b36c SUB	X5, X29, #16

0x41b370 MOVZ	W2, #34

0x41b374 LDR	W1, [X0]

0x41b378 SUB	W8, W8, W23

0x41b37c LDR	X22, [X6, #16]

0x41b380 LDR	X24, [X7, #16]

0x41b384 ADRP	X0,

0x41b388 ADD	X0, X0, #3264

0x41b38c SUB	X6, X29, #24

0x41b390 LDR	X25, [X12]

0x41b394 LDR	X26, [X12, #16]

0x41b398 LDR	X12, [X11]

0x41b39c LDR	X28, [X11, #16]

0x41b3a0 LDR	X11, [X10]

0x41b3a4 LDR	X21, [X10, #16]

0x41b3a8 SUB	W10, W14, #1

0x41b3ac STUR	X13, [X29, #472]

0x41b3b0 LDR	X13, [X7]

0x41b3b4 MOVZ	W7, #1

0x41b3b8 SUB	W27, W9, W10

0x41b3bc MOVN	X9, #0

0x41b3c0 STR	X10, [SP, #16]

0x41b3c4 STP	W1, WZR, [X29, #480]

0x41b3c8 UMADDL	X19, W27, W8, X9

0x41b3cc MOVZ	W8, #1

0x41b3d0 STP	X12, X13, [SP, #40]

0x41b3d4 STP	X14, X11, [SP, #24]

0x41b3d8 STUR	X8, [X29, #488]

0x41b3dc STR	X8, [SP]

0x41b3e0 STP	X19, XZR, [X29, #1008]

0x41b3e4 BL	4033a0

0x41b3e8 LDP	X8, X13, [X29, #1008]

0x41b3ec CMP	X8, X19

0x41b3f0 CSEL	X8, X8, X19, #11

0x41b3f4 CMP	X13, X8

0x41b3f8 B.GT	41b5d0

0x41b3fc SUB	X9, X8, X13

0x41b400 CNTD	X10, ALL

0x41b404 ADD	X11, X9, #1

0x41b408 ORR	X9, XZR, X13

0x41b40c CMP	X11, X10

0x41b410 B.CC	41b52c

0x41b414 UDIV	X9, X11, X10

0x41b418 PTRUE	P0.D, ALL

0x41b41c MADD	X12, X9, X10, XZR

0x41b420 INDEX	Z0.D, X13, #1

0x41b424 ADD	X9, X13, X12

0x41b428 LDR	X13, [SP, #16]

0x41b42c DUP	Z1.D, X10

0x41b430 SUB	X11, X11, X12

0x41b434 DUP	Z2.D, X27

0x41b438 DUP	Z3.D, X23

0x41b43c DUP	Z6.D, X20

0x41b440 DUP	Z7.D, X25

0x41b444 DUP	Z4.D, X13

0x41b448 LDR	X13, [SP, #48]

0x41b44c DUP	Z5.D, X13

0x41b450 LDR	X13, [SP, #24]

0x41b454 DUP	Z16.D, X13

0x41b458 LDR	X13, [SP, #40]

0x41b45c DUP	Z17.D, X13

0x41b460 LDUR	X13, [X29, #472]

0x41b464 DUP	Z18.D, X13

0x41b468 LDR	X13, [SP, #32]

0x41b46c DUP	Z19.D, X13

0x41b470 HINT	#0

0x41b474 HINT	#0

0x41b478 HINT	#0

0x41b47c HINT	#0

(279) 0x41b480 MOVPRFX	Z20, Z0

(279) 0x41b484 SDIV	Z20.D, P0/M, Z20.D, Z2.D

(279) 0x41b488 ADD	Z21.D, Z3.D, Z20.D

(279) 0x41b48c MOVPRFX	Z22, Z0

(279) 0x41b490 MLS	Z22.D, P0/M, Z20.D, Z2.D

(279) 0x41b494 ADD	Z20.D, Z6.D, Z20.D

(279) 0x41b498 SUBS	X12, X12, X10

(279) 0x41b49c ADD	Z23.D, Z4.D, Z22.D

(279) 0x41b4a0 MOVPRFX	Z24, Z23

(279) 0x41b4a4 SXTW	Z24.D, P0/M, Z23.D

(279) 0x41b4a8 ADD	Z22.D, Z16.D, Z22.D

(279) 0x41b4ac ADD	Z0.D, Z0.D, Z1.D

(279) 0x41b4b0 SXTW	Z20.D, P0/M, Z20.D

(279) 0x41b4b4 SXTW	Z21.D, P0/M, Z21.D

(279) 0x41b4b8 MOVPRFX	Z25, Z24

(279) 0x41b4bc MLA	Z25.D, P0/M, Z5.D, Z21.D

(279) 0x41b4c0 LD1D	{Z25.D}, P0/Z, [X24, Z25.D,LSL #3]

(279) 0x41b4c4 MOVPRFX	Z28, Z17

(279) 0x41b4c8 MUL	Z28.D, P0/M, Z28.D, Z21.D

(279) 0x41b4cc MOVPRFX	Z27, Z24

(279) 0x41b4d0 MLA	Z27.D, P0/M, Z7.D, Z21.D

(279) 0x41b4d4 ADR	Z22.D, [Z28, Z22.D,SXTW]

(279) 0x41b4d8 ADR	Z23.D, [Z28, Z23.D,SXTW]

(279) 0x41b4dc MAD	Z20.D, P0/M, Z7.D, Z24.D

(279) 0x41b4e0 LD1D	{Z26.D}, P0/Z, [X26, Z20.D,LSL #3]

(279) 0x41b4e4 LD1D	{Z29.D}, P0/Z, [X26, Z27.D,LSL #3]

(279) 0x41b4e8 LD1D	{Z22.D}, P0/Z, [X28, Z22.D,LSL #3]

(279) 0x41b4ec LD1D	{Z23.D}, P0/Z, [X28, Z23.D,LSL #3]

(279) 0x41b4f0 FADD	Z25.D, Z26.D, Z25.D

(279) 0x41b4f4 FADD	Z23.D, Z29.D, Z23.D

(279) 0x41b4f8 FADD	Z22.D, Z25.D, Z22.D

(279) 0x41b4fc FSUB	Z22.D, Z22.D, Z23.D

(279) 0x41b500 MOVPRFX	Z23, Z24

(279) 0x41b504 MLA	Z23.D, P0/M, Z18.D, Z21.D

(279) 0x41b508 MAD	Z21.D, P0/M, Z19.D, Z24.D

(279) 0x41b50c ST1D	{Z22.D}, P0, [X22, Z23.D,LSL #3]

(279) 0x41b510 LD1D	{Z20.D}, P0/Z, [X26, Z20.D,LSL #3]

(279) 0x41b514 LD1D	{Z23.D}, P0/Z, [X26, Z27.D,LSL #3]

(279) 0x41b518 FSUB	Z20.D, Z22.D, Z20.D

(279) 0x41b51c FADD	Z20.D, Z20.D, Z23.D

(279) 0x41b520 ST1D	{Z20.D}, P0, [X21, Z21.D,LSL #3]

(279) 0x41b524 B.NE	41b480

0x41b528 CBZ	X11, 41b5d0

0x41b52c LDP	X12, X2, [SP, #24]

0x41b530 LDUR	X18, [X29, #472]

0x41b534 LDP	X1, X0, [SP, #40]

0x41b538 SUB	X10, X9, #1

0x41b53c SUB	W11, WZR, W27

0x41b540 ADD	W9, W12, W9

(278) 0x41b544 ADD	X10, X10, #1

(278) 0x41b548 SDIV	X12, X10, X27

(278) 0x41b54c CMP	X8, X10

(278) 0x41b550 ADD	W13, W23, W12

(278) 0x41b554 MADD	W14, W11, W12, W9

(278) 0x41b558 ADD	W12, W20, W12

(278) 0x41b55c ADD	W9, W9, #1

(278) 0x41b560 SBFM	X13, X13, #0, #31

(278) 0x41b564 SUB	W15, W14, #1

(278) 0x41b568 SBFM	X12, X12, #0, #31

(278) 0x41b56c MADD	X17, X1, X13, XZR

(278) 0x41b570 SBFM	X15, X15, #0, #31

(278) 0x41b574 MADD	X16, X0, X13, X15

(278) 0x41b578 MADD	X12, X25, X12, X15

(278) 0x41b57c ADD	X14, X17, W14,SXTW

(278) 0x41b580 LDR	D0, [X24, X16,LSL #3]

(278) 0x41b584 LDR	D1, [X26, X12,LSL #3]

(278) 0x41b588 MADD	X16, X25, X13, X15

(278) 0x41b58c LDR	D3, [X28, X14,LSL #3]

(278) 0x41b590 ADD	X14, X17, X15

(278) 0x41b594 LDR	D2, [X26, X16,LSL #3]

(278) 0x41b598 LDR	D4, [X28, X14,LSL #3]

(278) 0x41b59c MADD	X14, X18, X13, X15

(278) 0x41b5a0 FADD	D0, D1, D0

(278) 0x41b5a4 FADD	D0, D0, D3

(278) 0x41b5a8 FADD	D1, D2, D4

(278) 0x41b5ac FSUB	D0, D0, S1

(278) 0x41b5b0 STR	D0, [X22, X14,LSL #3]

(278) 0x41b5b4 LDR	D1, [X26, X12,LSL #3]

(278) 0x41b5b8 LDR	D2, [X26, X16,LSL #3]

(278) 0x41b5bc MADD	X12, X2, X13, X15

(278) 0x41b5c0 FSUB	D0, D0, S1

(278) 0x41b5c4 FADD	D0, D0, D2

(278) 0x41b5c8 STR	D0, [X21, X12,LSL #3]

(278) 0x41b5cc B.NE	41b544

0x41b5d0 LDUR	W1, [X29, #480]

0x41b5d4 ADRP	X0,

0x41b5d8 ADD	X0, X0, #3288

0x41b5dc BL	403260

0x41b5e0 LDP	X20, X19, [SP, #176]

0x41b5e4 LDP	X22, X21, [SP, #160]

0x41b5e8 LDP	X24, X23, [SP, #144]

0x41b5ec LDP	X26, X25, [SP, #128]

0x41b5f0 LDP	X28, X27, [SP, #112]

0x41b5f4 LDP	X29, X30, [SP, #96]

0x41b5f8 ADD	SP, SP, #192

0x41b5fc RET

0x42ae1c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	advec_cell.cpp:136-140
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:136-140

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.00 to 12.00 cycles (1.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.00 to 1.00 cycles (16.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 328 bytes. The binary function is storing 184 bytes.

General properties

nb instructions	112
loop length	448
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	12.50	12.25	16.00	12.25	1.00	0.00	0.00	0.00	16.00	16.00	16.00	7.00	7.00
cycles	3.50	3.50	12.50	12.25	16.00	12.25	1.00	0.00	0.00	0.00	16.00	16.00	16.00	7.00	7.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	13.38
Overall L1	16.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.00 cycles. At this rate:

21% of peak load performance is reached (20.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
23% of peak store performance is reached (11.50 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41b310

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W14, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W9, W9, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W9, W14, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LT 41b5e0 <.omp_outlined..8+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X12, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W23, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W8, W8, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X22, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <462384>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3264	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X25, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W10, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X13, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W27, W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W1, WZR, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UMADDL X19, W27, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X12, X13, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X14, X11, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X19, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X13, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X8, X8, X19, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 41b5d0 <.omp_outlined..8+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X9, X8, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 41b52c <.omp_outlined..8+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X9, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
INDEX Z0.D, X13, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
ADD X9, X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z1.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z2.D, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z3.D, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z6.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z7.D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z4.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z5.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z16.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z17.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDUR X13, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z18.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z19.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
HINT #0
HINT #0
HINT #0
HINT #0
CBZ X11, 41b5d0 <.omp_outlined..8+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X12, X2, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDUR X18, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X1, X0, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X10, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W11, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR W1, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4625d4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	advec_cell.cpp:136-140
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:136-140

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.00 to 1.00 cycles (16.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 328 bytes. The binary function is storing 184 bytes.

General properties

nb instructions	112
loop length	448
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	12.50	12.25	16.00	12.25	1.00	0.00	0.00	0.00	16.00	16.00	16.00	7.00	7.00
cycles	3.50	3.50	12.50	12.25	16.00	12.25	1.00	0.00	0.00	0.00	16.00	16.00	16.00	7.00	7.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	13.38
Overall L1	16.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.00 cycles. At this rate:

21% of peak load performance is reached (20.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
23% of peak store performance is reached (11.50 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41b310

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W14, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W9, W9, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W9, W14, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LT 41b5e0 <.omp_outlined..8+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X12, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W23, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W8, W8, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X22, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <462384>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3264	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X25, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W10, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X13, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W27, W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W1, WZR, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UMADDL X19, W27, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X12, X13, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X14, X11, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X19, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4033a0 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X13, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X8, X8, X19, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 41b5d0 <.omp_outlined..8+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X9, X8, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 41b52c <.omp_outlined..8+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X9, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
INDEX Z0.D, X13, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
ADD X9, X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z1.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z2.D, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z3.D, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z6.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z7.D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z4.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z5.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z16.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z17.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDUR X13, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z18.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X13, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z19.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
HINT #0
HINT #0
HINT #0
HINT #0
CBZ X11, 41b5d0 <.omp_outlined..8+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X12, X2, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDUR X18, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X1, X0, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X10, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W11, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR W1, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4625d4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 403260 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..8–	1.12	0.6
○Loop 279 - advec_cell.cpp:137-140 - exec	1.12	0.6
○Loop 278 - advec_cell.cpp:137-140 - exec	0	0

Report Configuration

Code clean check

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Vectorization

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code