	*************************************************
	*                                               *
	*          ONE-View report generation           *
	*                                               *
	*************************************************

[MAQAO] Info: Experiment configuration summary is available adding -dbg=1 in command line

* [MAQAO] Warning: Experiment directory /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/run/oneview_runs/compilers/aocc_7/oneview_results_1786619102 already exists and is reused.
           It can be replaced using --replace in the command line.
[MAQAO] Info: 
[MAQAO] Info: START THE APPLICATION PROFILING
[MAQAO] Info: -> RUNNING THE PROFILER...
[MAQAO] Info:   LPROF has already been run
[MAQAO] Info: STOP THE APPLICATION PROFILING
[MAQAO] Info: 
[MAQAO] Info: START FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: STOP FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: 
[MAQAO] Info: START THE REPORT GENERATION
[MAQAO] Info: -> ONE-VIEW EXPERIMENT DIRECTORY: /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/run/oneview_runs/compilers/aocc_7/oneview_results_1786619102


+====================================================================================================================+
+                                                    1  -  GLOBAL                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             1.1  -  Experiment Summary                                             +
+--------------------------------------------------------------------------------------------------------------------+

  Application:			/beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/run/binaries/aocc_7/exec
  Timestamp:			2026-08-13 13:05:02
  Universal Timestamp:		1786619102
  Experiment Type:		MPI; OpenMP; Throughput; 
  Machine:			isix07.benchmarkcenter.megware.com
  Architecture:			x86_64
  Micro Architecture:		GRANITE_RAPIDS
  Model Name:			Intel(R) Xeon(R) 6972P
  Cache Size:			491520 KB
  Number of Cores:		96
  OS Version:			Linux 5.14.0-687.31.1.el9_8.x86_64 #1 SMP PREEMPT_DYNAMIC Sat Aug 1 05:38:01 EDT 2026
  Compilation Options:		
		exec: AMD clang version 17.0.6 (CLANG: AOCC_5.1.0-Build#1994 2025_12_23) /cluster/comp/aocc/5.1.0/bin/clang-17 --driver-mode=g++ -D USE_OMP -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/omp -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/aocc_7/generated -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/driver -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp -O2 -march=graniterapids -mprefer-vector-width=512 -ffast-math -g -fno-omit-frame-pointer -fcf-protection=none -nopie -grecord-command-line -D NDEBUG -std=c++17 -Wall -Wno-unused-parameter -Wno-unused-function -Wno-unused-variable -fopenmp=libomp -MD -MT CMakeFiles/cloverleaf.dir/src/omp/advec_mom.cpp.o -MF CMakeFiles/cloverleaf.dir/src/omp/advec_mom.cpp.o.d -o CMakeFiles/cloverleaf.dir/src/omp/advec_mom.cpp.o -c /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp -I /cluster/hpcx/2.23/ompi5-aocc-mt/include -I /cluster/hpcx/2.23/ompi5-aocc-mt/include/openmpi 
  Number of processes observed:	6
  Number of threads observed:	192
  MAQAO version:		2026.1.0
  MAQAO build:			6d1be1d51c1e63266254997eb301734a7264775d::20260810-150026




+--------------------------------------------------------------------------------------------------------------------+
+                                               1.2  -  Global Metrics                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Total Time:				40.25 s
  Max (Thread Active Time):		39.72 s
  Average Active Time:			39.44 s
  Activity Ratio:			99.9 %
  Average number of active threads:	188.113
  Affinity Stability:			99.8 %
  Time spent in analyzed loops:		94.3 %
  Time spent in analyzed innermost loops: 94.3 %
  Time spent in user code:		94.3 %
  Compilation Options Score:		100
  Array Access Efficiency:		8.15 %

   Potential Speedups
  ----------------------------------------------------
  Perfect Flow Complexity:		1.00
  Perfect OpenMP/MPI/Pthread/TBB:	1.04
  Perfect OpenMP/MPI/Pthread/TBB + Load Distribution:	1.06
  If No Scalar Integer:
      Potential Speedup:		1.64
      Nb Loops to get 80%:		23
  If FP Vectorized:
      Potential Speedup:		1.00
      Nb Loops to get 80%:		1
  If Fully Vectorized:
      Potential Speedup:		1.43
      Nb Loops to get 80%:		22
  If Only FP Arithmetic:
      Potential Speedup:		4.12
      Nb Loops to get 80%:		27




+--------------------------------------------------------------------------------------------------------------------+
+                                             1.3  -  Potential Speedups                                             +
+--------------------------------------------------------------------------------------------------------------------+

  If No Scalar Integer:
      Number of loops   | 1      | 10     | 20     | 29     | 40     | 
      Cumulated Speedup | 1.0363 | 1.2571 | 1.4747 | 1.6210 | 1.6403 | 
  Top 5 loops:
    exec - 229:	1.0363
    exec - 166:	1.0621
    exec - 167:	1.089
    exec - 175:	1.1169
    exec - 174:	1.1462

  If FP Vectorized:
      Number of loops   | 1      | 10     | 20     | 29     | 40     | 
      Cumulated Speedup | 1.0000 | 1.0000 | 1.0000 | 1.0000 | 1.0000 | 
  Top 5 loops:
    exec - 293:	1
    exec - 146:	1
    exec - 162:	1
    exec - 170:	1
    exec - 148:	1

  If Fully Vectorized:
      Number of loops   | 1      | 10     | 20     | 29     | 40     | 
      Cumulated Speedup | 1.0194 | 1.1677 | 1.3248 | 1.4216 | 1.4299 | 
  Top 5 loops:
    exec - 229:	1.0194
    exec - 175:	1.0372
    exec - 167:	1.0554
    exec - 153:	1.0711
    exec - 156:	1.0868

  If Only FP Arithmetic:
      Number of loops   | 1      | 10     | 20     | 29     | 40     | 
      Cumulated Speedup | 1.0491 | 1.5558 | 2.5580 | 3.8766 | 4.1168 | 
  Top 5 loops:
    exec - 293:	1.0491
    exec - 135:	1.1017
    exec - 229:	1.15
    exec - 291:	1.2018
    exec - 220:	1.2582



+====================================================================================================================+
+                                                   2  -  SUMMARY                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             2.1  -  EXPERIMENT QUALITY                                             +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Application profile is long enough (39.72 s)
To have good quality measurements, it is advised that the application profiling time is greater than 10 seconds.

  [3 / 3] Most of time spent in analyzed modules comes from functions with source/debug info
-g option gives access to debugging informations, such are source locations.

  [2.9981036701489 / 3] Most of time spent in analyzed modules (99.94%) comes from functions compiled with architecture specialization option
-march=graniterapids


  [3 / 3] Most of time spent in analyzed modules comes from functions with compilation options informations and
-fno-omit-frame-pointer is present
-fno-omit-frame-pointer improves the accuracy of callchains found during the application profiling.

  [3 / 3] Optimization level option is correctly used


  [3 / 3] Host configuration allows retrieval of all necessary metrics.


  [2 / 2] Application is correctly profiled ("Others" category represents 0.01 % of the execution time)
To have a representative profiling, it is advised that the category "Others" represents less than 20% of the execution
time in order to analyze as much as possible of the user code

  [1 / 1] Lstopo present. The Topology lstopo report will be generated.



+--------------------------------------------------------------------------------------------------------------------+
+                                                2.2  -  CODE QUALITY                                                +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Enough time of the experiment time spent in analyzed loops (94.33%)
If the time spent in analyzed loops is less than 30%, standard loop optimizations will have a limited impact on
application performances.

  [4 / 4] Threads activity is good
On average, more than 97.98% of observed threads are actually active 

  [4 / 4] CPU activity is good
CPU cores are active 99.86% of time

  [4 / 4] Loop profile is not flat
At least one loop coverage is greater than 4% (6.18%), representing an hotspot for the application

  [4 / 4] Enough time of the experiment time spent in analyzed innermost loops (94.33%)
If the time spent in analyzed innermost loops is less than 15%, standard innermost loop optimizations such as
vectorisation will have a limited impact on application performances.

  [4 / 4] Affinity is good (99.85%)
Threads are not migrating to CPU cores: probably successfully pinned

  [3 / 3] Less than 10% (0.00%) is spend in BLAS1 operations
It could be more efficient to inline by hand BLAS1 operations

  [3 / 3] Functions mostly use all threads
Functions running on a reduced number of threads (typically sequential code) cover less than 10% of application
walltime (3.83%)

  [3 / 3] Cumulative Outermost/In between loops coverage (0.01%) lower than cumulative innermost loop coverage (94.33%)
Having cumulative Outermost/In between loops coverage greater than cumulative innermost loop coverage will make loop
optimization more complex

  [2 / 2] Less than 10% (0.00%) is spend in BLAS2 operations
BLAS2 calls usually could make a poor cache usage and could benefit from inlining.

  [2 / 2] Less than 10% (0.00%) is spend in Libm/SVML (special functions)



+--------------------------------------------------------------------------------------------------------------------+
+                                               2.3  -  LOOPS OVERVIEW                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Top 5 loops:
   + exec - 293 :
     analysis: Execution Time: 6 % - Vectorization Ratio: 75.69 % - Vector Length Use: 63.02 %
     Loop Computation Issues: 10
        [8] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 2
            issues (= instructions) costing 4 points each.
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Data Access Issues: 188
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
        [52] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 13 issues ( = indirect data accesses) costing 4 point each.
        [112] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 28 issues (=
            instructions) costing 4 points each.
        [20] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 20 issues (= instructions) costing 1
            point each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 54
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
        [52] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 13 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 132
        [112] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 28 issues (=
            instructions) costing 4 points each.
        [20] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 20 issues (= instructions) costing 1
            point each.

   + exec - 229 :
     analysis: Execution Time: 5 % - Vectorization Ratio: 49.43 % - Vector Length Use: 42.53 %
     Loop Computation Issues: 14
        [8] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 2
            issues (= instructions) costing 4 points each.
        [4] [SA] Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA - Reorganize
            arithmetic expressions to exhibit potential for FMA. This issue costs 4 points.
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Data Access Issues: 55
        [16] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 4 issues ( = indirect data accesses) costing 4 point each.
        [20] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 5 issues (=
            instructions) costing 4 points each.
        [19] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE) - Simplify
            data access and try to get stride 1 access. There are 19 issues (= instructions) costing 1 point each.
     Vectorization Roadblocks: 16
        [16] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 4 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 39
        [20] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 5 issues (=
            instructions) costing 4 points each.
        [19] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE) - Simplify
            data access and try to get stride 1 access. There are 19 issues (= instructions) costing 1 point each.

   + exec - 291 :
     analysis: Execution Time: 5 % - Vectorization Ratio: 69.36 % - Vector Length Use: 57.15 %
     Loop Computation Issues: 10
        [8] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 2
            issues (= instructions) costing 4 points each.
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Data Access Issues: 148
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
        [44] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 11 issues ( = indirect data accesses) costing 4 point each.
        [80] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 20 issues (=
            instructions) costing 4 points each.
        [20] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 20 issues (= instructions) costing 1
            point each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 46
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
        [44] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 11 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 100
        [80] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 20 issues (=
            instructions) costing 4 points each.
        [20] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 20 issues (= instructions) costing 1
            point each.

   + exec - 135 :
     analysis: Execution Time: 5 % - Vectorization Ratio: 77.09 % - Vector Length Use: 60.13 %
     Loop Computation Issues: 6
        [4] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 1
            issues (= instructions) costing 4 points each.
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Data Access Issues: 224
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
        [40] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 10 issues ( = indirect data accesses) costing 4 point each.
        [160] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 40 issues (=
            instructions) costing 4 points each.
        [20] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 20 issues (= instructions) costing 1
            point each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 42
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
        [40] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 10 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 180
        [160] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 40 issues (=
            instructions) costing 4 points each.
        [20] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 20 issues (= instructions) costing 1
            point each.

   + exec - 174 :
     analysis: Execution Time: 4 % - Vectorization Ratio: 64.73 % - Vector Length Use: 54.89 %
     Loop Computation Issues: 26
        [24] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 6
            issues (= instructions) costing 4 points each.
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Data Access Issues: 123
        [20] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 5 issues ( = indirect data accesses) costing 4 point each.
        [64] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 16 issues (=
            instructions) costing 4 points each.
        [37] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE) - Simplify
            data access and try to get stride 1 access. There are 37 issues (= instructions) costing 1 point each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 20
        [20] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 5 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 103
        [64] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 16 issues (=
            instructions) costing 4 points each.
        [37] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE) - Simplify
            data access and try to get stride 1 access. There are 37 issues (= instructions) costing 1 point each.
        [2] [SA] Inefficient vectorization: use of masked instructions - Simplify control structure. The issue costs 2
            points.



+====================================================================================================================+
+                                                 3  -  APPLICATION                                                  +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                               3.1  -  Categorization                                               +
+--------------------------------------------------------------------------------------------------------------------+

   Category | IO     | Exe    | System  | Others  | Memory | String | MPI   | TBB   | OMP   | Pthread | Math  |
  ----------+--------+--------+---------+---------+--------+--------+-------+-------+-------+---------+-------+
   Time (%) | 0.00   | 94.34  | 0.36    | 0.01    | 0.00   | 0.01   | 0.02  | 0.00  | 5.27  | 0.00    | 0.00  |




+--------------------------------------------------------------------------------------------------------------------+
+                                          3.2  -  Function Based Profiling                                          +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Functions              | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 0                         | 0.00                      | 0.00                      |
   4% to 8%                   | 8                         | 38.25                     | 38.25                     |
   2% to 4%                   | 17                        | 51.22                     | 89.47                     |
   1% to 2%                   | 6                         | 8.01                      | 97.47                     |
   0.5% to 1%                 | 1                         | 0.97                      | 98.45                     |
   0.25% to 0.5%              | 3                         | 1.05                      | 99.50                     |
   0.125% to 0.25%            | 0                         | 0.00                      | 99.50                     |
   < 0.125%                   | 158                       | 0.50                      | 100.00                    |




+--------------------------------------------------------------------------------------------------------------------+
+                                            3.3  -  Loop Based Profiling                                            +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Loops                  | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 0                         | 0.00                      | 0.00                      |
   4% to 8%                   | 8                         | 38.25                     | 38.25                     |
   2% to 4%                   | 16                        | 47.38                     | 85.64                     |
   1% to 2%                   | 6                         | 8.01                      | 93.64                     |
   0.5% to 1%                 | 0                         | 0.00                      | 93.64                     |
   0.25% to 0.5%              | 1                         | 0.27                      | 93.91                     |
   0.125% to 0.25%            | 0                         | 0.00                      | 93.91                     |
   < 0.125%                   | 77                        | 0.42                      | 94.33                     |


+====================================================================================================================+
+                                                  4  -  FUNCTIONS                                                   +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                              4.1  -  Top 10 Functions                                              +
+--------------------------------------------------------------------------------------------------------------------+

   Function                                               | Module              | Coverage (%)   | Time (s)       |
  --------------------------------------------------------+---------------------+----------------+----------------+
   PdV_kernel(bool, int, int, int, int, double, clover... | exec                | 6.18           | 2.44           |
   ideal_gas_kernel(int, int, int, int, clover::Buffer... | exec                | 5.43           | 2.14           |
   PdV_kernel(bool, int, int, int, int, double, clover... | exec                | 5.25           | 2.07           |
   accelerate_kernel(int, int, int, int, double, clove... | exec                | 5.11           | 2.01           |
   advec_mom_kernel(int, int, int, int, clover::Buffer... | exec                | 4.13           | 1.63           |
   advec_mom_kernel(int, int, int, int, clover::Buffer... | exec                | 4.07           | 1.61           |
   advec_mom_kernel(int, int, int, int, clover::Buffer... | exec                | 4.04           | 1.59           |
   flux_calc_kernel(int, int, int, int, double, clover... | exec                | 4.03           | 1.59           |
   advec_mom_kernel(int, int, int, int, clover::Buffer... | exec                | 3.99           | 1.57           |
   __kmp_hyper_barrier_release(barrier_type, kmp_info*... | libomp.so           | 3.83           | 1.51           |


+====================================================================================================================+
+                                                    5  -  LOOPS                                                     +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                5.1  -  Top 10 Loops                                                +
+--------------------------------------------------------------------------------------------------------------------+

   Loop Id        | Module              | Source Location                                        | Coverage (%)   |
  ----------------+---------------------+--------------------------------------------------------+----------------+
   293            | exec                | context.h:69-69,PdV.cpp:70-83                          | 6.18           |
   229            | exec                | ideal_gas.cpp:38-45,context.h:69-69                    | 5.43           |
   291            | exec                | context.h:69-69,PdV.cpp:49-63                          | 5.25           |
   135            | exec                | accelerate.cpp:41-53,context.h:69-69                   | 5.11           |
   174            | exec                | context.h:69-69,advec_mom.cpp:181-186,advec_mom.cpp... | 4.13           |
   166            | exec                | context.h:69-69,advec_mom.cpp:109-114,advec_mom.cpp... | 4.07           |
   175            | exec                | context.h:69-69,advec_mom.cpp:219-221                  | 4.04           |
   220            | exec                | flux_calc.cpp:37-40,context.h:69-69                    | 4.03           |
   167            | exec                | context.h:69-69,advec_mom.cpp:147-149                  | 3.99           |
   142            | exec                | context.h:69-69,advec_cell.cpp:66-110                  | 3.39           |





+====================================================================================================================+
+                                                     6  -  CQA                                                      +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                   6.1  -  Loops                                                    +
+--------------------------------------------------------------------------------------------------------------------+





      6.1.1  -  Loop 293 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70-83


It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.1.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

Warnings:
The number of fused uops of the instruction [VPCMPEQD	%YMM5,%YMM5,%YMM5] is unknown
5% of peak computational performance is used (1.71 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 131.50 to 117.50 cycles (1.12x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.1.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 63% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 131.50 to 125.12 cycles (1.05x speedup).

Details
75% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 95% of SSE/AVX loads are used in vector version.
 - 96% of SSE/AVX multiply instructions are used in vector version.
 - 20% of SSE/AVX divide and square root instructions are used in vector version.
 - 62% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.1.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).


Workaround
Reduce the number of FP multiply/FMA instructions




      6.1.1.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 24 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.02x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.1.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 8 occurrences<<list_path_1_complex_1>>
 - KMOVW: 1 occurrences<<list_path_1_complex_2>>
 - VDIVPD: 2 occurrences<<list_path_1_complex_3>>
 - VGATHERQPD: 26 occurrences<<list_path_1_complex_4>>
 - VPEXTRQ: 8 occurrences<<list_path_1_complex_5>>
 - VPMULLQ: 19 occurrences<<list_path_1_complex_6>>
 - VSCATTERQPD: 2 occurrences<<list_path_1_complex_7>>



      6.1.1.1.6  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 1 occurrence(s)
 - Irregular (variable stride) or indirect: 13 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.1.1.7  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses). By removing them, you can lower the cost of an iteration from 131.50 to 112.00 cycles (1.17x speedup).

Details
 - VGATHERQPD: 26 occurrences<<list_path_1_gather_scatter_1>>
 - VSCATTERQPD: 2 occurrences<<list_path_1_gather_scatter_2>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.1.1.8  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 8 occurrences<<list_path_1_cvt_1>>
 - VPMOVQD: 2 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.1.1.9  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
25 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.1.1.10  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 225 FP arithmetical operations:
 - 144: addition or subtraction (24 inside FMA instructions)
 - 65: multiply (24 inside FMA instructions)
 - 16: divide
The binary loop is loading 2714 bytes (339 double precision FP elements).
The binary loop is storing 130 bytes (16 double precision FP elements).


      6.1.1.1.11  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.2  -  Loop 229 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38-45
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69


It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.2.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

1% of peak computational performance is used (0.49 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.2.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 114.00 to 40.50 cycles (2.81x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.2.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 42% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 114.00 to 74.00 cycles (1.54x speedup).

Details
49% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 20% of SSE/AVX divide and square root instructions are used in vector version.
 - 36% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.2.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 114.00 to 46.00 cycles (2.48x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.2.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 114.00 to 40.00 cycles (2.85x speedup).




      6.1.2.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 8 occurrences<<list_path_1_complex_1>>
 - VDIVPD: 1 occurrences<<list_path_1_complex_2>>
 - VGATHERQPD: 3 occurrences<<list_path_1_complex_3>>
 - VPEXTRQ: 8 occurrences<<list_path_1_complex_4>>
 - VPMULLQ: 5 occurrences<<list_path_1_complex_5>>
 - VSCATTERQPD: 2 occurrences<<list_path_1_complex_6>>
 - VSQRTPD: 1 occurrences<<list_path_1_complex_7>>



      6.1.2.1.6  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 4 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.2.1.7  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses).

Details
 - VGATHERQPD: 3 occurrences<<list_path_1_gather_scatter_1>>
 - VSCATTERQPD: 2 occurrences<<list_path_1_gather_scatter_2>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.2.1.8  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 8 occurrences<<list_path_1_cvt_1>>
 - VPMOVQD: 2 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.2.1.9  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

7 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.2.1.10  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 56 FP arithmetical operations:
 - 40: multiply
 - 8: divide
 - 8: square root
The binary loop is loading 192 bytes (24 double precision FP elements).
The binary loop is storing 128 bytes (16 double precision FP elements).


      6.1.2.1.11  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.







      6.1.3  -  Loop 291 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49-63


It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.3.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

4% of peak computational performance is used (1.44 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.3.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 112.00 to 91.50 cycles (1.22x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.3.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 57% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 112.00 to 95.12 cycles (1.18x speedup).

Details
69% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 92% of SSE/AVX loads are used in vector version.
 - 95% of SSE/AVX multiply instructions are used in vector version.
 - 20% of SSE/AVX divide and square root instructions are used in vector version.
 - 56% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.3.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 112.00 to 101.50 cycles (1.10x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.3.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 112.00 to 98.50 cycles (1.14x speedup).


      6.1.3.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 24 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.3.1.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 8 occurrences<<list_path_1_complex_1>>
 - VDIVPD: 2 occurrences<<list_path_1_complex_2>>
 - VGATHERQPD: 18 occurrences<<list_path_1_complex_3>>
 - VPEXTRQ: 8 occurrences<<list_path_1_complex_4>>
 - VPMULLQ: 15 occurrences<<list_path_1_complex_5>>
 - VSCATTERQPD: 2 occurrences<<list_path_1_complex_6>>



      6.1.3.1.7  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 1 occurrence(s)
 - Irregular (variable stride) or indirect: 11 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.3.1.8  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses).

Details
 - VGATHERQPD: 18 occurrences<<list_path_1_gather_scatter_1>>
 - VSCATTERQPD: 2 occurrences<<list_path_1_gather_scatter_2>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.3.1.9  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 8 occurrences<<list_path_1_cvt_1>>
 - VPMOVQD: 2 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.3.1.10  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
17 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.3.1.11  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 161 FP arithmetical operations:
 - 80: addition or subtraction (24 inside FMA instructions)
 - 65: multiply (24 inside FMA instructions)
 - 16: divide
The binary loop is loading 1600 bytes (200 double precision FP elements).
The binary loop is storing 128 bytes (16 double precision FP elements).


      6.1.3.1.12  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.







      6.1.4  -  Loop 135 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41-53
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69


It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.4.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

6% of peak computational performance is used (2.01 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.4.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 147.50 to 127.50 cycles (1.16x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.4.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 60% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 147.50 to 141.50 cycles (1.04x speedup).

Details
77% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 97% of SSE/AVX loads are used in vector version.
 - 11% of SSE/AVX divide and square root instructions are used in vector version.
 - 68% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.4.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 147.50 to 100.67 cycles (1.47x speedup).


Workaround
Reduce the number of FP multiply/FMA instructions




      6.1.4.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 88 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.02x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.4.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 8 occurrences<<list_path_1_complex_1>>
 - VDIVPD: 1 occurrences<<list_path_1_complex_2>>
 - VGATHERQPD: 36 occurrences<<list_path_1_complex_3>>
 - VPEXTRQ: 8 occurrences<<list_path_1_complex_4>>
 - VPMULLQ: 16 occurrences<<list_path_1_complex_5>>
 - VSCATTERQPD: 4 occurrences<<list_path_1_complex_6>>



      6.1.4.1.6  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 1 occurrence(s)
 - Irregular (variable stride) or indirect: 10 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.4.1.7  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses). By removing them, you can lower the cost of an iteration from 147.50 to 96.00 cycles (1.54x speedup).

Details
 - VGATHERQPD: 36 occurrences<<list_path_1_gather_scatter_1>>
 - VSCATTERQPD: 4 occurrences<<list_path_1_gather_scatter_2>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.4.1.8  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 8 occurrences<<list_path_1_cvt_1>>
 - VPMOVQD: 2 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.4.1.9  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

26 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.4.1.10  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 296 FP arithmetical operations:
 - 152: addition or subtraction (88 inside FMA instructions)
 - 136: multiply (88 inside FMA instructions)
 - 8: divide
The binary loop is loading 2624 bytes (328 double precision FP elements).
The binary loop is storing 256 bytes (32 double precision FP elements).


      6.1.4.1.11  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.







      6.1.5  -  Loop 174 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181-186,192-211


It is main loop of related source loop which is unrolled by 16 (including vectorization).

      6.1.5.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.06 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.5.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 256.00 to 114.50 cycles (2.24x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.5.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 54% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 256.00 to 176.00 cycles (1.45x speedup).

Details
64% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 91% of SSE/AVX loads are used in vector version.
 - 40% of SSE/AVX stores are used in vector version.
 - 27% of SSE/AVX divide and square root instructions are used in vector version.
 - 55% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.5.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 256.00 to 122.50 cycles (2.09x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.5.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 256.00 to 113.50 cycles (2.26x speedup).


      6.1.5.1.5  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.5.1.6  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 32 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.5.1.7  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 16 occurrences<<list_path_1_complex_1>>
 - VDIVPD: 6 occurrences<<list_path_1_complex_2>>
 - VGATHERDPD: 4 occurrences<<list_path_1_complex_3>>
 - VGATHERQPD: 10 occurrences<<list_path_1_complex_4>>
 - VPEXTRQ: 12 occurrences<<list_path_1_complex_5>>
 - VPMULLQ: 14 occurrences<<list_path_1_complex_6>>
 - VSCATTERQPD: 2 occurrences<<list_path_1_complex_7>>



      6.1.5.1.8  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 5 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.5.1.9  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses).

Details
 - VGATHERDPD: 4 occurrences<<list_path_1_gather_scatter_1>>
 - VGATHERQPD: 10 occurrences<<list_path_1_gather_scatter_2>>
 - VSCATTERQPD: 2 occurrences<<list_path_1_gather_scatter_3>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.5.1.10  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 16 occurrences<<list_path_1_cvt_1>>
 - VPMOVQD: 4 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.5.1.11  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

40 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.5.1.12  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 272 FP arithmetical operations:
 - 112: addition or subtraction (32 inside FMA instructions)
 - 112: multiply (32 inside FMA instructions)
 - 48: divide
The binary loop is loading 1360 bytes (170 double precision FP elements).
The binary loop is storing 152 bytes (19 double precision FP elements).


      6.1.5.1.13  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.







      6.1.6  -  Loop 166 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109-114,120-139


It is main loop of related source loop which is unrolled by 16 (including vectorization).

      6.1.6.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.06 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 256.00 to 108.50 cycles (2.36x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.6.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 54% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 256.00 to 176.00 cycles (1.45x speedup).

Details
64% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 91% of SSE/AVX loads are used in vector version.
 - 40% of SSE/AVX stores are used in vector version.
 - 27% of SSE/AVX divide and square root instructions are used in vector version.
 - 56% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.6.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 256.00 to 116.50 cycles (2.20x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.6.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 256.00 to 107.50 cycles (2.38x speedup).


      6.1.6.1.5  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.6.1.6  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 32 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.6.1.7  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 16 occurrences<<list_path_1_complex_1>>
 - VDIVPD: 6 occurrences<<list_path_1_complex_2>>
 - VGATHERDPD: 4 occurrences<<list_path_1_complex_3>>
 - VGATHERQPD: 10 occurrences<<list_path_1_complex_4>>
 - VPEXTRQ: 12 occurrences<<list_path_1_complex_5>>
 - VPMULLQ: 10 occurrences<<list_path_1_complex_6>>
 - VSCATTERQPD: 2 occurrences<<list_path_1_complex_7>>



      6.1.6.1.8  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 5 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.6.1.9  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses).

Details
 - VGATHERDPD: 4 occurrences<<list_path_1_gather_scatter_1>>
 - VGATHERQPD: 10 occurrences<<list_path_1_gather_scatter_2>>
 - VSCATTERQPD: 2 occurrences<<list_path_1_gather_scatter_3>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.6.1.10  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 16 occurrences<<list_path_1_cvt_1>>
 - VPMOVQD: 4 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.6.1.11  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

40 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.6.1.12  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 272 FP arithmetical operations:
 - 112: addition or subtraction (32 inside FMA instructions)
 - 112: multiply (32 inside FMA instructions)
 - 48: divide
The binary loop is loading 1408 bytes (176 double precision FP elements).
The binary loop is storing 152 bytes (19 double precision FP elements).


      6.1.6.1.13  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.







      6.1.7  -  Loop 175 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:219-221


It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.7.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

1% of peak computational performance is used (0.33 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.7.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 96.00 to 41.50 cycles (2.31x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.7.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 40% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 96.00 to 56.00 cycles (1.71x speedup).

Details
51% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 11% of SSE/AVX divide and square root instructions are used in vector version.
 - 41% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.7.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 96.00 to 46.00 cycles (2.09x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.7.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 96.00 to 43.00 cycles (2.23x speedup).


      6.1.7.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 8 FMA (fused multiply-add) operations.




      6.1.7.1.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 8 occurrences<<list_path_1_complex_1>>
 - VDIVPD: 1 occurrences<<list_path_1_complex_2>>
 - VGATHERQPD: 5 occurrences<<list_path_1_complex_3>>
 - VPEXTRQ: 8 occurrences<<list_path_1_complex_4>>
 - VPMULLQ: 6 occurrences<<list_path_1_complex_5>>
 - VSCATTERQPD: 1 occurrences<<list_path_1_complex_6>>



      6.1.7.1.7  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 4 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.7.1.8  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses).

Details
 - VGATHERQPD: 5 occurrences<<list_path_1_gather_scatter_1>>
 - VSCATTERQPD: 1 occurrences<<list_path_1_gather_scatter_2>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.7.1.9  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 8 occurrences<<list_path_1_cvt_1>>
 - VPMOVQD: 2 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.7.1.10  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

3 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.7.1.11  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 32 FP arithmetical operations:
 - 16: addition or subtraction (8 inside FMA instructions)
 - 8: multiply (all inside FMA instructions)
 - 8: divide
The binary loop is loading 320 bytes (40 double precision FP elements).
The binary loop is storing 64 bytes (8 double precision FP elements).


      6.1.7.1.12  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.8  -  Loop 220 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37-40
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69


It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.8.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.02 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.8.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 80.00 to 65.00 cycles (1.23x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.8.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 50% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 80.00 to 64.25 cycles (1.25x speedup).

Details
63% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 83% of SSE/AVX loads are used in vector version.
 - 88% of SSE/AVX multiply instructions are used in vector version.
 - 0% of SSE/AVX divide and square root instructions are used in vector version.
 - 51% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.8.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 80.00 to 71.00 cycles (1.13x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.8.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 80.00 to 71.00 cycles (1.13x speedup).


      6.1.8.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).





      6.1.8.1.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 8 occurrences<<list_path_1_complex_1>>
 - VGATHERQPD: 10 occurrences<<list_path_1_complex_2>>
 - VPEXTRQ: 8 occurrences<<list_path_1_complex_3>>
 - VPMULLQ: 11 occurrences<<list_path_1_complex_4>>
 - VSCATTERQPD: 2 occurrences<<list_path_1_complex_5>>



      6.1.8.1.7  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 8 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.8.1.8  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses).

Details
 - VGATHERQPD: 10 occurrences<<list_path_1_gather_scatter_1>>
 - VSCATTERQPD: 2 occurrences<<list_path_1_gather_scatter_2>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.8.1.9  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 8 occurrences<<list_path_1_cvt_1>>
 - VPMOVQD: 2 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.8.1.10  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
10 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.8.1.11  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 82 FP arithmetical operations:
 - 48: addition or subtraction
 - 34: multiply
The binary loop is loading 680 bytes (85 double precision FP elements).
The binary loop is storing 128 bytes (16 double precision FP elements).


      6.1.8.1.12  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.







      6.1.9  -  Loop 167 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:147-149


It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.9.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

1% of peak computational performance is used (0.33 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.9.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 96.00 to 40.00 cycles (2.40x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.9.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 40% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 96.00 to 56.00 cycles (1.71x speedup).

Details
50% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 11% of SSE/AVX divide and square root instructions are used in vector version.
 - 40% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.9.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 96.00 to 44.50 cycles (2.16x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.9.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 96.00 to 41.50 cycles (2.31x speedup).


      6.1.9.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 8 FMA (fused multiply-add) operations.




      6.1.9.1.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 8 occurrences<<list_path_1_complex_1>>
 - VDIVPD: 1 occurrences<<list_path_1_complex_2>>
 - VGATHERQPD: 5 occurrences<<list_path_1_complex_3>>
 - VPEXTRQ: 8 occurrences<<list_path_1_complex_4>>
 - VPMULLQ: 5 occurrences<<list_path_1_complex_5>>
 - VSCATTERQPD: 1 occurrences<<list_path_1_complex_6>>



      6.1.9.1.7  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 4 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.9.1.8  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses).

Details
 - VGATHERQPD: 5 occurrences<<list_path_1_gather_scatter_1>>
 - VSCATTERQPD: 1 occurrences<<list_path_1_gather_scatter_2>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.9.1.9  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 8 occurrences<<list_path_1_cvt_1>>
 - VPMOVQD: 2 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.9.1.10  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

3 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.9.1.11  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 32 FP arithmetical operations:
 - 16: addition or subtraction (8 inside FMA instructions)
 - 8: multiply (all inside FMA instructions)
 - 8: divide
The binary loop is loading 320 bytes (40 double precision FP elements).
The binary loop is storing 64 bytes (8 double precision FP elements).


      6.1.9.1.12  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.10  -  Loop 142 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66-110


It is main loop of related source loop which is unrolled by 16 (including vectorization).

      6.1.10.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

Warnings:
The number of fused uops of the instruction [VPCMPEQD	%YMM1,%YMM1,%YMM1] is unknown
5% of peak computational performance is used (1.81 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.10.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 256.00 to 154.50 cycles (1.66x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.10.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 63% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 256.00 to 176.00 cycles (1.45x speedup).

Details
74% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 95% of SSE/AVX loads are used in vector version.
 - 70% of SSE/AVX stores are used in vector version.
 - 27% of SSE/AVX divide and square root instructions are used in vector version.
 - 67% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.10.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 256.00 to 168.50 cycles (1.52x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.10.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 256.00 to 159.50 cycles (1.61x speedup).


      6.1.10.1.5  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.10.1.6  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 80 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.10.1.7  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - IDIV: 16 occurrences<<list_path_1_complex_1>>
 - VDIVPD: 6 occurrences<<list_path_1_complex_2>>
 - VGATHERDPD: 2 occurrences<<list_path_1_complex_3>>
 - VGATHERQPD: 22 occurrences<<list_path_1_complex_4>>
 - VPEXTRQ: 12 occurrences<<list_path_1_complex_5>>
 - VPMULLQ: 14 occurrences<<list_path_1_complex_6>>
 - VSCATTERQPD: 4 occurrences<<list_path_1_complex_7>>



      6.1.10.1.8  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 1 occurrence(s)
 - Irregular (variable stride) or indirect: 6 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.10.1.9  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses).

Details
 - VGATHERDPD: 2 occurrences<<list_path_1_gather_scatter_1>>
 - VGATHERQPD: 22 occurrences<<list_path_1_gather_scatter_2>>
 - VSCATTERQPD: 4 occurrences<<list_path_1_gather_scatter_3>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.10.1.10  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CQTO: 16 occurrences<<list_path_1_cvt_1>>
 - VPMOVQD: 4 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.10.1.11  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

66 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.10.1.12  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 464 FP arithmetical operations:
 - 192: addition or subtraction (80 inside FMA instructions)
 - 224: multiply (80 inside FMA instructions)
 - 48: divide
The binary loop is loading 2704 bytes (338 double precision FP elements).
The binary loop is storing 472 bytes (59 double precision FP elements).


      6.1.10.1.13  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.





[MAQAO] Info: STOP THE REPORT GENERATION
[MAQAO] Info: 
[MAQAO] Info: If your application produces files, they can be found in directory "/beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4073/intel/CloverLeaf2.0-CXX/run/oneview_runs/compilers/aocc_7/oneview_run_1786619102"
[MAQAO] Info: 
