OV - exec - Loop 304

	Loop Id: 304	Module: exec	Source: revert.cpp:35-39 [...]	Coverage: 1.97%

0x444440 MOVQ	%XMM6,%RAX

0x444445 XOR	%EDX,%EDX

0x444447 DIV	%RDI

0x44444a MOVQ	%RAX,%XMM1

0x44444f PSHUFD	$-0x12,%XMM6,%XMM2

0x444454 MOVQ	%XMM2,%RAX

0x444459 XOR	%EDX,%EDX

0x44445b DIV	%R15

0x44445e MOVQ	%RAX,%XMM2

0x444463 PUNPCKLQDQ	%XMM2,%XMM1

0x444467 MOVDQA	%XMM1,%XMM15

0x44446c PADDQ	-0xd0(%RBP),%XMM15    [6]

0x444475 PMULUDQ	-0xe0(%RBP),%XMM1    [6]

0x44447d MOVDQA	%XMM6,%XMM2

0x444481 PSUBQ	%XMM1,%XMM2

0x444485 PADDQ	-0xc0(%RBP),%XMM2    [6]

0x44448d PSLLQ	$0x20,%XMM2

0x444492 PSHUFD	$-0x13,%XMM2,%XMM9

0x444498 PSHUFD	$-0x18,%XMM15,%XMM2

0x44449e PSLLQ	$0x20,%XMM15

0x4444a4 PSRAD	$0x1f,%XMM15

0x4444aa MOVDQA	%XMM9,%XMM1

0x4444af PSHUFD	$-0x13,%XMM15,%XMM3

0x4444b5 PUNPCKLDQ	%XMM3,%XMM2

0x4444b9 MOVDQA	%XMM8,%XMM3

0x4444be PSRAD	$0x1f,%XMM1

0x4444c3 PMULUDQ	%XMM2,%XMM3

0x4444c7 MOVDQA	%XMM11,%XMM0

0x4444cc PMULUDQ	%XMM2,%XMM0

0x4444d0 PUNPCKLDQ	%XMM1,%XMM9

0x4444d5 PSRLQ	$0x20,%XMM15

0x4444db MOVDQA	%XMM8,%XMM1

0x4444e0 PMULUDQ	%XMM15,%XMM1

0x4444e5 PADDQ	%XMM0,%XMM1

0x4444e9 PSLLQ	$0x20,%XMM1

0x4444ee PADDQ	%XMM9,%XMM3

0x4444f3 PADDQ	%XMM1,%XMM3

0x4444f7 PSLLQ	$0x3,%XMM3

0x4444fc MOVDQA	%XMM10,%XMM0

0x444501 PMULUDQ	%XMM2,%XMM0

0x444505 MOVDQA	%XMM4,%XMM1

0x444509 PADDQ	-0xb0(%RBP),%XMM3    [6]

0x444511 PMULUDQ	%XMM15,%XMM1

0x444516 PADDQ	%XMM0,%XMM1

0x44451a MOVDQA	%XMM4,%XMM0

0x44451e MOVQ	%XMM3,%RDX

0x444523 PMULUDQ	%XMM2,%XMM0

0x444527 PSLLQ	$0x20,%XMM1

0x44452c PADDQ	%XMM9,%XMM0

0x444531 PSHUFD	$-0x12,%XMM3,%XMM3

0x444536 PADDQ	%XMM1,%XMM0

0x44453a PSLLQ	$0x3,%XMM0

0x44453f PADDQ	-0xa0(%RBP),%XMM0    [6]

0x444547 MOVQ	%XMM3,%R9

0x44454c MOVQ	%XMM0,%R12

0x444551 PSHUFD	$-0x12,%XMM0,%XMM0

0x444556 MOVDQA	%XMM5,%XMM1

0x44455a MOVQ	%XMM0,%RAX

0x44455f MOVDQA	%XMM12,%XMM0

0x444564 PMULUDQ	%XMM2,%XMM0

0x444568 MOVDQA	%XMM5,%XMM3

0x44456c PMULUDQ	%XMM2,%XMM1

0x444570 PMULUDQ	%XMM15,%XMM3

0x444575 PADDQ	%XMM0,%XMM3

0x444579 PSLLQ	$0x20,%XMM3

0x44457e MOVSD	(%RDX),%XMM0    [10]

0x444582 PADDQ	%XMM9,%XMM1

0x444587 PADDQ	%XMM3,%XMM1

0x44458b MOVSD	(%R9),%XMM3    [3]

0x444590 MOVSD	%XMM0,(%R12)    [7]

0x444596 PSLLQ	$0x3,%XMM1

0x44459b PADDQ	%XMM13,%XMM1

0x4445a0 MOVQ	%XMM1,%R9

0x4445a5 PSHUFD	$-0x12,%XMM1,%XMM0

0x4445aa MOVQ	%XMM0,%RDX

0x4445af MOVDQA	%XMM7,%XMM0

0x4445b3 PMULUDQ	%XMM2,%XMM0

0x4445b7 PMULUDQ	%XMM14,%XMM2

0x4445bc PMULUDQ	%XMM7,%XMM15

0x4445c1 PADDQ	%XMM2,%XMM15

0x4445c6 PADDQ	%XMM9,%XMM0

0x4445cb MOVSD	%XMM3,(%RAX)    [5]

0x4445cf PSLLQ	$0x20,%XMM15

0x4445d5 PADDQ	%XMM15,%XMM0

0x4445da MOVQ	%R13,%XMM1

0x4445df PSLLQ	$0x3,%XMM0

0x4445e4 PSHUFD	$0x44,%XMM1,%XMM1

0x4445e9 PADDQ	%XMM0,%XMM1

0x4445ed MOVQ	(%R9),%XMM0    [2]

0x4445f2 MOVQ	%XMM1,%RAX

0x4445f7 PSHUFD	$-0x12,%XMM1,%XMM1

0x4445fc MOVQ	%XMM1,%R9

0x444601 MOVQ	(%RDX),%XMM1    [9]

0x444605 MOVQ	%XMM0,(%RAX)    [4]

0x444609 MOVQ	%XMM1,(%R9)    [1]

0x44460e PADDQ	0x56e3a(%RIP),%XMM6    [8]

0x444616 ADD	$0x2,%R10

0x44461a CMP	%R8,%R10

0x44461d JB	444440

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp: 35 - 39

--------------------------------------------------------------------------------

35:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

36:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

37:       density1(i, j) = density0(i, j);

38:       energy1(i, j) = energy0(i, j);

39:     }

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.08
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.57
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P0, P1, P5,
Function	revert_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source	context.h:69-69,revert.cpp:35-39
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	25.67
CQA cycles if no scalar integer	23.83
CQA cycles if FP arith vectorized	25.67
CQA cycles if fully vectorized	10.00
Front-end cycles	17.67
P0 cycles	25.67
P1 cycles	25.67
P2 cycles	3.33
P3 cycles	3.33
P4 cycles	2.00
P5 cycles	25.67
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	3.33
DIV/SQRT cycles	20.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	99.00
Nb uops	106.00
Nb loads	10.00
Nb stores	4.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.23
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	32.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	74.47
Vectorization ratio load	60.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	72.55
Vector-efficiency ratio all	19.81
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	21.08

Metric	Value
CQA speedup if no scalar integer	1.08
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.57
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P0, P1, P5,
Function	revert_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source	context.h:69-69,revert.cpp:35-39
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	25.67
CQA cycles if no scalar integer	23.83
CQA cycles if FP arith vectorized	25.67
CQA cycles if fully vectorized	10.00
Front-end cycles	17.67
P0 cycles	25.67
P1 cycles	25.67
P2 cycles	3.33
P3 cycles	3.33
P4 cycles	2.00
P5 cycles	25.67
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	3.33
DIV/SQRT cycles	20.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	99.00
Nb uops	106.00
Nb loads	10.00
Nb stores	4.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.23
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	32.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	74.47
Vectorization ratio load	60.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	72.55
Vector-efficiency ratio all	19.81
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	21.08

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	revert_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source file and lines	revert.cpp:35-39
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:35-39

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.67 to 23.83 cycles (1.08x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 19% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 25.67 to 10.00 cycles (2.57x speedup).

Details

74% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

60% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
72% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:35
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:35

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	99
nb uops	106
loop length	483
used x86 registers	10
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	17.67 cycles
front end	17.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	25.67	25.67	3.33	3.33	2.00	25.67	1.00	2.00	2.00	2.00	0.00	3.33
cycles	25.67	25.67	3.33	3.33	2.00	25.67	1.00	2.00	2.00	2.00	0.00	3.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	20.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	17.67
Dispatch	25.67
DIV/SQRT	20.00
Data deps.	1.00
Overall L1	25.67

Vectorization ratios

INT

all	77%
load	75%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	69%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	74%
load	60%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	72%

Vector efficiency ratios

INT

all	20%
load	20%
store	12%
mul	12%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	19%
load	18%
store	12%
mul	12%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.67 cycles. At this rate:

2% of peak load performance is reached (4.99 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 444440

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOVQ %XMM6,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %RDI	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOVQ %RAX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM6,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM2,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R15	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOVQ %RAX,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PUNPCKLQDQ %XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM1,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PADDQ -0xd0(%RBP),%XMM15	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PMULUDQ -0xe0(%RBP),%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	5	0.50	vect (12.5%)
MOVDQA %XMM6,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSUBQ %XMM1,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
PADDQ -0xc0(%RBP),%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSHUFD $-0x13,%XMM2,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSHUFD $-0x18,%XMM15,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLQ $0x20,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRAD $0x1f,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM9,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSHUFD $-0x13,%XMM15,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PUNPCKLDQ %XMM3,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOVDQA %XMM8,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRAD $0x1f,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM2,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM11,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PUNPCKLDQ %XMM1,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
PSRLQ $0x20,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM15,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM0,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM9,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM1,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM10,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PADDQ -0xb0(%RBP),%XMM3	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PMULUDQ %XMM15,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM0,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVQ %XMM3,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PMULUDQ %XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSLLQ $0x20,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM9,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSHUFD $-0x12,%XMM3,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM1,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ -0xa0(%RBP),%XMM0	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOVQ %XMM3,%R9	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVQ %XMM0,%R12	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM5,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVQ %XMM0,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM12,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM2,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PMULUDQ %XMM15,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM0,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVSD (%RDX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
PADDQ %XMM9,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM3,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVSD (%R9),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSD %XMM0,(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
PSLLQ $0x3,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM13,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM1,%R9	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PMULUDQ %XMM14,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PMULUDQ %XMM7,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM2,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM9,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVSD %XMM3,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
PSLLQ $0x20,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM15,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %R13,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSLLQ $0x3,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSHUFD $0x44,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM0,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ (%R9),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVQ %XMM1,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%R9	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVQ (%RDX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVQ %XMM0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %XMM1,(%R9)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
PADDQ 0x56e3a(%RIP),%XMM6	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
ADD $0x2,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 444440 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.extracted+0x1f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	revert_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source file and lines	revert.cpp:35-39
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:35-39

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

74% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

60% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
72% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:35
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:35

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	99
nb uops	106
loop length	483
used x86 registers	10
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	17.67 cycles
front end	17.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	25.67	25.67	3.33	3.33	2.00	25.67	1.00	2.00	2.00	2.00	0.00	3.33
cycles	25.67	25.67	3.33	3.33	2.00	25.67	1.00	2.00	2.00	2.00	0.00	3.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	20.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	17.67
Dispatch	25.67
DIV/SQRT	20.00
Data deps.	1.00
Overall L1	25.67

Vectorization ratios

INT

all	77%
load	75%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	69%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	74%
load	60%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	72%

Vector efficiency ratios

INT

all	20%
load	20%
store	12%
mul	12%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	19%
load	18%
store	12%
mul	12%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.67 cycles. At this rate:

2% of peak load performance is reached (4.99 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 444440

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOVQ %XMM6,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %RDI	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOVQ %RAX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM6,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM2,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R15	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOVQ %RAX,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PUNPCKLQDQ %XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM1,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PADDQ -0xd0(%RBP),%XMM15	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PMULUDQ -0xe0(%RBP),%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	5	0.50	vect (12.5%)
MOVDQA %XMM6,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSUBQ %XMM1,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
PADDQ -0xc0(%RBP),%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSHUFD $-0x13,%XMM2,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSHUFD $-0x18,%XMM15,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLQ $0x20,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRAD $0x1f,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM9,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSHUFD $-0x13,%XMM15,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PUNPCKLDQ %XMM3,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOVDQA %XMM8,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRAD $0x1f,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM2,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM11,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PUNPCKLDQ %XMM1,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
PSRLQ $0x20,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM15,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM0,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM9,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM1,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM10,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PADDQ -0xb0(%RBP),%XMM3	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PMULUDQ %XMM15,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM0,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVQ %XMM3,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PMULUDQ %XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSLLQ $0x20,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM9,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSHUFD $-0x12,%XMM3,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM1,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ -0xa0(%RBP),%XMM0	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOVQ %XMM3,%R9	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVQ %XMM0,%R12	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM5,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVQ %XMM0,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM12,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM2,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PMULUDQ %XMM15,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM0,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVSD (%RDX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
PADDQ %XMM9,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM3,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVSD (%R9),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSD %XMM0,(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
PSLLQ $0x3,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM13,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM1,%R9	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PMULUDQ %XMM14,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PMULUDQ %XMM7,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM2,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM9,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVSD %XMM3,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
PSLLQ $0x20,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM15,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %R13,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSLLQ $0x3,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSHUFD $0x44,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM0,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ (%R9),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVQ %XMM1,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%R9	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVQ (%RDX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVQ %XMM0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %XMM1,(%R9)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
PADDQ 0x56e3a(%RIP),%XMM6	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
ADD $0x2,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 444440 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.extracted+0x1f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code