OV - exec - Loop 234

	Loop Id: 234	Module: exec	Source: ideal_gas.cpp:38-46 [...]	Coverage: 4.23%

0x4388d0 MOVQ	%XMM7,%RAX

0x4388d5 XOR	%EDX,%EDX

0x4388d7 DIV	%RDI

0x4388da MOVQ	%RAX,%XMM1

0x4388df PSHUFD	$-0x12,%XMM7,%XMM2

0x4388e4 MOVQ	%XMM2,%RAX

0x4388e9 XOR	%EDX,%EDX

0x4388eb DIV	%R9

0x4388ee MOVQ	%RAX,%XMM2

0x4388f3 PUNPCKLQDQ	%XMM2,%XMM1

0x4388f7 MOVDQA	%XMM1,%XMM10

0x4388fc PMULUDQ	-0xd0(%RBP),%XMM1    [5]

0x438904 PADDQ	-0xc0(%RBP),%XMM10    [5]

0x43890d MOVDQA	%XMM7,%XMM2

0x438911 PSUBQ	%XMM1,%XMM2

0x438915 PADDQ	-0xb0(%RBP),%XMM2    [5]

0x43891d PSLLQ	$0x20,%XMM2

0x438922 PSHUFD	$-0x18,%XMM10,%XMM11

0x438928 PSLLQ	$0x20,%XMM10

0x43892e PSRAD	$0x1f,%XMM10

0x438934 PSHUFD	$-0x13,%XMM2,%XMM15

0x43893a PSHUFD	$-0x13,%XMM10,%XMM1

0x438940 PUNPCKLDQ	%XMM1,%XMM11

0x438945 MOVDQA	%XMM0,%XMM1

0x438949 MOVDQA	%XMM15,%XMM2

0x43894e PMULUDQ	%XMM11,%XMM1

0x438953 MOVDQA	%XMM9,%XMM8

0x438958 PMULUDQ	%XMM11,%XMM8

0x43895d PSRAD	$0x1f,%XMM2

0x438962 PSRLQ	$0x20,%XMM10

0x438968 MOVDQA	%XMM0,%XMM3

0x43896c PMULUDQ	%XMM10,%XMM3

0x438971 PUNPCKLDQ	%XMM2,%XMM15

0x438976 PADDQ	%XMM8,%XMM3

0x43897b PSLLQ	$0x20,%XMM3

0x438980 PADDQ	%XMM15,%XMM1

0x438985 PADDQ	%XMM3,%XMM1

0x438989 PSLLQ	$0x3,%XMM1

0x43898e PADDQ	-0xa0(%RBP),%XMM1    [5]

0x438996 PSHUFD	$-0x12,%XMM1,%XMM2

0x43899b MOVQ	%XMM1,%RDX

0x4389a0 MOVQ	%XMM2,%RAX

0x4389a5 MOVSD	(%RDX),%XMM2    [10]

0x4389a9 MOVHPD	(%RAX),%XMM2    [2]

0x4389ad MOVDQA	%XMM12,%XMM3

0x4389b2 PMULUDQ	%XMM11,%XMM3

0x4389b7 MOVDQA	%XMM4,%XMM8

0x4389bc MOVAPD	0x62c1c(%RIP),%XMM1    [8]

0x4389c4 PMULUDQ	%XMM10,%XMM8

0x4389c9 PADDQ	%XMM3,%XMM8

0x4389ce MOVDQA	%XMM4,%XMM3

0x4389d2 DIVPD	%XMM2,%XMM1

0x4389d6 PMULUDQ	%XMM11,%XMM3

0x4389db PSLLQ	$0x20,%XMM8

0x4389e1 PADDQ	%XMM15,%XMM3

0x4389e6 PADDQ	%XMM8,%XMM3

0x4389eb PSLLQ	$0x3,%XMM3

0x4389f0 PADDQ	%XMM13,%XMM3

0x4389f5 PSHUFD	$-0x12,%XMM3,%XMM8

0x4389fb MOVQ	%XMM3,%R12

0x438a00 MOVQ	%XMM8,%R11

0x438a05 MOVDQA	%XMM14,%XMM3

0x438a0a MOVDQA	%XMM5,%XMM8

0x438a0f PMULUDQ	%XMM11,%XMM3

0x438a14 PMULUDQ	%XMM10,%XMM8

0x438a19 PADDQ	%XMM3,%XMM8

0x438a1e MOVDQA	%XMM5,%XMM3

0x438a22 PMULUDQ	%XMM11,%XMM3

0x438a27 PSLLQ	$0x20,%XMM8

0x438a2d PADDQ	%XMM15,%XMM3

0x438a32 PADDQ	%XMM8,%XMM3

0x438a37 MULPD	0x65db1(%RIP),%XMM2    [8]

0x438a3f MOVSD	(%R12),%XMM8    [7]

0x438a45 MOVHPD	(%R11),%XMM8    [4]

0x438a4a MULPD	%XMM2,%XMM8

0x438a4f PSLLQ	$0x3,%XMM3

0x438a54 MOVQ	%R15,%XMM2

0x438a59 PSHUFD	$0x44,%XMM2,%XMM2

0x438a5e PADDQ	%XMM3,%XMM2

0x438a62 MOVQ	%XMM2,%R11

0x438a67 PSHUFD	$-0x12,%XMM2,%XMM2

0x438a6c MOVQ	%XMM2,%R12

0x438a71 MOVLPD	%XMM8,(%R11)    [3]

0x438a76 MOVHPD	%XMM8,(%R12)    [6]

0x438a7c MOVSD	(%RDX),%XMM2    [10]

0x438a80 MOVHPD	(%RAX),%XMM2    [2]

0x438a84 MULPD	%XMM1,%XMM1

0x438a88 MULPD	%XMM8,%XMM2

0x438a8d MULPD	0x65d6b(%RIP),%XMM1    [8]

0x438a95 MULPD	%XMM1,%XMM2

0x438a99 MOVDQA	%XMM6,%XMM1

0x438a9d MOVDQA	%XMM6,%XMM3

0x438aa1 PMULUDQ	%XMM11,%XMM1

0x438aa6 PSRLQ	$0x20,%XMM3

0x438aab PMULUDQ	%XMM11,%XMM3

0x438ab0 PMULUDQ	%XMM6,%XMM10

0x438ab5 PADDQ	%XMM3,%XMM10

0x438aba PADDQ	%XMM15,%XMM1

0x438abf PSLLQ	$0x20,%XMM10

0x438ac5 PADDQ	%XMM10,%XMM1

0x438aca PSLLQ	$0x3,%XMM1

0x438acf MOVQ	%R14,%XMM3

0x438ad4 PSHUFD	$0x44,%XMM3,%XMM3

0x438ad9 PADDQ	%XMM1,%XMM3

0x438add MOVQ	%XMM3,%RAX

0x438ae2 PSHUFD	$-0x12,%XMM3,%XMM1

0x438ae7 MOVQ	%XMM1,%RDX

0x438aec SQRTPD	%XMM2,%XMM1

0x438af0 MOVLPD	%XMM1,(%RAX)    [1]

0x438af4 MOVHPD	%XMM1,(%RDX)    [9]

0x438af8 PADDQ	0x62950(%RIP),%XMM7    [8]

0x438b00 ADD	$0x2,%R10

0x438b04 CMP	%R13,%R10

0x438b07 JB	4388d0

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp: 38 - 46

--------------------------------------------------------------------------------

38:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

39:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

40:       double v = 1.0 / density(i, j);

41:       pressure(i, j) = (1.4 - 1.0) * density(i, j) * energy(i, j);

42:       double pressurebyenergy = (1.4 - 1.0) * density(i, j);

43:       double pressurebyvolume = -density(i, j) * pressure(i, j);

44:       double sound_speed_squared = v * v * (pressure(i, j) * pressurebyenergy - pressurebyvolume);

45:       soundspeed(i, j) = std::sqrt(sound_speed_squared);

46:     }

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.07
CQA speedup if FP arith vectorized	1.07
CQA speedup if fully vectorized	1.65
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P5,
Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source	context.h:69-69,ideal_gas.cpp:38-46
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	30.50
CQA cycles if no scalar integer	28.50
CQA cycles if FP arith vectorized	28.50
CQA cycles if fully vectorized	18.50
Front-end cycles	20.17
P0 cycles	30.17
P1 cycles	30.33
P2 cycles	4.67
P3 cycles	4.67
P4 cycles	2.00
P5 cycles	30.50
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	4.67
DIV/SQRT cycles	28.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	114.00
Nb uops	121.00
Nb loads	14.00
Nb stores	4.00
Nb stack references	4.00
FLOP/cycle	0.52
Nb FLOP add-sub	0.00
Nb FLOP mul	12.00
Nb FLOP fma	0.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	2.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.82
Bytes prefetched	0.00
Bytes loaded	176.00
Bytes stored	32.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	75.23
Vectorization ratio load	57.14
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	50.00
Vectorization ratio other	72.73
Vector-efficiency ratio all	20.18
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	16.45
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	18.75
Vector-efficiency ratio other	21.14

Metric	Value
CQA speedup if no scalar integer	1.07
CQA speedup if FP arith vectorized	1.07
CQA speedup if fully vectorized	1.65
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P5,
Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source	context.h:69-69,ideal_gas.cpp:38-46
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	30.50
CQA cycles if no scalar integer	28.50
CQA cycles if FP arith vectorized	28.50
CQA cycles if fully vectorized	18.50
Front-end cycles	20.17
P0 cycles	30.17
P1 cycles	30.33
P2 cycles	4.67
P3 cycles	4.67
P4 cycles	2.00
P5 cycles	30.50
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	4.67
DIV/SQRT cycles	28.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	114.00
Nb uops	121.00
Nb loads	14.00
Nb stores	4.00
Nb stack references	4.00
FLOP/cycle	0.52
Nb FLOP add-sub	0.00
Nb FLOP mul	12.00
Nb FLOP fma	0.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	2.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.82
Bytes prefetched	0.00
Bytes loaded	176.00
Bytes stored	32.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	75.23
Vectorization ratio load	57.14
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	50.00
Vectorization ratio other	72.73
Vector-efficiency ratio all	20.18
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	16.45
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	18.75
Vector-efficiency ratio other	21.14

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source file and lines	ideal_gas.cpp:38-46
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38-46

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 30.50 to 28.50 cycles (1.07x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 20% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 30.50 to 18.50 cycles (1.65x speedup).

Details

75% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

57% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
50% of SSE/AVX divide and square root instructions are used in vector version.
72% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 5 suboptimal vector unaligned load/store instructions.

Details

MOVHPD: 5 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:40
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:41
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:41
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:42
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:45

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

12: multiply
2: divide
2: square root

The binary loop is loading 176 bytes (22 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	114
nb uops	121
loop length	573
used x86 registers	11
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	20.17 cycles
front end	20.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	30.17	30.33	4.67	4.67	2.00	30.50	1.00	2.00	2.00	2.00	0.00	4.67
cycles	30.17	30.33	4.67	4.67	2.00	30.50	1.00	2.00	2.00	2.00	0.00	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	28.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	20.17
Dispatch	30.50
DIV/SQRT	28.50
Data deps.	1.00
Overall L1	30.50

Vectorization ratios

INT

all	81%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	70%

all	47%
load	33%
store	0%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	75%
load	57%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	50%
other	72%

Vector efficiency ratios

INT

all	20%
load	22%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	18%
load	16%
store	12%
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	20%
load	18%
store	12%
mul	16%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	18%
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 30.50 cycles. At this rate:

3% of peak load performance is reached (5.77 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.05 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4388d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOVQ %XMM7,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %RDI	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOVQ %RAX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM7,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM2,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R9	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOVQ %RAX,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PUNPCKLQDQ %XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ -0xd0(%RBP),%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	5	0.50	vect (12.5%)
PADDQ -0xc0(%RBP),%XMM10	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOVDQA %XMM7,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSUBQ %XMM1,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
PADDQ -0xb0(%RBP),%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSHUFD $-0x18,%XMM10,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLQ $0x20,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRAD $0x1f,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSHUFD $-0x13,%XMM2,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSHUFD $-0x13,%XMM10,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PUNPCKLDQ %XMM1,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOVDQA %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVDQA %XMM15,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM11,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM9,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM11,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSRAD $0x1f,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRLQ $0x20,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM10,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PUNPCKLDQ %XMM2,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
PADDQ %XMM8,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM15,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM3,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ -0xa0(%RBP),%XMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PSHUFD $-0x12,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVQ %XMM2,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%RDX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%RAX),%XMM2	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
MOVDQA %XMM12,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM11,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM4,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVAPD 0x62c1c(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PMULUDQ %XMM10,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM3,%XMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
DIVPD %XMM2,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	vect (25.0%)
PMULUDQ %XMM11,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSLLQ $0x20,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM15,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM8,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM13,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSHUFD $-0x12,%XMM3,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM3,%R12	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVQ %XMM8,%R11	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM14,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVDQA %XMM5,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM11,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PMULUDQ %XMM10,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM3,%XMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM11,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSLLQ $0x20,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM15,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM8,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MULPD 0x65db1(%RIP),%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
MOVSD (%R12),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%R11),%XMM8	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
MULPD %XMM2,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
PSLLQ $0x3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R15,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM2,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM3,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM2,%R11	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM2,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM2,%R12	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVLPD %XMM8,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
MOVHPD %XMM8,(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
MOVSD (%RDX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%RAX),%XMM2	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
MULPD %XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
MULPD %XMM8,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
MULPD 0x65d6b(%RIP),%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
MULPD %XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
MOVDQA %XMM6,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVDQA %XMM6,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM11,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSRLQ $0x20,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM11,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PMULUDQ %XMM6,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM3,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM15,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM10,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R14,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM3,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM1,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM3,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM3,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
SQRTPD %XMM2,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	vect (25.0%)
MOVLPD %XMM1,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
MOVHPD %XMM1,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
PADDQ 0x62950(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
ADD $0x2,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 4388d0 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.extracted+0x1d0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source file and lines	ideal_gas.cpp:38-46
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38-46

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

75% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

57% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
50% of SSE/AVX divide and square root instructions are used in vector version.
72% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 5 suboptimal vector unaligned load/store instructions.

Details

MOVHPD: 5 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:40
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:41
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:41
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:42
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:45

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

12: multiply
2: divide
2: square root

The binary loop is loading 176 bytes (22 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	114
nb uops	121
loop length	573
used x86 registers	11
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	20.17 cycles
front end	20.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	30.17	30.33	4.67	4.67	2.00	30.50	1.00	2.00	2.00	2.00	0.00	4.67
cycles	30.17	30.33	4.67	4.67	2.00	30.50	1.00	2.00	2.00	2.00	0.00	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	28.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	20.17
Dispatch	30.50
DIV/SQRT	28.50
Data deps.	1.00
Overall L1	30.50

Vectorization ratios

INT

all	81%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	70%

all	47%
load	33%
store	0%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	75%
load	57%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	50%
other	72%

Vector efficiency ratios

INT

all	20%
load	22%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	18%
load	16%
store	12%
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	20%
load	18%
store	12%
mul	16%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	18%
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 30.50 cycles. At this rate:

3% of peak load performance is reached (5.77 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.05 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4388d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOVQ %XMM7,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %RDI	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOVQ %RAX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM7,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM2,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R9	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOVQ %RAX,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PUNPCKLQDQ %XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ -0xd0(%RBP),%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	5	0.50	vect (12.5%)
PADDQ -0xc0(%RBP),%XMM10	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOVDQA %XMM7,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSUBQ %XMM1,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
PADDQ -0xb0(%RBP),%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSHUFD $-0x18,%XMM10,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLQ $0x20,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRAD $0x1f,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSHUFD $-0x13,%XMM2,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSHUFD $-0x13,%XMM10,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PUNPCKLDQ %XMM1,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOVDQA %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVDQA %XMM15,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM11,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM9,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM11,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSRAD $0x1f,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRLQ $0x20,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM10,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PUNPCKLDQ %XMM2,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
PADDQ %XMM8,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM15,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM3,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ -0xa0(%RBP),%XMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PSHUFD $-0x12,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVQ %XMM2,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%RDX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%RAX),%XMM2	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
MOVDQA %XMM12,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM11,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM4,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVAPD 0x62c1c(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PMULUDQ %XMM10,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM3,%XMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
DIVPD %XMM2,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	vect (25.0%)
PMULUDQ %XMM11,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSLLQ $0x20,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM15,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM8,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM13,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSHUFD $-0x12,%XMM3,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM3,%R12	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVQ %XMM8,%R11	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM14,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVDQA %XMM5,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM11,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PMULUDQ %XMM10,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM3,%XMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM11,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSLLQ $0x20,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM15,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM8,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MULPD 0x65db1(%RIP),%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
MOVSD (%R12),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%R11),%XMM8	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
MULPD %XMM2,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
PSLLQ $0x3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R15,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM2,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM3,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM2,%R11	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM2,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM2,%R12	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVLPD %XMM8,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
MOVHPD %XMM8,(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
MOVSD (%RDX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%RAX),%XMM2	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
MULPD %XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
MULPD %XMM8,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
MULPD 0x65d6b(%RIP),%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
MULPD %XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
MOVDQA %XMM6,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVDQA %XMM6,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM11,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSRLQ $0x20,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM11,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PMULUDQ %XMM6,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM3,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM15,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM10,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R14,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM3,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM1,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM3,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM3,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
SQRTPD %XMM2,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	vect (25.0%)
MOVLPD %XMM1,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
MOVHPD %XMM1,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
PADDQ 0x62950(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
ADD $0x2,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 4388d0 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.extracted+0x1d0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code