OV - exec - Loop 217

	Loop Id: 217	Module: exec	Source: field_summary.cpp:81-82 [...]	Coverage: 0.29%

0x432fc0 PAND	%XMM1,%XMM11

0x432fc5 PANDN	%XMM6,%XMM1

0x432fc9 MOVDQA	%XMM1,%XMM6

0x432fcd POR	%XMM11,%XMM6

0x432fd2 PAND	%XMM5,%XMM14

0x432fd7 PANDN	%XMM2,%XMM5

0x432fdb MOVDQA	%XMM5,%XMM2

0x432fdf POR	%XMM14,%XMM2

0x432fe4 MOVDQA	%XMM2,%XMM1

0x432fe8 MULPD	%XMM2,%XMM1

0x432fec ADDPD	%XMM13,%XMM1

0x432ff1 MOVDQA	%XMM6,%XMM5

0x432ff5 MULPD	%XMM6,%XMM5

0x432ff9 ADDPD	%XMM9,%XMM5

0x432ffe MOVAPD	0x6843a(%RIP),%XMM7    [3]

0x433006 MULPD	%XMM7,%XMM1

0x43300a ADDPD	%XMM1,%XMM8

0x43300f MULPD	%XMM7,%XMM5

0x433013 ADDPD	%XMM5,%XMM3

0x433017 MOVQ	%RCX,%XMM1

0x43301c PSHUFD	$0x44,%XMM1,%XMM5

0x433021 PXOR	0x6b1f7(%RIP),%XMM5    [3]

0x433029 MOVDQA	-0x3a0(%RBP),%XMM9    [2]

0x433032 MOVDQA	%XMM9,%XMM7

0x433037 PCMPGTD	%XMM5,%XMM7

0x43303b MOVDQA	-0x390(%RBP),%XMM10    [2]

0x433044 MOVDQA	%XMM10,%XMM1

0x433049 PCMPGTD	%XMM5,%XMM1

0x43304d PCMPEQD	%XMM5,%XMM9

0x433052 PCMPEQD	%XMM10,%XMM5

0x433057 SHUFPS	$-0x23,%XMM9,%XMM5

0x43305c MOVDQA	%XMM1,%XMM9

0x433061 SHUFPS	$-0x78,%XMM7,%XMM9

0x433066 ANDPS	%XMM9,%XMM5

0x43306a SHUFPS	$-0x23,%XMM7,%XMM1

0x43306e ORPS	%XMM5,%XMM1

0x433071 PSHUFD	$-0x6,%XMM15,%XMM5

0x433077 PSLLD	$0x1f,%XMM5

0x43307c PSRAD	$0x1f,%XMM5

0x433081 MOVAPD	%XMM8,%XMM7

0x433086 ANDPD	%XMM5,%XMM7

0x43308a ANDNPD	%XMM12,%XMM5

0x43308f MOVAPD	%XMM5,%XMM12

0x433094 ORPD	%XMM7,%XMM12

0x433099 PSHUFD	$0x50,%XMM15,%XMM5

0x43309f PSLLD	$0x1f,%XMM5

0x4330a4 PSRAD	$0x1f,%XMM5

0x4330a9 MOVAPD	%XMM3,%XMM7

0x4330ad ANDPD	%XMM5,%XMM7

0x4330b1 ANDNPD	%XMM4,%XMM5

0x4330b5 MOVAPD	%XMM5,%XMM4

0x4330b9 ORPD	%XMM7,%XMM4

0x4330bd PAND	%XMM1,%XMM15

0x4330c2 MOVDQA	-0x110(%RBP),%XMM10    [2]

0x4330cb MOVDQA	%XMM10,%XMM1

0x4330d0 PAND	%XMM15,%XMM1

0x4330d5 PSLLD	$0x1f,%XMM1

0x4330da MOVMSKPS	%XMM1,%EDX

0x4330dd INC	%RCX

0x4330e0 TEST	%EDX,%EDX

0x4330e2 JE	432de0

0x4330e8 LEA	-0x1(%RCX),%RDX

0x4330ec MOVDQA	%XMM10,%XMM5

0x4330f1 PAND	%XMM15,%XMM5

0x4330f6 MOVQ	%RDX,%XMM1

0x4330fb PSHUFD	$0x44,%XMM1,%XMM14

0x433101 MOVDQA	-0xf0(%RBP),%XMM1    [2]

0x433109 PADDQ	%XMM14,%XMM1

0x43310e MOVQ	%R14,%XMM9

0x433113 PSHUFD	$0x44,%XMM9,%XMM10

0x433119 PSLLQ	$0x3,%XMM1

0x43311e PADDQ	%XMM10,%XMM1

0x433123 MOVDQA	%XMM5,%XMM9

0x433128 PSLLD	$0x1f,%XMM9

0x43312e MOVMSKPS	%XMM9,%EDX

0x433132 TEST	$0x1,%DL

0x433135 JE	433141

0x433137 MOVQ	%XMM1,%RSI

0x43313c MOVSD	(%RSI),%XMM9    [10]

0x433141 TEST	$0x2,%DL

0x433144 JE	433154

0x433146 PSHUFD	$-0x12,%XMM1,%XMM1

0x43314b MOVQ	%XMM1,%RSI

0x433150 MOVHPS	(%RSI),%XMM9    [9]

0x433154 MOVDQA	-0xe0(%RBP),%XMM1    [2]

0x43315c PADDQ	%XMM14,%XMM1

0x433161 PSLLQ	$0x3,%XMM1

0x433166 PADDQ	%XMM1,%XMM10

0x43316b TEST	$0x4,%DL

0x43316e JE	433180

0x433170 MOVQ	%XMM10,%RSI

0x433175 MOVLPS	(%RSI),%XMM13    [4]

0x433179 TEST	$0x8,%DL

0x43317c JNE	433185

0x43317e JMP	433194

0x433180 TEST	$0x8,%DL

0x433183 JE	433194

0x433185 PSHUFD	$-0x12,%XMM10,%XMM1

0x43318b MOVQ	%XMM1,%RSI

0x433190 MOVHPS	(%RSI),%XMM13    [5]

0x433194 MOVDQA	-0x100(%RBP),%XMM1    [2]

0x43319c PADDQ	%XMM14,%XMM1

0x4331a1 PSLLQ	$0x3,%XMM1

0x4331a6 MOVQ	%R15,%XMM10

0x4331ab PSHUFD	$0x44,%XMM10,%XMM10

0x4331b1 PADDQ	%XMM10,%XMM1

0x4331b6 TEST	$0x1,%DL

0x4331b9 JE	4331c5

0x4331bb MOVQ	%XMM1,%RSI

0x4331c0 MOVSD	(%RSI),%XMM11    [8]

0x4331c5 TEST	$0x2,%DL

0x4331c8 JE	4331d8

0x4331ca PSHUFD	$-0x12,%XMM1,%XMM1

0x4331cf MOVQ	%XMM1,%RSI

0x4331d4 MOVHPS	(%RSI),%XMM11    [7]

0x4331d8 PADDQ	-0x3b0(%RBP),%XMM14    [2]

0x4331e1 PSLLQ	$0x3,%XMM14

0x4331e7 PADDQ	%XMM14,%XMM10

0x4331ec TEST	$0x4,%DL

0x4331ef JE	433200

0x4331f1 MOVQ	%XMM10,%RSI

0x4331f6 MOVLPS	(%RSI),%XMM14    [6]

0x4331fa JMP	433200

0x433200 PSHUFD	$0x50,%XMM5,%XMM1

0x433205 PSLLD	$0x1f,%XMM1

0x43320a PSRAD	$0x1f,%XMM1

0x43320f MOVDQA	%XMM1,%XMM7

0x433213 PANDN	-0x120(%RBP),%XMM7    [2]

0x43321b PAND	%XMM1,%XMM9

0x433220 POR	%XMM7,%XMM9

0x433225 PSHUFD	$-0x6,%XMM5,%XMM5

0x43322a PSLLD	$0x1f,%XMM5

0x43322f PSRAD	$0x1f,%XMM5

0x433234 MOVDQA	%XMM5,%XMM7

0x433238 PANDN	%XMM0,%XMM7

0x43323c PAND	%XMM5,%XMM13

0x433241 MOVDQA	%XMM13,%XMM0

0x433246 POR	%XMM7,%XMM0

0x43324a MOVDQA	%XMM0,%XMM13

0x43324f MULPD	%XMM0,%XMM13

0x433254 MOVDQA	%XMM9,-0x120(%RBP)    [2]

0x43325d MULPD	%XMM9,%XMM9

0x433262 TEST	$0x8,%DL

0x433265 JE	432fc0

0x43326b PSHUFD	$-0x12,%XMM10,%XMM7

0x433271 MOVQ	%XMM7,%RDX

0x433276 MOVHPS	(%RDX),%XMM14    [1]

0x43327a JMP	432fc0

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp: 81 - 82

--------------------------------------------------------------------------------

81:         for (int jv = j; jv <= j + 1; ++jv) {

82:           vsqrd += 0.25 * (field.xvel0(jv, kv) * field.xvel0(jv, kv) + field.yvel0(jv, kv) * field.yvel0(jv, kv));

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.28
CQA speedup if fully vectorized	4.82
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P0,
Function	field_summary(global_variables&, parallel_&) [clone .extracted]
Source	field_summary.cpp:81-82,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	medium
Unroll/vectorization loop type	peel/tail
Unroll factor	1
CQA cycles	31.83
CQA cycles if no scalar integer	31.83
CQA cycles if FP arith vectorized	24.92
CQA cycles if fully vectorized	6.60
Front-end cycles	24.67
P0 cycles	31.83
P1 cycles	31.50
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	0.50
P5 cycles	31.67
P6 cycles	10.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	10.00
P11 cycles	6.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	148.00
Nb uops	148.00
Nb loads	18.00
Nb stores	1.00
Nb stack references	8.00
FLOP/cycle	0.63
Nb FLOP add-sub	8.00
Nb FLOP mul	12.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.54
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	87.90
Vectorization ratio load	88.89
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	85.56
Vector-efficiency ratio all	22.83
Vector-efficiency ratio load	19.44
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.13

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.28
CQA speedup if fully vectorized	4.82
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P0,
Function	field_summary(global_variables&, parallel_&) [clone .extracted]
Source	field_summary.cpp:81-82,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	medium
Unroll/vectorization loop type	peel/tail
Unroll factor	1
CQA cycles	31.83
CQA cycles if no scalar integer	31.83
CQA cycles if FP arith vectorized	24.92
CQA cycles if fully vectorized	6.60
Front-end cycles	24.67
P0 cycles	31.83
P1 cycles	31.50
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	0.50
P5 cycles	31.67
P6 cycles	10.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	10.00
P11 cycles	6.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	148.00
Nb uops	148.00
Nb loads	18.00
Nb stores	1.00
Nb stack references	8.00
FLOP/cycle	0.63
Nb FLOP add-sub	8.00
Nb FLOP mul	12.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.54
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	87.90
Vectorization ratio load	88.89
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	85.56
Vector-efficiency ratio all	22.83
Vector-efficiency ratio load	19.44
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.13

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	field_summary(global_variables&, parallel_&) [clone .extracted]
Source file and lines	field_summary.cpp:81-82
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:81-82
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

It is peel/tail loop of related source loop which is unrolled by 2 (including vectorization).
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 256 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is partially vectorized. Only 22% of vector register length is used (average across all SSE/AVX instructions).

Details

87% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

88% of SSE/AVX loads are used in vector version.
85% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

MOVHPS: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

10 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

8: addition or subtraction
12: multiply

The binary loop is loading 224 bytes (28 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	148
nb uops	148
loop length	699
used x86 registers	6
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	8
ADD-SUB / MUL ratio	0.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	24.67 cycles
front end	24.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	31.83	31.50	6.00	6.00	0.50	31.67	10.00	0.50	0.50	0.50	10.00	6.00
cycles	31.83	31.50	6.00	6.00	0.50	31.67	10.00	0.50	0.50	0.50	10.00	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	24.67
Dispatch	31.83
Overall L1	31.83

Vectorization ratios

INT

all	85%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	82%

all	94%
load	77%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	87%
load	88%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

Vector efficiency ratios

INT

all	23%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	22%

all	22%
load	13%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	22%
load	19%
store	25%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 31.83 cycles. At this rate:

3% of peak load performance is reached (7.04 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.50 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4330e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PAND %XMM1,%XMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PANDN %XMM6,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM1,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
POR %XMM11,%XMM6	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PAND %XMM5,%XMM14	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PANDN %XMM2,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM5,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
POR %XMM14,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MULPD %XMM2,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
ADDPD %XMM13,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVDQA %XMM6,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MULPD %XMM6,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
ADDPD %XMM9,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVAPD 0x6843a(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MULPD %XMM7,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
ADDPD %XMM1,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MULPD %XMM7,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
ADDPD %XMM5,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVQ %RCX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PXOR 0x6b1f7(%RIP),%XMM5	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA -0x3a0(%RBP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM9,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PCMPGTD %XMM5,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
MOVDQA -0x390(%RBP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM10,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PCMPGTD %XMM5,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
PCMPEQD %XMM5,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
PCMPEQD %XMM10,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
SHUFPS $-0x23,%XMM9,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM1,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
SHUFPS $-0x78,%XMM7,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
ANDPS %XMM9,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
SHUFPS $-0x23,%XMM7,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
ORPS %XMM5,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSHUFD $-0x6,%XMM15,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLD $0x1f,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRAD $0x1f,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVAPD %XMM8,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ANDPD %XMM5,%XMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ANDNPD %XMM12,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVAPD %XMM5,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ORPD %XMM7,%XMM12	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSHUFD $0x50,%XMM15,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLD $0x1f,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRAD $0x1f,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVAPD %XMM3,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ANDPD %XMM5,%XMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ANDNPD %XMM4,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVAPD %XMM5,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ORPD %XMM7,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PAND %XMM1,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA -0x110(%RBP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM10,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PAND %XMM15,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLD $0x1f,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVMSKPS %XMM1,%EDX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	vect (25.0%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %EDX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 432de0 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xaa0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RCX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVDQA %XMM10,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PAND %XMM15,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %RDX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA -0xf0(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PADDQ %XMM14,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %R14,%XMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM9,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLQ $0x3,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM10,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM5,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSLLD $0x1f,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVMSKPS %XMM9,%EDX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	vect (25.0%)
TEST $0x1,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 433141 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xe01>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ %XMM1,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%RSI),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST $0x2,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 433154 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xe14>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
PSHUFD $-0x12,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVHPS (%RSI),%XMM9	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	vect (12.5%)
MOVDQA -0xe0(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PADDQ %XMM14,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM1,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
TEST $0x4,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 433180 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xe40>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ %XMM10,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVLPS (%RSI),%XMM13	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4-12	0.50	vect (12.5%)
TEST $0x8,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 433185 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xe45>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 433194 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xe54>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
TEST $0x8,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 433194 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xe54>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
PSHUFD $-0x12,%XMM10,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVHPS (%RSI),%XMM13	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	vect (12.5%)
MOVDQA -0x100(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PADDQ %XMM14,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R15,%XMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM10,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM10,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
TEST $0x1,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 4331c5 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xe85>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ %XMM1,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%RSI),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST $0x2,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 4331d8 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xe98>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
PSHUFD $-0x12,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVHPS (%RSI),%XMM11	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	vect (12.5%)
PADDQ -0x3b0(%RBP),%XMM14	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM14,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
TEST $0x4,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 433200 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xec0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ %XMM10,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVLPS (%RSI),%XMM14	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4-12	0.50	vect (12.5%)
JMP 433200 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xec0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
PSHUFD $0x50,%XMM5,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLD $0x1f,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRAD $0x1f,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM1,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PANDN -0x120(%RBP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PAND %XMM1,%XMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
POR %XMM7,%XMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSHUFD $-0x6,%XMM5,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLD $0x1f,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRAD $0x1f,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM5,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PANDN %XMM0,%XMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PAND %XMM5,%XMM13	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
POR %XMM7,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM0,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MULPD %XMM0,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
MOVDQA %XMM9,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MULPD %XMM9,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
TEST $0x8,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 432fc0 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xc80>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
PSHUFD $-0x12,%XMM10,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM7,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVHPS (%RDX),%XMM14	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	vect (12.5%)
JMP 432fc0 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xc80>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	field_summary(global_variables&, parallel_&) [clone .extracted]
Source file and lines	field_summary.cpp:81-82
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:81-82
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

It is peel/tail loop of related source loop which is unrolled by 2 (including vectorization).
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Unrolling/vectorization cost

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is partially vectorized. Only 22% of vector register length is used (average across all SSE/AVX instructions).

Details

87% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

88% of SSE/AVX loads are used in vector version.
85% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

MOVHPS: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

10 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

8: addition or subtraction
12: multiply

The binary loop is loading 224 bytes (28 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	148
nb uops	148
loop length	699
used x86 registers	6
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	8
ADD-SUB / MUL ratio	0.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	24.67 cycles
front end	24.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	31.83	31.50	6.00	6.00	0.50	31.67	10.00	0.50	0.50	0.50	10.00	6.00
cycles	31.83	31.50	6.00	6.00	0.50	31.67	10.00	0.50	0.50	0.50	10.00	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	24.67
Dispatch	31.83
Overall L1	31.83

Vectorization ratios

INT

all	85%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	82%

all	94%
load	77%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	87%
load	88%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

Vector efficiency ratios

INT

all	23%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	22%

all	22%
load	13%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	22%
load	19%
store	25%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 31.83 cycles. At this rate:

3% of peak load performance is reached (7.04 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.50 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4330e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PAND %XMM1,%XMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PANDN %XMM6,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM1,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
POR %XMM11,%XMM6	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PAND %XMM5,%XMM14	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PANDN %XMM2,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM5,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
POR %XMM14,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MULPD %XMM2,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
ADDPD %XMM13,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVDQA %XMM6,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MULPD %XMM6,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
ADDPD %XMM9,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVAPD 0x6843a(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MULPD %XMM7,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
ADDPD %XMM1,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MULPD %XMM7,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
ADDPD %XMM5,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVQ %RCX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PXOR 0x6b1f7(%RIP),%XMM5	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA -0x3a0(%RBP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM9,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PCMPGTD %XMM5,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
MOVDQA -0x390(%RBP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM10,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PCMPGTD %XMM5,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
PCMPEQD %XMM5,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
PCMPEQD %XMM10,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
SHUFPS $-0x23,%XMM9,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM1,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
SHUFPS $-0x78,%XMM7,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
ANDPS %XMM9,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
SHUFPS $-0x23,%XMM7,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
ORPS %XMM5,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSHUFD $-0x6,%XMM15,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLD $0x1f,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRAD $0x1f,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVAPD %XMM8,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ANDPD %XMM5,%XMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ANDNPD %XMM12,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVAPD %XMM5,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ORPD %XMM7,%XMM12	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSHUFD $0x50,%XMM15,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLD $0x1f,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRAD $0x1f,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVAPD %XMM3,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ANDPD %XMM5,%XMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ANDNPD %XMM4,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVAPD %XMM5,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ORPD %XMM7,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PAND %XMM1,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA -0x110(%RBP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM10,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PAND %XMM15,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLD $0x1f,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVMSKPS %XMM1,%EDX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	vect (25.0%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %EDX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 432de0 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xaa0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RCX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVDQA %XMM10,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PAND %XMM15,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %RDX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA -0xf0(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PADDQ %XMM14,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %R14,%XMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM9,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLQ $0x3,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM10,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM5,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSLLD $0x1f,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVMSKPS %XMM9,%EDX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	vect (25.0%)
TEST $0x1,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 433141 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xe01>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ %XMM1,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%RSI),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST $0x2,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 433154 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xe14>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
PSHUFD $-0x12,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVHPS (%RSI),%XMM9	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	vect (12.5%)
MOVDQA -0xe0(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PADDQ %XMM14,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM1,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
TEST $0x4,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 433180 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xe40>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ %XMM10,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVLPS (%RSI),%XMM13	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4-12	0.50	vect (12.5%)
TEST $0x8,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 433185 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xe45>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 433194 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xe54>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
TEST $0x8,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 433194 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xe54>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
PSHUFD $-0x12,%XMM10,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVHPS (%RSI),%XMM13	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	vect (12.5%)
MOVDQA -0x100(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PADDQ %XMM14,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R15,%XMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM10,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM10,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
TEST $0x1,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 4331c5 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xe85>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ %XMM1,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%RSI),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST $0x2,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 4331d8 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xe98>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
PSHUFD $-0x12,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVHPS (%RSI),%XMM11	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	vect (12.5%)
PADDQ -0x3b0(%RBP),%XMM14	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM14,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
TEST $0x4,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 433200 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xec0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ %XMM10,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVLPS (%RSI),%XMM14	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4-12	0.50	vect (12.5%)
JMP 433200 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xec0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
PSHUFD $0x50,%XMM5,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLD $0x1f,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRAD $0x1f,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM1,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PANDN -0x120(%RBP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PAND %XMM1,%XMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
POR %XMM7,%XMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSHUFD $-0x6,%XMM5,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLD $0x1f,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRAD $0x1f,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM5,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PANDN %XMM0,%XMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PAND %XMM5,%XMM13	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
POR %XMM7,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM0,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MULPD %XMM0,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
MOVDQA %XMM9,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MULPD %XMM9,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
TEST $0x8,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 432fc0 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xc80>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
PSHUFD $-0x12,%XMM10,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM7,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVHPS (%RDX),%XMM14	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	vect (12.5%)
JMP 432fc0 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xc80>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code