OV - exec - Loop 216

	Loop Id: 216	Module: exec	Source: field_summary.cpp:80-82 [...]	Coverage: 0.05%

0x432de0 INC	%RAX

0x432de3 MOVQ	%RAX,%XMM1

0x432de8 PSHUFD	$0x44,%XMM1,%XMM1

0x432ded PXOR	0x6b42b(%RIP),%XMM1

0x432df5 MOVDQA	-0x340(%RBP),%XMM8

0x432dfe MOVDQA	%XMM8,%XMM5

0x432e03 PCMPGTD	%XMM1,%XMM5

0x432e07 MOVDQA	-0x330(%RBP),%XMM9

0x432e10 MOVDQA	%XMM9,%XMM3

0x432e15 PCMPGTD	%XMM1,%XMM3

0x432e19 MOVDQA	%XMM3,%XMM7

0x432e1d SHUFPS	$-0x78,%XMM5,%XMM7

0x432e21 PCMPEQD	%XMM1,%XMM8

0x432e26 PCMPEQD	%XMM9,%XMM1

0x432e2b SHUFPS	$-0x23,%XMM8,%XMM1

0x432e30 ANDPS	%XMM7,%XMM1

0x432e33 SHUFPS	$-0x23,%XMM5,%XMM3

0x432e37 ORPS	%XMM1,%XMM3

0x432e3a MOVAPD	-0x380(%RBP),%XMM7

0x432e42 MOVAPD	-0x370(%RBP),%XMM9

0x432e4b PSHUFD	$-0x6,%XMM10,%XMM1

0x432e51 PSLLD	$0x1f,%XMM1

0x432e56 PSRAD	$0x1f,%XMM1

0x432e5b MOVAPD	%XMM12,%XMM5

0x432e60 ANDPD	%XMM1,%XMM5

0x432e64 ANDNPD	%XMM9,%XMM1

0x432e69 MOVAPD	%XMM1,%XMM9

0x432e6e ORPD	%XMM5,%XMM9

0x432e73 PSHUFD	$0x50,%XMM10,%XMM1

0x432e79 PSLLD	$0x1f,%XMM1

0x432e7e PSRAD	$0x1f,%XMM1

0x432e83 MOVAPD	%XMM4,%XMM5

0x432e87 ANDPD	%XMM1,%XMM5

0x432e8b ANDNPD	%XMM7,%XMM1

0x432e8f MOVAPD	%XMM1,%XMM7

0x432e93 ORPD	%XMM5,%XMM7

0x432e97 PAND	%XMM3,%XMM10

0x432e9c MOVDQA	%XMM10,%XMM1

0x432ea1 PSLLD	$0x1f,%XMM1

0x432ea6 MOVMSKPS	%XMM1,%ECX

0x432ea9 MOVAPD	%XMM4,%XMM3

0x432ead MOVAPD	%XMM12,%XMM8

0x432eb2 TEST	%ECX,%ECX

0x432eb4 JE	432590

0x432eba MOVDQA	%XMM10,%XMM1

0x432ebf PSLLD	$0x1f,%XMM1

0x432ec4 MOVMSKPS	%XMM1,%ECX

0x432ec7 TEST	%ECX,%ECX

0x432ec9 JE	433280

0x432ecf MOVAPS	%XMM9,-0x370(%RBP)

0x432ed7 MOVAPS	%XMM7,-0x380(%RBP)

0x432ede MOVQ	%RAX,%XMM1

0x432ee3 PSHUFD	$0x44,%XMM1,%XMM9

0x432ee9 MOVDQA	-0x320(%RBP),%XMM1

0x432ef1 PMULUDQ	%XMM9,%XMM1

0x432ef6 MOVDQA	%XMM9,%XMM4

0x432efb PSRLQ	$0x20,%XMM4

0x432f00 MOVDQA	-0x190(%RBP),%XMM7

0x432f08 MOVDQA	%XMM7,%XMM5

0x432f0c PMULUDQ	%XMM4,%XMM5

0x432f10 PADDQ	%XMM1,%XMM5

0x432f14 PSLLQ	$0x20,%XMM5

0x432f19 PMULUDQ	%XMM9,%XMM7

0x432f1e PADDQ	%XMM5,%XMM7

0x432f22 MOVDQA	-0x310(%RBP),%XMM1

0x432f2a PADDQ	%XMM7,%XMM1

0x432f2e MOVDQA	%XMM1,-0xe0(%RBP)

0x432f36 PADDQ	-0x300(%RBP),%XMM7

0x432f3e MOVDQA	%XMM7,-0xf0(%RBP)

0x432f46 MOVDQA	-0x2f0(%RBP),%XMM1

0x432f4e PMULUDQ	%XMM9,%XMM1

0x432f53 MOVDQA	-0x180(%RBP),%XMM5

0x432f5b PMULUDQ	%XMM5,%XMM4

0x432f5f PADDQ	%XMM1,%XMM4

0x432f63 PSLLQ	$0x20,%XMM4

0x432f68 PMULUDQ	%XMM5,%XMM9

0x432f6d PADDQ	%XMM4,%XMM9

0x432f72 MOVDQA	-0x360(%RBP),%XMM1

0x432f7a PADDQ	%XMM9,%XMM1

0x432f7f MOVDQA	%XMM1,-0x3b0(%RBP)

0x432f87 PADDQ	-0x350(%RBP),%XMM9

0x432f90 MOVDQA	%XMM9,-0x100(%RBP)

0x432f99 MOV	$0x1,%ECX

0x432f9e MOVDQA	0x68209(%RIP),%XMM15

0x432fa7 MOVDQA	%XMM10,-0x110(%RBP)

0x432fb0 JMP	4330e8

  (217) 0x432fc0 PAND	%XMM1,%XMM11

  (217) 0x432fc5 PANDN	%XMM6,%XMM1

  (217) 0x432fc9 MOVDQA	%XMM1,%XMM6

  (217) 0x432fcd POR	%XMM11,%XMM6

  (217) 0x432fd2 PAND	%XMM5,%XMM14

  (217) 0x432fd7 PANDN	%XMM2,%XMM5

  (217) 0x432fdb MOVDQA	%XMM5,%XMM2

  (217) 0x432fdf POR	%XMM14,%XMM2

  (217) 0x432fe4 MOVDQA	%XMM2,%XMM1

  (217) 0x432fe8 MULPD	%XMM2,%XMM1

  (217) 0x432fec ADDPD	%XMM13,%XMM1

  (217) 0x432ff1 MOVDQA	%XMM6,%XMM5

  (217) 0x432ff5 MULPD	%XMM6,%XMM5

  (217) 0x432ff9 ADDPD	%XMM9,%XMM5

  (217) 0x432ffe MOVAPD	0x6843a(%RIP),%XMM7

  (217) 0x433006 MULPD	%XMM7,%XMM1

  (217) 0x43300a ADDPD	%XMM1,%XMM8

  (217) 0x43300f MULPD	%XMM7,%XMM5

  (217) 0x433013 ADDPD	%XMM5,%XMM3

  (217) 0x433017 MOVQ	%RCX,%XMM1

  (217) 0x43301c PSHUFD	$0x44,%XMM1,%XMM5

  (217) 0x433021 PXOR	0x6b1f7(%RIP),%XMM5

  (217) 0x433029 MOVDQA	-0x3a0(%RBP),%XMM9

  (217) 0x433032 MOVDQA	%XMM9,%XMM7

  (217) 0x433037 PCMPGTD	%XMM5,%XMM7

  (217) 0x43303b MOVDQA	-0x390(%RBP),%XMM10

  (217) 0x433044 MOVDQA	%XMM10,%XMM1

  (217) 0x433049 PCMPGTD	%XMM5,%XMM1

  (217) 0x43304d PCMPEQD	%XMM5,%XMM9

  (217) 0x433052 PCMPEQD	%XMM10,%XMM5

  (217) 0x433057 SHUFPS	$-0x23,%XMM9,%XMM5

  (217) 0x43305c MOVDQA	%XMM1,%XMM9

  (217) 0x433061 SHUFPS	$-0x78,%XMM7,%XMM9

  (217) 0x433066 ANDPS	%XMM9,%XMM5

  (217) 0x43306a SHUFPS	$-0x23,%XMM7,%XMM1

  (217) 0x43306e ORPS	%XMM5,%XMM1

  (217) 0x433071 PSHUFD	$-0x6,%XMM15,%XMM5

  (217) 0x433077 PSLLD	$0x1f,%XMM5

  (217) 0x43307c PSRAD	$0x1f,%XMM5

  (217) 0x433081 MOVAPD	%XMM8,%XMM7

  (217) 0x433086 ANDPD	%XMM5,%XMM7

  (217) 0x43308a ANDNPD	%XMM12,%XMM5

  (217) 0x43308f MOVAPD	%XMM5,%XMM12

  (217) 0x433094 ORPD	%XMM7,%XMM12

  (217) 0x433099 PSHUFD	$0x50,%XMM15,%XMM5

  (217) 0x43309f PSLLD	$0x1f,%XMM5

  (217) 0x4330a4 PSRAD	$0x1f,%XMM5

  (217) 0x4330a9 MOVAPD	%XMM3,%XMM7

  (217) 0x4330ad ANDPD	%XMM5,%XMM7

  (217) 0x4330b1 ANDNPD	%XMM4,%XMM5

  (217) 0x4330b5 MOVAPD	%XMM5,%XMM4

  (217) 0x4330b9 ORPD	%XMM7,%XMM4

  (217) 0x4330bd PAND	%XMM1,%XMM15

  (217) 0x4330c2 MOVDQA	-0x110(%RBP),%XMM10

  (217) 0x4330cb MOVDQA	%XMM10,%XMM1

  (217) 0x4330d0 PAND	%XMM15,%XMM1

  (217) 0x4330d5 PSLLD	$0x1f,%XMM1

  (217) 0x4330da MOVMSKPS	%XMM1,%EDX

  (217) 0x4330dd INC	%RCX

  (217) 0x4330e0 TEST	%EDX,%EDX

  (217) 0x4330e2 JE	432de0

  (217) 0x4330e8 LEA	-0x1(%RCX),%RDX

  (217) 0x4330ec MOVDQA	%XMM10,%XMM5

  (217) 0x4330f1 PAND	%XMM15,%XMM5

  (217) 0x4330f6 MOVQ	%RDX,%XMM1

  (217) 0x4330fb PSHUFD	$0x44,%XMM1,%XMM14

  (217) 0x433101 MOVDQA	-0xf0(%RBP),%XMM1

  (217) 0x433109 PADDQ	%XMM14,%XMM1

  (217) 0x43310e MOVQ	%R14,%XMM9

  (217) 0x433113 PSHUFD	$0x44,%XMM9,%XMM10

  (217) 0x433119 PSLLQ	$0x3,%XMM1

  (217) 0x43311e PADDQ	%XMM10,%XMM1

  (217) 0x433123 MOVDQA	%XMM5,%XMM9

  (217) 0x433128 PSLLD	$0x1f,%XMM9

  (217) 0x43312e MOVMSKPS	%XMM9,%EDX

  (217) 0x433132 TEST	$0x1,%DL

  (217) 0x433135 JE	433141

  (217) 0x433137 MOVQ	%XMM1,%RSI

  (217) 0x43313c MOVSD	(%RSI),%XMM9

  (217) 0x433141 TEST	$0x2,%DL

  (217) 0x433144 JE	433154

  (217) 0x433146 PSHUFD	$-0x12,%XMM1,%XMM1

  (217) 0x43314b MOVQ	%XMM1,%RSI

  (217) 0x433150 MOVHPS	(%RSI),%XMM9

  (217) 0x433154 MOVDQA	-0xe0(%RBP),%XMM1

  (217) 0x43315c PADDQ	%XMM14,%XMM1

  (217) 0x433161 PSLLQ	$0x3,%XMM1

  (217) 0x433166 PADDQ	%XMM1,%XMM10

  (217) 0x43316b TEST	$0x4,%DL

  (217) 0x43316e JE	433180

  (217) 0x433170 MOVQ	%XMM10,%RSI

  (217) 0x433175 MOVLPS	(%RSI),%XMM13

  (217) 0x433179 TEST	$0x8,%DL

  (217) 0x43317c JNE	433185

  (217) 0x43317e JMP	433194

  (217) 0x433180 TEST	$0x8,%DL

  (217) 0x433183 JE	433194

  (217) 0x433185 PSHUFD	$-0x12,%XMM10,%XMM1

  (217) 0x43318b MOVQ	%XMM1,%RSI

  (217) 0x433190 MOVHPS	(%RSI),%XMM13

  (217) 0x433194 MOVDQA	-0x100(%RBP),%XMM1

  (217) 0x43319c PADDQ	%XMM14,%XMM1

  (217) 0x4331a1 PSLLQ	$0x3,%XMM1

  (217) 0x4331a6 MOVQ	%R15,%XMM10

  (217) 0x4331ab PSHUFD	$0x44,%XMM10,%XMM10

  (217) 0x4331b1 PADDQ	%XMM10,%XMM1

  (217) 0x4331b6 TEST	$0x1,%DL

  (217) 0x4331b9 JE	4331c5

  (217) 0x4331bb MOVQ	%XMM1,%RSI

  (217) 0x4331c0 MOVSD	(%RSI),%XMM11

  (217) 0x4331c5 TEST	$0x2,%DL

  (217) 0x4331c8 JE	4331d8

  (217) 0x4331ca PSHUFD	$-0x12,%XMM1,%XMM1

  (217) 0x4331cf MOVQ	%XMM1,%RSI

  (217) 0x4331d4 MOVHPS	(%RSI),%XMM11

  (217) 0x4331d8 PADDQ	-0x3b0(%RBP),%XMM14

  (217) 0x4331e1 PSLLQ	$0x3,%XMM14

  (217) 0x4331e7 PADDQ	%XMM14,%XMM10

  (217) 0x4331ec TEST	$0x4,%DL

  (217) 0x4331ef JE	433200

  (217) 0x4331f1 MOVQ	%XMM10,%RSI

  (217) 0x4331f6 MOVLPS	(%RSI),%XMM14

  (217) 0x4331fa JMP	433200

  (217) 0x433200 PSHUFD	$0x50,%XMM5,%XMM1

  (217) 0x433205 PSLLD	$0x1f,%XMM1

  (217) 0x43320a PSRAD	$0x1f,%XMM1

  (217) 0x43320f MOVDQA	%XMM1,%XMM7

  (217) 0x433213 PANDN	-0x120(%RBP),%XMM7

  (217) 0x43321b PAND	%XMM1,%XMM9

  (217) 0x433220 POR	%XMM7,%XMM9

  (217) 0x433225 PSHUFD	$-0x6,%XMM5,%XMM5

  (217) 0x43322a PSLLD	$0x1f,%XMM5

  (217) 0x43322f PSRAD	$0x1f,%XMM5

  (217) 0x433234 MOVDQA	%XMM5,%XMM7

  (217) 0x433238 PANDN	%XMM0,%XMM7

  (217) 0x43323c PAND	%XMM5,%XMM13

  (217) 0x433241 MOVDQA	%XMM13,%XMM0

  (217) 0x433246 POR	%XMM7,%XMM0

  (217) 0x43324a MOVDQA	%XMM0,%XMM13

  (217) 0x43324f MULPD	%XMM0,%XMM13

  (217) 0x433254 MOVDQA	%XMM9,-0x120(%RBP)

  (217) 0x43325d MULPD	%XMM9,%XMM9

  (217) 0x433262 TEST	$0x8,%DL

  (217) 0x433265 JE	432fc0

  (217) 0x43326b PSHUFD	$-0x12,%XMM10,%XMM7

  (217) 0x433271 MOVQ	%XMM7,%RDX

  (217) 0x433276 MOVHPS	(%RDX),%XMM14

  (217) 0x43327a JMP	432fc0

0x433280 PXOR	%XMM4,%XMM4

0x433284 PXOR	%XMM12,%XMM12

0x433289 XOR	%EAX,%EAX

0x43328b XORPD	%XMM3,%XMM3

0x43328f JMP	432e4b

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp: 80 - 82

--------------------------------------------------------------------------------

80:       for (int kv = k; kv <= k + 1; ++kv) {

81:         for (int jv = j; jv <= j + 1; ++jv) {

82:           vsqrd += 0.25 * (field.xvel0(jv, kv) * field.xvel0(jv, kv) + field.yvel0(jv, kv) * field.yvel0(jv, kv));

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.83
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P0, P1, P5,
Function	field_summary(global_variables&, parallel_&) [clone .extracted]
Source	field_summary.cpp:80-82
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	3.31
Front-end cycles	15.17
P0 cycles	16.00
P1 cycles	16.00
P2 cycles	4.67
P3 cycles	4.67
P4 cycles	3.50
P5 cycles	16.00
P6 cycles	2.40
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	2.60
P11 cycles	4.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	91.00
Nb uops	91.00
Nb loads	14.00
Nb stores	7.00
Nb stack references	17.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.00
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	112.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	94.12
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	88.89
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	92.31
Vector-efficiency ratio all	23.24
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	23.61
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.80

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.83
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P0, P1, P5,
Function	field_summary(global_variables&, parallel_&) [clone .extracted]
Source	field_summary.cpp:80-82
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	3.31
Front-end cycles	15.17
P0 cycles	16.00
P1 cycles	16.00
P2 cycles	4.67
P3 cycles	4.67
P4 cycles	3.50
P5 cycles	16.00
P6 cycles	2.40
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	2.60
P11 cycles	4.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	91.00
Nb uops	91.00
Nb loads	14.00
Nb stores	7.00
Nb stack references	17.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.00
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	112.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	94.12
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	88.89
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	92.31
Vector-efficiency ratio all	23.24
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	23.61
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.80

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	field_summary(global_variables&, parallel_&) [clone .extracted]
Source file and lines	field_summary.cpp:80-82
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:80-82
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:80-82.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 257 paths individually, rerun with max-paths=257
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 257 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 23% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 16.00 to 3.31 cycles (4.83x speedup).

Details

94% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

88% of SSE/AVX addition or subtraction instructions are used in vector version.
92% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 224 bytes. The binary loop is storing 112 bytes.

General properties

nb instructions	91
nb uops	91
loop length	489
used x86 registers	3
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.17 cycles
front end	15.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	16.00	16.00	4.67	4.67	3.50	16.00	2.40	3.50	3.50	3.50	2.60	4.67
cycles	16.00	16.00	4.67	4.67	3.50	16.00	2.40	3.50	3.50	3.50	2.60	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.17
Dispatch	16.00
Overall L1	16.00

Vectorization ratios

INT

all	91%
load	100%
store	100%
mul	100%
add-sub	88%
fma	NA (no fma vectorizable/vectorized instructions)
other	87%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	94%
load	100%
store	100%
mul	100%
add-sub	88%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	92%

Vector efficiency ratios

INT

all	22%
load	25%
store	25%
mul	12%
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
other	23%

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	23%
load	25%
store	25%
mul	12%
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

7% of peak load performance is reached (14.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 432eba

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVQ %RAX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PXOR 0x6b42b(%RIP),%XMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA -0x340(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM8,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PCMPGTD %XMM1,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
MOVDQA -0x330(%RBP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM9,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PCMPGTD %XMM1,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM3,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
SHUFPS $-0x78,%XMM5,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PCMPEQD %XMM1,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
PCMPEQD %XMM9,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
SHUFPS $-0x23,%XMM8,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
ANDPS %XMM7,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
SHUFPS $-0x23,%XMM5,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
ORPS %XMM1,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVAPD -0x380(%RBP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVAPD -0x370(%RBP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PSHUFD $-0x6,%XMM10,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLD $0x1f,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRAD $0x1f,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVAPD %XMM12,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ANDPD %XMM1,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ANDNPD %XMM9,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVAPD %XMM1,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ORPD %XMM5,%XMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSHUFD $0x50,%XMM10,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLD $0x1f,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRAD $0x1f,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVAPD %XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ANDPD %XMM1,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ANDNPD %XMM7,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVAPD %XMM1,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ORPD %XMM5,%XMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PAND %XMM3,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM10,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSLLD $0x1f,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVMSKPS %XMM1,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	vect (25.0%)
MOVAPD %XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVAPD %XMM12,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
TEST %ECX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 432590 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0x250>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVDQA %XMM10,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSLLD $0x1f,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVMSKPS %XMM1,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	vect (25.0%)
TEST %ECX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 433280 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xf40>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVAPS %XMM9,-0x370(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVAPS %XMM7,-0x380(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RAX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA -0x320(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PMULUDQ %XMM9,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM9,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA -0x190(%RBP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM7,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM4,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM1,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM9,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM5,%XMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA -0x310(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PADDQ %XMM7,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM1,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PADDQ -0x300(%RBP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOVDQA %XMM7,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA -0x2f0(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PMULUDQ %XMM9,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA -0x180(%RBP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PMULUDQ %XMM5,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM1,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM5,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM4,%XMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA -0x360(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PADDQ %XMM9,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM1,-0x3b0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PADDQ -0x350(%RBP),%XMM9	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOVDQA %XMM9,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVDQA 0x68209(%RIP),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM10,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
JMP 4330e8 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xda8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
PXOR %XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PXOR %XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
XORPD %XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 432e4b <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xb0b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	field_summary(global_variables&, parallel_&) [clone .extracted]
Source file and lines	field_summary.cpp:80-82
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:80-82
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:80-82.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 257 paths individually, rerun with max-paths=257
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

94% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

88% of SSE/AVX addition or subtraction instructions are used in vector version.
92% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 224 bytes. The binary loop is storing 112 bytes.

General properties

nb instructions	91
nb uops	91
loop length	489
used x86 registers	3
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.17 cycles
front end	15.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	16.00	16.00	4.67	4.67	3.50	16.00	2.40	3.50	3.50	3.50	2.60	4.67
cycles	16.00	16.00	4.67	4.67	3.50	16.00	2.40	3.50	3.50	3.50	2.60	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.17
Dispatch	16.00
Overall L1	16.00

Vectorization ratios

INT

all	91%
load	100%
store	100%
mul	100%
add-sub	88%
fma	NA (no fma vectorizable/vectorized instructions)
other	87%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	94%
load	100%
store	100%
mul	100%
add-sub	88%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	92%

Vector efficiency ratios

INT

all	22%
load	25%
store	25%
mul	12%
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
other	23%

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	23%
load	25%
store	25%
mul	12%
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

7% of peak load performance is reached (14.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 432eba

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVQ %RAX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PXOR 0x6b42b(%RIP),%XMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA -0x340(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM8,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PCMPGTD %XMM1,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
MOVDQA -0x330(%RBP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM9,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PCMPGTD %XMM1,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM3,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
SHUFPS $-0x78,%XMM5,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PCMPEQD %XMM1,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
PCMPEQD %XMM9,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
SHUFPS $-0x23,%XMM8,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
ANDPS %XMM7,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
SHUFPS $-0x23,%XMM5,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
ORPS %XMM1,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVAPD -0x380(%RBP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVAPD -0x370(%RBP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PSHUFD $-0x6,%XMM10,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLD $0x1f,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRAD $0x1f,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVAPD %XMM12,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ANDPD %XMM1,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ANDNPD %XMM9,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVAPD %XMM1,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ORPD %XMM5,%XMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSHUFD $0x50,%XMM10,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLD $0x1f,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRAD $0x1f,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVAPD %XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ANDPD %XMM1,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ANDNPD %XMM7,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVAPD %XMM1,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ORPD %XMM5,%XMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PAND %XMM3,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM10,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSLLD $0x1f,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVMSKPS %XMM1,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	vect (25.0%)
MOVAPD %XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVAPD %XMM12,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
TEST %ECX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 432590 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0x250>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVDQA %XMM10,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSLLD $0x1f,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVMSKPS %XMM1,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	vect (25.0%)
TEST %ECX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 433280 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xf40>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVAPS %XMM9,-0x370(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVAPS %XMM7,-0x380(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RAX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA -0x320(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PMULUDQ %XMM9,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM9,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA -0x190(%RBP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM7,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM4,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM1,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM9,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM5,%XMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA -0x310(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PADDQ %XMM7,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM1,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PADDQ -0x300(%RBP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOVDQA %XMM7,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA -0x2f0(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PMULUDQ %XMM9,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA -0x180(%RBP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PMULUDQ %XMM5,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM1,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM5,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM4,%XMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA -0x360(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PADDQ %XMM9,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM1,-0x3b0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PADDQ -0x350(%RBP),%XMM9	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOVDQA %XMM9,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVDQA 0x68209(%RIP),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM10,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
JMP 4330e8 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xda8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
PXOR %XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PXOR %XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
XORPD %XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 432e4b <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xb0b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code