OV - exec - Loop 178

	Loop Id: 178	Module: exec	Source: advec_mom.cpp:72-76 [...]	Coverage: 1.96%

0x425ab0 MOVQ	%XMM7,%RAX

0x425ab5 XOR	%EDX,%EDX

0x425ab7 DIV	%R8

0x425aba MOV	%RAX,%RSI

0x425abd PSHUFD	$-0x12,%XMM7,%XMM1

0x425ac2 MOVQ	%XMM1,%RAX

0x425ac7 XOR	%EDX,%EDX

0x425ac9 DIV	%R10

0x425acc MOVQ	%RSI,%XMM1

0x425ad1 MOVQ	%RAX,%XMM4

0x425ad6 PUNPCKLQDQ	%XMM4,%XMM1

0x425ada MOVDQA	%XMM1,%XMM12

0x425adf PADDQ	-0xe0(%RBP),%XMM12    [6]

0x425ae8 PMULUDQ	-0xf0(%RBP),%XMM1    [6]

0x425af0 MOVDQA	%XMM7,%XMM4

0x425af4 PSUBQ	%XMM1,%XMM4

0x425af8 PSHUFD	$-0x18,%XMM4,%XMM15

0x425afe PXOR	%XMM4,%XMM4

0x425b02 PSHUFD	$-0x18,%XMM12,%XMM1

0x425b08 PADDD	-0xd0(%RBP),%XMM15    [6]

0x425b11 PSLLQ	$0x20,%XMM12

0x425b17 PSRAD	$0x1f,%XMM12

0x425b1d PSHUFD	$-0x13,%XMM12,%XMM5

0x425b23 PCMPGTD	%XMM15,%XMM4

0x425b28 PUNPCKLDQ	%XMM5,%XMM1

0x425b2c MOVDQA	%XMM3,%XMM5

0x425b30 PMULUDQ	%XMM1,%XMM5

0x425b34 MOVDQA	%XMM15,%XMM14

0x425b39 MOVDQA	%XMM8,%XMM10

0x425b3e PMULUDQ	%XMM1,%XMM10

0x425b43 PSRLQ	$0x20,%XMM12

0x425b49 PUNPCKLDQ	%XMM4,%XMM14

0x425b4e MOVDQA	%XMM3,%XMM4

0x425b52 PMULUDQ	%XMM12,%XMM4

0x425b57 PADDQ	%XMM10,%XMM4

0x425b5c PSLLQ	$0x20,%XMM4

0x425b61 PADDQ	%XMM14,%XMM5

0x425b66 PADDQ	%XMM4,%XMM5

0x425b6a MOVDQA	%XMM2,%XMM4

0x425b6e PSLLQ	$0x3,%XMM5

0x425b73 PMULUDQ	%XMM1,%XMM4

0x425b77 MOVDQA	%XMM11,%XMM9

0x425b7c PMULUDQ	%XMM1,%XMM9

0x425b81 PADDQ	-0xc0(%RBP),%XMM5    [6]

0x425b89 MOVDQA	%XMM2,%XMM10

0x425b8e PMULUDQ	%XMM12,%XMM10

0x425b93 PADDQ	%XMM9,%XMM10

0x425b98 MOVQ	%XMM5,%RAX

0x425b9d PADDQ	%XMM14,%XMM4

0x425ba2 PSUBD	0x75a15(%RIP),%XMM15    [9]

0x425bab PXOR	%XMM9,%XMM9

0x425bb0 PSHUFD	$-0x12,%XMM5,%XMM5

0x425bb5 PCMPGTD	%XMM15,%XMM9

0x425bba PUNPCKLDQ	%XMM9,%XMM15

0x425bbf MOVDQA	%XMM0,%XMM9

0x425bc4 MOVQ	%XMM5,%RDX

0x425bc9 PMULUDQ	%XMM1,%XMM9

0x425bce MOVDQA	%XMM13,%XMM5

0x425bd3 PMULUDQ	%XMM12,%XMM5

0x425bd8 PSLLQ	$0x20,%XMM10

0x425bde PADDQ	%XMM9,%XMM5

0x425be3 MOVDQA	%XMM13,%XMM9

0x425be8 PMULUDQ	%XMM1,%XMM9

0x425bed PADDQ	%XMM10,%XMM4

0x425bf2 PSLLQ	$0x20,%XMM5

0x425bf7 PADDQ	%XMM9,%XMM5

0x425bfc PADDQ	%XMM5,%XMM15

0x425c01 PSLLQ	$0x3,%XMM15

0x425c07 MOVQ	%R12,%XMM9

0x425c0c PSHUFD	$0x44,%XMM9,%XMM9

0x425c12 PADDQ	%XMM14,%XMM5

0x425c17 PADDQ	%XMM9,%XMM15

0x425c1c PSLLQ	$0x3,%XMM5

0x425c21 MOVDQA	%XMM6,%XMM10

0x425c26 PMULUDQ	%XMM1,%XMM10

0x425c2b PADDQ	%XMM9,%XMM5

0x425c30 MOVDQA	%XMM6,%XMM9

0x425c35 PSRLQ	$0x20,%XMM9

0x425c3b PMULUDQ	%XMM1,%XMM9

0x425c40 PSLLQ	$0x3,%XMM4

0x425c45 PADDQ	-0xb0(%RBP),%XMM4    [6]

0x425c4d MOVQ	%XMM4,%RSI

0x425c52 PSHUFD	$-0x12,%XMM4,%XMM1

0x425c57 MOVQ	%XMM1,%R13

0x425c5c PMULUDQ	%XMM6,%XMM12

0x425c61 PADDQ	%XMM9,%XMM12

0x425c66 PADDQ	%XMM14,%XMM10

0x425c6b PSLLQ	$0x20,%XMM12

0x425c71 PADDQ	%XMM12,%XMM10

0x425c76 MOVQ	%R14,%XMM1

0x425c7b PSHUFD	$0x44,%XMM1,%XMM1

0x425c80 PSLLQ	$0x3,%XMM10

0x425c86 PADDQ	%XMM10,%XMM1

0x425c8b MOVQ	%XMM15,%R15

0x425c90 PSHUFD	$-0x12,%XMM15,%XMM4

0x425c96 MOVQ	%XMM4,%RBX

0x425c9b MOVSD	(%RAX),%XMM4    [5]

0x425c9f MOVQ	%XMM5,%RAX

0x425ca4 PSHUFD	$-0x12,%XMM5,%XMM5

0x425ca9 MOVQ	%XMM5,%RDI

0x425cae MOVSD	(%RDX),%XMM5    [12]

0x425cb2 MOVSD	%XMM4,(%RSI)    [3]

0x425cb6 MOVSD	%XMM5,(%R13)    [7]

0x425cbc UNPCKLPD	%XMM5,%XMM4

0x425cc0 MOVSD	(%R15),%XMM5    [10]

0x425cc5 MOVHPD	(%RBX),%XMM5    [11]

0x425cc9 ADDPD	%XMM4,%XMM5

0x425ccd MOVSD	(%RAX),%XMM4    [4]

0x425cd1 MOVHPD	(%RDI),%XMM4    [2]

0x425cd5 SUBPD	%XMM4,%XMM5

0x425cd9 MOVQ	%XMM1,%RAX

0x425cde PSHUFD	$-0x12,%XMM1,%XMM1

0x425ce3 MOVQ	%XMM1,%RDX

0x425ce8 MOVLPD	%XMM5,(%RAX)    [1]

0x425cec MOVHPD	%XMM5,(%RDX)    [8]

0x425cf0 PADDQ	0x75758(%RIP),%XMM7    [9]

0x425cf8 ADD	$0x2,%R11

0x425cfc CMP	%R9,%R11

0x425cff JB	425ab0

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 72 - 76

--------------------------------------------------------------------------------

72:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

73:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

74:         post_vol(i, j) = volume(i, j);

75:         pre_vol(i, j) = post_vol(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

76:       }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►99.98+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.06
CQA speedup if FP arith vectorized	1.17
CQA speedup if fully vectorized	3.10
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.48
Bottlenecks	P0, P1, P5,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .extracted.42]
Source	advec_mom.cpp:72-76,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	31.00
CQA cycles if no scalar integer	29.17
CQA cycles if FP arith vectorized	26.50
CQA cycles if fully vectorized	10.00
Front-end cycles	21.00
P0 cycles	31.00
P1 cycles	31.00
P2 cycles	4.33
P3 cycles	4.33
P4 cycles	2.00
P5 cycles	31.00
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	4.33
DIV/SQRT cycles	20.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	119.00
Nb uops	126.00
Nb loads	13.00
Nb stores	4.00
Nb stack references	5.00
FLOP/cycle	0.13
Nb FLOP add-sub	4.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.19
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	32.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	10.00
Stride indirect	0.00
Vectorization ratio all	73.45
Vectorization ratio load	53.85
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	71.43
Vector-efficiency ratio all	19.91
Vector-efficiency ratio load	18.27
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	20.83

Metric	Value
CQA speedup if no scalar integer	1.06
CQA speedup if FP arith vectorized	1.17
CQA speedup if fully vectorized	3.10
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.48
Bottlenecks	P0, P1, P5,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .extracted.42]
Source	advec_mom.cpp:72-76,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	31.00
CQA cycles if no scalar integer	29.17
CQA cycles if FP arith vectorized	26.50
CQA cycles if fully vectorized	10.00
Front-end cycles	21.00
P0 cycles	31.00
P1 cycles	31.00
P2 cycles	4.33
P3 cycles	4.33
P4 cycles	2.00
P5 cycles	31.00
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	4.33
DIV/SQRT cycles	20.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	119.00
Nb uops	126.00
Nb loads	13.00
Nb stores	4.00
Nb stack references	5.00
FLOP/cycle	0.13
Nb FLOP add-sub	4.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.19
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	32.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	10.00
Stride indirect	0.00
Vectorization ratio all	73.45
Vectorization ratio load	53.85
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	71.43
Vector-efficiency ratio all	19.91
Vector-efficiency ratio load	18.27
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	20.83

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .extracted.42]
Source file and lines	advec_mom.cpp:72-76
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72-76
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 31.00 to 29.17 cycles (1.06x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 19% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 31.00 to 10.00 cycles (3.10x speedup).

Details

73% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

53% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
71% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 31.00 to 21.00 cycles (1.48x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 10 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 3 suboptimal vector unaligned load/store instructions.

Details

MOVHPD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:75
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:75
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:75

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 4 FP arithmetical operations:

4: addition or subtraction

The binary loop is loading 160 bytes (20 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	119
nb uops	126
loop length	597
used x86 registers	14
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	21.00 cycles
front end	21.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	31.00	31.00	4.33	4.33	2.00	31.00	1.00	2.00	2.00	2.00	0.00	4.33
cycles	31.00	31.00	4.33	4.33	2.00	31.00	1.00	2.00	2.00	2.00	0.00	4.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	20.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	21.00
Dispatch	31.00
DIV/SQRT	20.00
Data deps.	1.00
Overall L1	31.00

Vectorization ratios

INT

all	81%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	70%

all	15%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	73%
load	53%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	71%

Vector efficiency ratios

INT

all	20%
load	23%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	14%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	19%
load	18%
store	12%
mul	12%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 31.00 cycles. At this rate:

2% of peak load performance is reached (5.16 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.03 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 425ab0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOVQ %XMM7,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R8	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PSHUFD $-0x12,%XMM7,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R10	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOVQ %RSI,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
MOVQ %RAX,%XMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PUNPCKLQDQ %XMM4,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM1,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PADDQ -0xe0(%RBP),%XMM12	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PMULUDQ -0xf0(%RBP),%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	5	0.50	vect (12.5%)
MOVDQA %XMM7,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSUBQ %XMM1,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
PSHUFD $-0x18,%XMM4,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PXOR %XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSHUFD $-0x18,%XMM12,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDD -0xd0(%RBP),%XMM15	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRAD $0x1f,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSHUFD $-0x13,%XMM12,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PCMPGTD %XMM15,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
PUNPCKLDQ %XMM5,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOVDQA %XMM3,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM1,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM15,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVDQA %XMM8,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM1,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSRLQ $0x20,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PUNPCKLDQ %XMM4,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOVDQA %XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM12,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM10,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM14,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM4,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSLLQ $0x3,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM1,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM11,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM1,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ -0xc0(%RBP),%XMM5	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOVDQA %XMM2,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM12,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM9,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM5,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PADDQ %XMM14,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSUBD 0x75a15(%RIP),%XMM15	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PXOR %XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSHUFD $-0x12,%XMM5,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PCMPGTD %XMM15,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
PUNPCKLDQ %XMM9,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOVDQA %XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVQ %XMM5,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PMULUDQ %XMM1,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM13,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM12,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSLLQ $0x20,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM9,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM13,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM1,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM10,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM9,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM5,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R12,%XMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM9,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM14,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM9,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM6,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM1,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM9,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM6,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM1,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSLLQ $0x3,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ -0xb0(%RBP),%XMM4	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOVQ %XMM4,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM4,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%R13	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PMULUDQ %XMM6,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM9,%XMM12	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM14,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM12,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %R14,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLQ $0x3,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM10,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM15,%R15	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM15,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM4,%RBX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%RAX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVQ %XMM5,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM5,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM5,%RDI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%RDX),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSD %XMM4,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSD %XMM5,(%R13)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
UNPCKLPD %XMM5,%XMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%R15),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%RBX),%XMM5	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
ADDPD %XMM4,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVSD (%RAX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%RDI),%XMM4	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
SUBPD %XMM4,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVQ %XMM1,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVLPD %XMM5,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
MOVHPD %XMM5,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
PADDQ 0x75758(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
ADD $0x2,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 425ab0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.42+0x1e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .extracted.42]
Source file and lines	advec_mom.cpp:72-76
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72-76
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

73% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

53% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
71% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 10 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 3 suboptimal vector unaligned load/store instructions.

Details

MOVHPD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:75
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:75
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:75

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 4 FP arithmetical operations:

4: addition or subtraction

The binary loop is loading 160 bytes (20 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	119
nb uops	126
loop length	597
used x86 registers	14
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	21.00 cycles
front end	21.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	31.00	31.00	4.33	4.33	2.00	31.00	1.00	2.00	2.00	2.00	0.00	4.33
cycles	31.00	31.00	4.33	4.33	2.00	31.00	1.00	2.00	2.00	2.00	0.00	4.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	20.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	21.00
Dispatch	31.00
DIV/SQRT	20.00
Data deps.	1.00
Overall L1	31.00

Vectorization ratios

INT

all	81%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	70%

all	15%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	73%
load	53%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	71%

Vector efficiency ratios

INT

all	20%
load	23%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	14%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	19%
load	18%
store	12%
mul	12%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 31.00 cycles. At this rate:

2% of peak load performance is reached (5.16 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.03 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 425ab0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOVQ %XMM7,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R8	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PSHUFD $-0x12,%XMM7,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R10	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOVQ %RSI,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
MOVQ %RAX,%XMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PUNPCKLQDQ %XMM4,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM1,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PADDQ -0xe0(%RBP),%XMM12	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PMULUDQ -0xf0(%RBP),%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	5	0.50	vect (12.5%)
MOVDQA %XMM7,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSUBQ %XMM1,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
PSHUFD $-0x18,%XMM4,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PXOR %XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSHUFD $-0x18,%XMM12,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDD -0xd0(%RBP),%XMM15	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRAD $0x1f,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSHUFD $-0x13,%XMM12,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PCMPGTD %XMM15,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
PUNPCKLDQ %XMM5,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOVDQA %XMM3,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM1,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM15,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVDQA %XMM8,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM1,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSRLQ $0x20,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PUNPCKLDQ %XMM4,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOVDQA %XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM12,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM10,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM14,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM4,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSLLQ $0x3,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM1,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM11,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM1,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ -0xc0(%RBP),%XMM5	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOVDQA %XMM2,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM12,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM9,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM5,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PADDQ %XMM14,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSUBD 0x75a15(%RIP),%XMM15	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PXOR %XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSHUFD $-0x12,%XMM5,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PCMPGTD %XMM15,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
PUNPCKLDQ %XMM9,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOVDQA %XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVQ %XMM5,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PMULUDQ %XMM1,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM13,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM12,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSLLQ $0x20,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM9,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM13,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM1,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM10,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM9,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM5,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R12,%XMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM9,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM14,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM9,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM6,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM1,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM9,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM6,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM1,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSLLQ $0x3,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ -0xb0(%RBP),%XMM4	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOVQ %XMM4,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM4,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%R13	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PMULUDQ %XMM6,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM9,%XMM12	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM14,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM12,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %R14,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLQ $0x3,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM10,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM15,%R15	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM15,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM4,%RBX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%RAX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVQ %XMM5,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM5,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM5,%RDI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%RDX),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSD %XMM4,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSD %XMM5,(%R13)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
UNPCKLPD %XMM5,%XMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%R15),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%RBX),%XMM5	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
ADDPD %XMM4,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVSD (%RAX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%RDI),%XMM4	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
SUBPD %XMM4,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVQ %XMM1,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVLPD %XMM5,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
MOVHPD %XMM5,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
PADDQ 0x75758(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
ADD $0x2,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 425ab0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.42+0x1e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

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Complex instructions

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Slow data structures access

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Vector unaligned load/store instructions

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

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Vectorization ratios

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Cycles and memory resources usage

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Code clean check

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Vectorization

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Execution units bottlenecks

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Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code