OV - exec - Loop 172

	Loop Id: 172	Module: exec	Source: advec_mom.cpp:109-139 [...]	Coverage: 6.16%

0x424520 DIVPD	%XMM1,%XMM9

0x424525 MOVAPD	%XMM14,%XMM1

0x42452a ANDPD	0x765bd(%RIP),%XMM14    [11]

0x424533 MOVAPD	0x770b5(%RIP),%XMM4    [11]

0x42453b SUBPD	%XMM0,%XMM4

0x42453f MULPD	%XMM14,%XMM4

0x424544 DIVPD	%XMM11,%XMM4

0x424549 ADDPD	%XMM9,%XMM4

0x42454e MULPD	%XMM4,%XMM3

0x424552 MOVAPD	%XMM2,%XMM4

0x424556 MINPD	%XMM3,%XMM4

0x42455a CMPPD	$0x3,%XMM3,%XMM3

0x42455f ANDPD	%XMM3,%XMM2

0x424563 ANDNPD	%XMM4,%XMM3

0x424567 ORPD	%XMM2,%XMM3

0x42456b MOVAPD	%XMM14,%XMM2

0x424570 MINPD	%XMM3,%XMM2

0x424574 CMPPD	$0x3,%XMM3,%XMM3

0x424579 ANDPD	%XMM3,%XMM14

0x42457e ANDNPD	%XMM2,%XMM3

0x424582 XORPD	%XMM4,%XMM4

0x424586 CMPPD	$0x6,%XMM4,%XMM1

0x42458b ORPD	%XMM14,%XMM3

0x424590 MOVAPD	%XMM3,%XMM2

0x424594 XORPD	0x77074(%RIP),%XMM2    [11]

0x42459c ANDPD	%XMM1,%XMM3

0x4245a0 ANDNPD	%XMM2,%XMM1

0x4245a4 ORPD	%XMM3,%XMM1

0x4245a8 ANDPD	%XMM1,%XMM10

0x4245ad MOVAPD	0x7702b(%RIP),%XMM1    [11]

0x4245b5 SUBPD	%XMM0,%XMM1

0x4245b9 MULPD	%XMM10,%XMM1

0x4245be ADDPD	%XMM13,%XMM1

0x4245c3 MULPD	%XMM6,%XMM1

0x4245c7 MOVDQA	-0xd0(%RBP),%XMM3    [9]

0x4245cf MOVDQA	%XMM3,%XMM0

0x4245d3 PSRLQ	$0x20,%XMM0

0x4245d8 PMULUDQ	%XMM15,%XMM0

0x4245dd MOVDQA	%XMM3,%XMM2

0x4245e1 PMULUDQ	%XMM15,%XMM2

0x4245e6 PSRLQ	$0x20,%XMM15

0x4245ec PMULUDQ	%XMM3,%XMM15

0x4245f1 PADDQ	%XMM0,%XMM15

0x4245f6 PADDQ	%XMM12,%XMM2

0x4245fb PSLLQ	$0x20,%XMM15

0x424601 PADDQ	%XMM15,%XMM2

0x424606 PSLLQ	$0x3,%XMM2

0x42460b MOVQ	%R14,%XMM0

0x424610 PSHUFD	$0x44,%XMM0,%XMM0

0x424615 PADDQ	%XMM2,%XMM0

0x424619 MOVQ	%XMM0,%RAX

0x42461e PSHUFD	$-0x12,%XMM0,%XMM0

0x424623 MOVQ	%XMM0,%RDX

0x424628 MOVLPD	%XMM1,(%RAX)    [2]

0x42462c MOVHPD	%XMM1,(%RDX)    [10]

0x424630 PADDQ	0x76e18(%RIP),%XMM7    [11]

0x424638 ADD	$0x2,%R8

0x42463c CMP	%R13,%R8

0x42463f JAE	4249f5

0x424645 MOV	%R11,%RSI

0x424648 MOVQ	%XMM7,%RAX

0x42464d XOR	%EDX,%EDX

0x42464f DIV	%R12

0x424652 MOVQ	%RAX,%XMM0

0x424657 PSHUFD	$-0x12,%XMM7,%XMM1

0x42465c MOVQ	%XMM1,%RAX

0x424661 XOR	%EDX,%EDX

0x424663 DIV	%RDI

0x424666 MOVQ	%RAX,%XMM1

0x42466b PUNPCKLQDQ	%XMM1,%XMM0

0x42466f MOVDQA	%XMM0,%XMM11

0x424674 PADDQ	-0x120(%RBP),%XMM11    [9]

0x42467d PMULUDQ	-0x130(%RBP),%XMM0    [9]

0x424685 MOVDQA	%XMM7,%XMM1

0x424689 PSUBQ	%XMM0,%XMM1

0x42468d PSHUFD	$-0x18,%XMM1,%XMM2

0x424692 PADDD	-0x110(%RBP),%XMM2    [9]

0x42469a PXOR	%XMM0,%XMM0

0x42469e PCMPGTD	%XMM2,%XMM0

0x4246a2 MOVDQA	%XMM2,%XMM12

0x4246a7 PUNPCKLDQ	%XMM0,%XMM12

0x4246ac PSHUFD	$-0x18,%XMM11,%XMM15

0x4246b2 PSLLQ	$0x20,%XMM11

0x4246b8 PSRAD	$0x1f,%XMM11

0x4246be PSHUFD	$-0x13,%XMM11,%XMM0

0x4246c4 PUNPCKLDQ	%XMM0,%XMM15

0x4246c9 MOVDQA	-0x100(%RBP),%XMM3    [9]

0x4246d1 MOVDQA	%XMM3,%XMM0

0x4246d5 PMULUDQ	%XMM15,%XMM0

0x4246da MOVDQA	-0xc0(%RBP),%XMM1    [9]

0x4246e2 PMULUDQ	%XMM15,%XMM1

0x4246e7 PSRLQ	$0x20,%XMM11

0x4246ed PMULUDQ	%XMM11,%XMM3

0x4246f2 PADDQ	%XMM1,%XMM3

0x4246f6 PSLLQ	$0x20,%XMM3

0x4246fb PADDQ	%XMM12,%XMM0

0x424700 PADDQ	%XMM3,%XMM0

0x424704 PSLLQ	$0x3,%XMM0

0x424709 PADDQ	-0xb0(%RBP),%XMM0    [9]

0x424711 MOVQ	%XMM0,%RAX

0x424716 PSHUFD	$-0x12,%XMM0,%XMM0

0x42471b MOVQ	%XMM0,%RDX

0x424720 MOVSD	(%RAX),%XMM6    [7]

0x424724 MOVHPD	(%RDX),%XMM6    [19]

0x424728 MOVAPD	%XMM6,%XMM8

0x42472d CMPPD	$0x1,%XMM4,%XMM8

0x424733 MOVDQA	%XMM2,%XMM3

0x424737 PCMPEQD	%XMM0,%XMM0

0x42473b PSUBD	%XMM0,%XMM3

0x42473f MOVDQA	%XMM2,%XMM9

0x424744 PADDD	%XMM0,%XMM9

0x424749 XORPD	%XMM4,%XMM4

0x42474d PCMPGTD	%XMM3,%XMM4

0x424751 MOVDQA	%XMM3,%XMM0

0x424755 PUNPCKLDQ	%XMM4,%XMM0

0x424759 PADDD	0x78d6f(%RIP),%XMM2    [11]

0x424761 MOVAPD	%XMM8,%XMM5

0x424766 ANDNPD	%XMM0,%XMM5

0x42476a MOVDQA	%XMM12,%XMM4

0x42476f PAND	%XMM8,%XMM4

0x424774 POR	%XMM5,%XMM4

0x424778 MOVDQA	%XMM8,%XMM5

0x42477d PANDN	%XMM12,%XMM5

0x424782 PAND	%XMM8,%XMM0

0x424787 POR	%XMM5,%XMM0

0x42478b MOVDQA	-0xe0(%RBP),%XMM10    [9]

0x424794 MOVDQA	%XMM10,%XMM5

0x424799 PMULUDQ	%XMM15,%XMM5

0x42479e MOVDQA	%XMM10,%XMM13

0x4247a3 PSRLQ	$0x20,%XMM13

0x4247a9 PMULUDQ	%XMM15,%XMM13

0x4247ae PMULUDQ	%XMM11,%XMM10

0x4247b3 PADDQ	%XMM13,%XMM10

0x4247b8 PSLLQ	$0x20,%XMM10

0x4247be PADDQ	%XMM5,%XMM10

0x4247c3 MOVDQA	%XMM10,%XMM13

0x4247c8 PADDQ	%XMM0,%XMM13

0x4247cd PSLLQ	$0x3,%XMM13

0x4247d3 MOVQ	%R15,%XMM5

0x4247d8 PSHUFD	$0x44,%XMM5,%XMM5

0x4247dd PADDQ	%XMM5,%XMM13

0x4247e2 MOVQ	%XMM13,%RAX

0x4247e7 PSHUFD	$-0x12,%XMM13,%XMM13

0x4247ed MOVQ	%XMM13,%RDX

0x4247f2 PXOR	%XMM13,%XMM13

0x4247f7 PCMPGTD	%XMM9,%XMM13

0x4247fc MOVDQA	%XMM9,%XMM14

0x424801 PUNPCKLDQ	%XMM13,%XMM14

0x424806 MOVDQA	%XMM8,%XMM1

0x42480b PANDN	%XMM14,%XMM1

0x424810 PXOR	%XMM13,%XMM13

0x424815 PCMPGTD	%XMM2,%XMM13

0x42481a PUNPCKLDQ	%XMM13,%XMM2

0x42481f MOVSD	(%RAX),%XMM13    [6]

0x424824 MOVHPD	(%RDX),%XMM13    [18]

0x424829 PAND	%XMM8,%XMM2

0x42482e POR	%XMM1,%XMM2

0x424832 PADDQ	%XMM10,%XMM2

0x424837 PSLLQ	$0x3,%XMM2

0x42483c PADDQ	%XMM5,%XMM2

0x424840 MOVQ	%XMM2,%RAX

0x424845 PSHUFD	$-0x12,%XMM2,%XMM1

0x42484a MOVQ	%XMM1,%RDX

0x42484f MOVSD	(%RAX),%XMM1    [5]

0x424853 MOVHPD	(%RDX),%XMM1    [17]

0x424857 PADDQ	%XMM4,%XMM10

0x42485c MOVAPD	%XMM13,%XMM2

0x424861 PSLLQ	$0x3,%XMM10

0x424867 PADDQ	%XMM5,%XMM10

0x42486c MOVQ	%XMM10,%RAX

0x424871 PSHUFD	$-0x12,%XMM10,%XMM4

0x424877 MOVQ	%XMM4,%RDX

0x42487c MOVSD	(%RAX),%XMM14    [4]

0x424881 MOVHPD	(%RDX),%XMM14    [16]

0x424886 SUBPD	%XMM1,%XMM2

0x42488a SUBPD	%XMM13,%XMM14

0x42488f MOVAPD	%XMM14,%XMM1

0x424894 MULPD	%XMM2,%XMM1

0x424898 PXOR	%XMM10,%XMM10

0x42489d CMPPD	$0x1,%XMM1,%XMM10

0x4248a3 MOVMSKPD	%XMM10,%EAX

0x4248a8 TEST	%EAX,%EAX

0x4248aa JE	4248b4

0x4248ac MOV	-0x58(%RBP),%RDX    [9]

0x4248b0 MOV	0x8(%RDX),%RDX    [15]

0x4248b4 MOVDQA	-0xf0(%RBP),%XMM5    [9]

0x4248bc MOVDQA	%XMM5,%XMM1

0x4248c0 PMULUDQ	%XMM15,%XMM1

0x4248c5 MOVDQA	-0xa0(%RBP),%XMM4    [9]

0x4248cd PMULUDQ	%XMM15,%XMM4

0x4248d2 PMULUDQ	%XMM5,%XMM11

0x4248d7 PADDQ	%XMM4,%XMM11

0x4248dc PSLLQ	$0x20,%XMM11

0x4248e2 PADDQ	%XMM1,%XMM11

0x4248e7 PADDQ	%XMM0,%XMM11

0x4248ec PSLLQ	$0x3,%XMM11

0x4248f2 MOVQ	%R10,%XMM0

0x4248f7 PSHUFD	$0x44,%XMM0,%XMM0

0x4248fc PADDQ	%XMM11,%XMM0

0x424901 MOVQ	%XMM0,%R9

0x424906 PSHUFD	$-0x12,%XMM0,%XMM0

0x42490b MOVQ	%XMM0,%R11

0x424910 MOVSD	(%R9),%XMM5    [1]

0x424915 MOVHPD	(%R11),%XMM5    [8]

0x42491a MOVDQA	%XMM12,%XMM0

0x42491f PSLLQ	$0x3,%XMM0

0x424924 MOVQ	%RDX,%XMM1

0x424929 PSHUFD	$0x44,%XMM1,%XMM4

0x42492e PADDQ	%XMM4,%XMM0

0x424932 TEST	$0x1,%AL

0x424934 JE	424940

0x424936 MOVQ	%XMM0,%RDX

0x42493b MOVSD	(%RDX),%XMM11    [14]

0x424940 TEST	$0x2,%AL

0x424942 JE	424953

0x424944 PSHUFD	$-0x12,%XMM0,%XMM0

0x424949 MOVQ	%XMM0,%RDX

0x42494e MOVHPD	(%RDX),%XMM11    [13]

0x424953 MOV	%RSI,%R11

0x424956 SHUFPS	$-0x18,%XMM8,%XMM8

0x42495b PAND	%XMM8,%XMM3

0x424960 PANDN	%XMM9,%XMM8

0x424965 POR	%XMM3,%XMM8

0x42496a MOVAPD	%XMM6,%XMM0

0x42496e ANDPD	0x7617a(%RIP),%XMM0    [11]

0x424976 DIVPD	%XMM5,%XMM0

0x42497a MOVAPD	%XMM11,%XMM3

0x42497f MULPD	0x76c79(%RIP),%XMM3    [11]

0x424987 MOVAPD	%XMM0,%XMM9

0x42498c ADDPD	0x76c4b(%RIP),%XMM9    [11]

0x424995 PXOR	%XMM1,%XMM1

0x424999 PCMPGTD	%XMM8,%XMM1

0x42499e PUNPCKLDQ	%XMM1,%XMM8

0x4249a3 PSLLQ	$0x3,%XMM8

0x4249a9 PADDQ	%XMM8,%XMM4

0x4249ae TEST	$0x1,%AL

0x4249b0 JE	4249bb

0x4249b2 MOVQ	%XMM4,%RDX

0x4249b7 MOVSD	(%RDX),%XMM1    [12]

0x4249bb ANDPD	0x7612d(%RIP),%XMM2    [11]

0x4249c3 MULPD	%XMM2,%XMM9

0x4249c8 TEST	$0x2,%AL

0x4249ca JE	424520

0x4249d0 PSHUFD	$-0x12,%XMM4,%XMM4

0x4249d5 MOVQ	%XMM4,%RAX

0x4249da MOVHPD	(%RAX),%XMM1    [3]

0x4249de JMP	424520

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 109 - 139

--------------------------------------------------------------------------------

109:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

110:       for (int i = (x_min - 1 + 1); i < (x_max + 1 + 2); i++)

111:         ({

112:           int upwind, donor, downwind, dif;

113:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

114:           if (node_flux(i, j) < 0.0) {

115:             upwind = i + 2;

116:             donor = i + 1;

117:             downwind = i;

118:             dif = donor;

119:           } else {

120:             upwind = i - 1;

121:             donor = i;

122:             downwind = i + 1;

123:             dif = upwind;

124:           }

125:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(donor, j));

126:           width = celldx[i];

127:           vdiffuw = vel1(donor, j) - vel1(upwind, j);

128:           vdiffdw = vel1(downwind, j) - vel1(donor, j);

129:           limiter = 0.0;

130:           if (vdiffuw * vdiffdw > 0.0) {

131:             auw = std::fabs(vdiffuw);

132:             adw = std::fabs(vdiffdw);

133:             wind = 1.0;

134:             if (vdiffdw <= 0.0) wind = -1.0;

135:             limiter =

136:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldx[dif]) / 6.0, auw), adw);

137:           }

138:           advec_vel_s = vel1(donor, j) + (1.0 - sigma) * limiter;

139:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.03
CQA speedup if FP arith vectorized	1.26
CQA speedup if fully vectorized	2.70
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.40
Bottlenecks	P0, P1, P5,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .extracted.27]
Source	advec_mom.cpp:109-139,context.h:46-46,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	59.33
CQA cycles if no scalar integer	57.33
CQA cycles if FP arith vectorized	47.13
CQA cycles if fully vectorized	22.00
Front-end cycles	42.50
P0 cycles	59.33
P1 cycles	59.33
P2 cycles	12.00
P3 cycles	12.00
P4 cycles	1.00
P5 cycles	59.33
P6 cycles	6.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	6.00
P11 cycles	12.00
DIV/SQRT cycles	32.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	247.00
Nb uops	255.00
Nb loads	36.00
Nb stores	2.00
Nb stack references	11.00
FLOP/cycle	0.57
Nb FLOP add-sub	14.00
Nb FLOP mul	14.00
Nb FLOP fma	0.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.82
Bytes prefetched	0.00
Bytes loaded	448.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	79.65
Vectorization ratio load	58.82
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	97.30
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	60.00
Vectorization ratio other	80.69
Vector-efficiency ratio all	21.40
Vector-efficiency ratio load	19.49
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	16.88
Vector-efficiency ratio add_sub	24.66
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	20.00
Vector-efficiency ratio other	22.03

Metric	Value
CQA speedup if no scalar integer	1.03
CQA speedup if FP arith vectorized	1.26
CQA speedup if fully vectorized	2.70
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.40
Bottlenecks	P0, P1, P5,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .extracted.27]
Source	advec_mom.cpp:109-139,context.h:46-46,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	59.33
CQA cycles if no scalar integer	57.33
CQA cycles if FP arith vectorized	47.13
CQA cycles if fully vectorized	22.00
Front-end cycles	42.50
P0 cycles	59.33
P1 cycles	59.33
P2 cycles	12.00
P3 cycles	12.00
P4 cycles	1.00
P5 cycles	59.33
P6 cycles	6.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	6.00
P11 cycles	12.00
DIV/SQRT cycles	32.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	247.00
Nb uops	255.00
Nb loads	36.00
Nb stores	2.00
Nb stack references	11.00
FLOP/cycle	0.57
Nb FLOP add-sub	14.00
Nb FLOP mul	14.00
Nb FLOP fma	0.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.82
Bytes prefetched	0.00
Bytes loaded	448.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	79.65
Vectorization ratio load	58.82
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	97.30
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	60.00
Vectorization ratio other	80.69
Vector-efficiency ratio all	21.40
Vector-efficiency ratio load	19.49
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	16.88
Vector-efficiency ratio add_sub	24.66
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	20.00
Vector-efficiency ratio other	22.03

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .extracted.27]
Source file and lines	advec_mom.cpp:109-139
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109-139
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

It is main loop of related source loop which is unrolled by 2 (including vectorization).
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=32
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 32 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 21% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 59.33 to 22.00 cycles (2.70x speedup).

Details

79% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

58% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
97% of SSE/AVX addition or subtraction instructions are used in vector version.
60% of SSE/AVX divide and square root instructions are used in vector version.
80% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 59.33 to 42.50 cycles (1.40x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109

Vector unaligned load/store instructions

Detected 8 suboptimal vector unaligned load/store instructions.

Details

MOVHPD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:139
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:114
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:127
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:127
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:128
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:125
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:126
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:136

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

24 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 34 FP arithmetical operations:

14: addition or subtraction
14: multiply
6: divide

The binary loop is loading 448 bytes (56 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	247
nb uops	255
loop length	1219
used x86 registers	13
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	11
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	42.50 cycles
front end	42.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	59.33	59.33	12.00	12.00	1.00	59.33	6.00	1.00	1.00	1.00	6.00	12.00
cycles	59.33	59.33	12.00	12.00	1.00	59.33	6.00	1.00	1.00	1.00	6.00	12.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

32.00

Cycles summary

Front-end	42.50
Dispatch	59.33
DIV/SQRT	32.00
Overall L1	59.33

Vectorization ratios

INT

all	80%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	96%
fma	NA (no fma vectorizable/vectorized instructions)
other	72%

all	77%
load	36%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

INT+FP

all	79%
load	58%
store	0%
mul	100%
add-sub	97%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	60%
other	80%

Vector efficiency ratios

INT

all	21%
load	23%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	24%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	22%
load	17%
store	12%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	21%
load	19%
store	12%
mul	16%
add-sub	24%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	20%
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 59.33 cycles. At this rate:

3% of peak load performance is reached (7.55 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 424645

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
DIVPD %XMM1,%XMM9	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	vect (25.0%)
MOVAPD %XMM14,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ANDPD 0x765bd(%RIP),%XMM14	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOVAPD 0x770b5(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
SUBPD %XMM0,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MULPD %XMM14,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
DIVPD %XMM11,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	vect (25.0%)
ADDPD %XMM9,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MULPD %XMM4,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
MOVAPD %XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MINPD %XMM3,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
CMPPD $0x3,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
ANDPD %XMM3,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ANDNPD %XMM4,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ORPD %XMM2,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVAPD %XMM14,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MINPD %XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
CMPPD $0x3,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
ANDPD %XMM3,%XMM14	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ANDNPD %XMM2,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
XORPD %XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMPPD $0x6,%XMM4,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
ORPD %XMM14,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVAPD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
XORPD 0x77074(%RIP),%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
ANDPD %XMM1,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ANDNPD %XMM2,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ORPD %XMM3,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ANDPD %XMM1,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVAPD 0x7702b(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
SUBPD %XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MULPD %XMM10,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
ADDPD %XMM13,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MULPD %XMM6,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
MOVDQA -0xd0(%RBP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM15,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM15,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSRLQ $0x20,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM3,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM0,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM12,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM15,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R14,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM2,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM0,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVLPD %XMM1,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
MOVHPD %XMM1,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
PADDQ 0x76e18(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
ADD $0x2,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %R13,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 4249f5 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x6c5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R11,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVQ %XMM7,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOVQ %RAX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM7,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %RDI	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOVQ %RAX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PUNPCKLQDQ %XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM0,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PADDQ -0x120(%RBP),%XMM11	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PMULUDQ -0x130(%RBP),%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	5	0.50	vect (12.5%)
MOVDQA %XMM7,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSUBQ %XMM0,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
PSHUFD $-0x18,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDD -0x110(%RBP),%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PXOR %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PCMPGTD %XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM2,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PUNPCKLDQ %XMM0,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
PSHUFD $-0x18,%XMM11,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLQ $0x20,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRAD $0x1f,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSHUFD $-0x13,%XMM11,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PUNPCKLDQ %XMM0,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOVDQA -0x100(%RBP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM15,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA -0xc0(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PMULUDQ %XMM15,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSRLQ $0x20,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM11,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM1,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM12,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM3,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ -0xb0(%RBP),%XMM0	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOVQ %XMM0,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%RAX),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%RDX),%XMM6	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
MOVAPD %XMM6,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
CMPPD $0x1,%XMM4,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
MOVDQA %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PCMPEQD %XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
PSUBD %XMM0,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
MOVDQA %XMM2,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PADDD %XMM0,%XMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
XORPD %XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PCMPGTD %XMM3,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PUNPCKLDQ %XMM4,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
PADDD 0x78d6f(%RIP),%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOVAPD %XMM8,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ANDNPD %XMM0,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM12,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PAND %XMM8,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
POR %XMM5,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM8,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PANDN %XMM12,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PAND %XMM8,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
POR %XMM5,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA -0xe0(%RBP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM10,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM15,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM10,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM15,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PMULUDQ %XMM11,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM13,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM5,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM10,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PADDQ %XMM0,%XMM13	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R15,%XMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM5,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM5,%XMM13	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM13,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM13,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM13,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PXOR %XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PCMPGTD %XMM9,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM9,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PUNPCKLDQ %XMM13,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOVDQA %XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PANDN %XMM14,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PXOR %XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PCMPGTD %XMM2,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
PUNPCKLDQ %XMM13,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOVSD (%RAX),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%RDX),%XMM13	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
PAND %XMM8,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
POR %XMM1,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM10,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM5,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM2,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%RAX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%RDX),%XMM1	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
PADDQ %XMM4,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVAPD %XMM13,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSLLQ $0x3,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM5,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM10,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM10,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM4,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%RAX),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%RDX),%XMM14	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
SUBPD %XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
SUBPD %XMM13,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVAPD %XMM14,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MULPD %XMM2,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
PXOR %XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMPPD $0x1,%XMM1,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
MOVMSKPD %XMM10,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	vect (25.0%)
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 4248b4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x584>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x58(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVDQA -0xf0(%RBP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM5,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM15,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA -0xa0(%RBP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PMULUDQ %XMM15,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PMULUDQ %XMM5,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM4,%XMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM1,%XMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM0,%XMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R10,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM11,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM0,%R9	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,%R11	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%R9),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%R11),%XMM5	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
MOVDQA %XMM12,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSLLQ $0x3,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %RDX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM4,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
TEST $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 424940 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x610>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ %XMM0,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%RDX),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST $0x2,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 424953 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x623>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
PSHUFD $-0x12,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVHPD (%RDX),%XMM11	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
MOV %RSI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHUFPS $-0x18,%XMM8,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PAND %XMM8,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PANDN %XMM9,%XMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
POR %XMM3,%XMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVAPD %XMM6,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ANDPD 0x7617a(%RIP),%XMM0	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
DIVPD %XMM5,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	vect (25.0%)
MOVAPD %XMM11,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MULPD 0x76c79(%RIP),%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
MOVAPD %XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ADDPD 0x76c4b(%RIP),%XMM9	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	2-3	0.50	vect (25.0%)
PXOR %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PCMPGTD %XMM8,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
PUNPCKLDQ %XMM1,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
PSLLQ $0x3,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM8,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
TEST $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 4249bb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x68b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ %XMM4,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%RDX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ANDPD 0x7612d(%RIP),%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MULPD %XMM2,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
TEST $0x2,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 424520 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x1f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
PSHUFD $-0x12,%XMM4,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM4,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVHPD (%RAX),%XMM1	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
JMP 424520 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x1f0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .extracted.27]
Source file and lines	advec_mom.cpp:109-139
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109-139
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

It is main loop of related source loop which is unrolled by 2 (including vectorization).
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=32
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

79% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

58% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
97% of SSE/AVX addition or subtraction instructions are used in vector version.
60% of SSE/AVX divide and square root instructions are used in vector version.
80% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109

Vector unaligned load/store instructions

Detected 8 suboptimal vector unaligned load/store instructions.

Details

MOVHPD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:139
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:114
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:127
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:127
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:128
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:125
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:126
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:136

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

24 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 34 FP arithmetical operations:

14: addition or subtraction
14: multiply
6: divide

The binary loop is loading 448 bytes (56 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	247
nb uops	255
loop length	1219
used x86 registers	13
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	11
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	42.50 cycles
front end	42.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	59.33	59.33	12.00	12.00	1.00	59.33	6.00	1.00	1.00	1.00	6.00	12.00
cycles	59.33	59.33	12.00	12.00	1.00	59.33	6.00	1.00	1.00	1.00	6.00	12.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

32.00

Cycles summary

Front-end	42.50
Dispatch	59.33
DIV/SQRT	32.00
Overall L1	59.33

Vectorization ratios

INT

all	80%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	96%
fma	NA (no fma vectorizable/vectorized instructions)
other	72%

all	77%
load	36%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

INT+FP

all	79%
load	58%
store	0%
mul	100%
add-sub	97%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	60%
other	80%

Vector efficiency ratios

INT

all	21%
load	23%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	24%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	22%
load	17%
store	12%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	21%
load	19%
store	12%
mul	16%
add-sub	24%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	20%
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 59.33 cycles. At this rate:

3% of peak load performance is reached (7.55 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 424645

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
DIVPD %XMM1,%XMM9	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	vect (25.0%)
MOVAPD %XMM14,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ANDPD 0x765bd(%RIP),%XMM14	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOVAPD 0x770b5(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
SUBPD %XMM0,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MULPD %XMM14,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
DIVPD %XMM11,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	vect (25.0%)
ADDPD %XMM9,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MULPD %XMM4,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
MOVAPD %XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MINPD %XMM3,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
CMPPD $0x3,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
ANDPD %XMM3,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ANDNPD %XMM4,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ORPD %XMM2,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVAPD %XMM14,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MINPD %XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
CMPPD $0x3,%XMM3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
ANDPD %XMM3,%XMM14	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ANDNPD %XMM2,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
XORPD %XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMPPD $0x6,%XMM4,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
ORPD %XMM14,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVAPD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
XORPD 0x77074(%RIP),%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
ANDPD %XMM1,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ANDNPD %XMM2,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ORPD %XMM3,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
ANDPD %XMM1,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVAPD 0x7702b(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
SUBPD %XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MULPD %XMM10,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
ADDPD %XMM13,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MULPD %XMM6,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
MOVDQA -0xd0(%RBP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM15,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM15,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSRLQ $0x20,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM3,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM0,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM12,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM15,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R14,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM2,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM0,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVLPD %XMM1,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
MOVHPD %XMM1,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
PADDQ 0x76e18(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
ADD $0x2,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %R13,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 4249f5 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x6c5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R11,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVQ %XMM7,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOVQ %RAX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM7,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %RDI	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOVQ %RAX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PUNPCKLQDQ %XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM0,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PADDQ -0x120(%RBP),%XMM11	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PMULUDQ -0x130(%RBP),%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	5	0.50	vect (12.5%)
MOVDQA %XMM7,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSUBQ %XMM0,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
PSHUFD $-0x18,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDD -0x110(%RBP),%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PXOR %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PCMPGTD %XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM2,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PUNPCKLDQ %XMM0,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
PSHUFD $-0x18,%XMM11,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLQ $0x20,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSRAD $0x1f,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PSHUFD $-0x13,%XMM11,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PUNPCKLDQ %XMM0,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOVDQA -0x100(%RBP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM15,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA -0xc0(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PMULUDQ %XMM15,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSRLQ $0x20,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM11,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM1,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM12,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM3,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ -0xb0(%RBP),%XMM0	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOVQ %XMM0,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%RAX),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%RDX),%XMM6	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
MOVAPD %XMM6,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
CMPPD $0x1,%XMM4,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
MOVDQA %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PCMPEQD %XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
PSUBD %XMM0,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
MOVDQA %XMM2,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PADDD %XMM0,%XMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
XORPD %XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PCMPGTD %XMM3,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PUNPCKLDQ %XMM4,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
PADDD 0x78d6f(%RIP),%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOVAPD %XMM8,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ANDNPD %XMM0,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM12,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PAND %XMM8,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
POR %XMM5,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM8,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PANDN %XMM12,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PAND %XMM8,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
POR %XMM5,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA -0xe0(%RBP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM10,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM15,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM10,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM15,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PMULUDQ %XMM11,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM13,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM5,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVDQA %XMM10,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PADDQ %XMM0,%XMM13	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R15,%XMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM5,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM5,%XMM13	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM13,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM13,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM13,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PXOR %XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PCMPGTD %XMM9,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM9,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PUNPCKLDQ %XMM13,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOVDQA %XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PANDN %XMM14,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PXOR %XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PCMPGTD %XMM2,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
PUNPCKLDQ %XMM13,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOVSD (%RAX),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%RDX),%XMM13	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
PAND %XMM8,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
POR %XMM1,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM10,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM5,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM2,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%RAX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%RDX),%XMM1	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
PADDQ %XMM4,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVAPD %XMM13,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSLLQ $0x3,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM5,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM10,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM10,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM4,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%RAX),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%RDX),%XMM14	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
SUBPD %XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
SUBPD %XMM13,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVAPD %XMM14,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MULPD %XMM2,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
PXOR %XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMPPD $0x1,%XMM1,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
MOVMSKPD %XMM10,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	vect (25.0%)
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 4248b4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x584>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x58(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVDQA -0xf0(%RBP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM5,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM15,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA -0xa0(%RBP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PMULUDQ %XMM15,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PMULUDQ %XMM5,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM4,%XMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM1,%XMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM0,%XMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R10,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM11,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM0,%R9	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,%R11	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%R9),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%R11),%XMM5	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
MOVDQA %XMM12,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSLLQ $0x3,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %RDX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM4,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
TEST $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 424940 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x610>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ %XMM0,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%RDX),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST $0x2,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 424953 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x623>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
PSHUFD $-0x12,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVHPD (%RDX),%XMM11	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
MOV %RSI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHUFPS $-0x18,%XMM8,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PAND %XMM8,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PANDN %XMM9,%XMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
POR %XMM3,%XMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVAPD %XMM6,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ANDPD 0x7617a(%RIP),%XMM0	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
DIVPD %XMM5,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	vect (25.0%)
MOVAPD %XMM11,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MULPD 0x76c79(%RIP),%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
MOVAPD %XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ADDPD 0x76c4b(%RIP),%XMM9	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	2-3	0.50	vect (25.0%)
PXOR %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PCMPGTD %XMM8,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
PUNPCKLDQ %XMM1,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
PSLLQ $0x3,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM8,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
TEST $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 4249bb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x68b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ %XMM4,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%RDX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ANDPD 0x7612d(%RIP),%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MULPD %XMM2,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
TEST $0x2,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 424520 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x1f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
PSHUFD $-0x12,%XMM4,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM4,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVHPD (%RAX),%XMM1	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
JMP 424520 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x1f0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code