OV - exec - Loop 160

	Loop Id: 160	Module: exec	Source: advec_cell.cpp:45-49 [...]	Coverage: 1.18%

0x421790 MOVQ	%XMM7,%RAX

0x421795 XOR	%EDX,%EDX

0x421797 DIVQ	-0x98(%RBP)    [11]

0x42179e MOV	%RAX,%RSI

0x4217a1 PSHUFD	$-0x12,%XMM7,%XMM0

0x4217a6 MOVQ	%XMM0,%RAX

0x4217ab XOR	%EDX,%EDX

0x4217ad DIVQ	-0x90(%RBP)    [11]

0x4217b4 MOVQ	%RSI,%XMM0

0x4217b9 MOVQ	%RAX,%XMM1

0x4217be PUNPCKLQDQ	%XMM1,%XMM0

0x4217c2 PSHUFD	$-0x18,%XMM0,%XMM1

0x4217c7 PADDD	-0x120(%RBP),%XMM1    [11]

0x4217cf PMULUDQ	-0x130(%RBP),%XMM0    [11]

0x4217d7 MOVDQA	%XMM7,%XMM2

0x4217db PSUBQ	%XMM0,%XMM2

0x4217df PSHUFD	$-0x18,%XMM2,%XMM15

0x4217e5 PXOR	%XMM4,%XMM4

0x4217e9 PXOR	%XMM9,%XMM9

0x4217ee PADDD	-0x110(%RBP),%XMM15    [11]

0x4217f7 PCMPGTD	%XMM1,%XMM9

0x4217fc MOVDQA	%XMM1,%XMM0

0x421800 PUNPCKLDQ	%XMM9,%XMM0

0x421805 PCMPGTD	%XMM15,%XMM4

0x42180a MOVDQA	-0xe0(%RBP),%XMM10    [11]

0x421813 MOVDQA	%XMM10,%XMM3

0x421818 PMULUDQ	%XMM0,%XMM3

0x42181c MOVDQA	-0x100(%RBP),%XMM5    [11]

0x421824 MOVDQA	%XMM15,%XMM2

0x421829 PMULUDQ	%XMM0,%XMM5

0x42182d PUNPCKLDQ	0x78f6a(%RIP),%XMM9    [14]

0x421836 PUNPCKLDQ	%XMM4,%XMM2

0x42183a PMULUDQ	%XMM9,%XMM10

0x42183f PADDQ	%XMM5,%XMM10

0x421844 PSLLQ	$0x20,%XMM10

0x42184a PADDQ	%XMM2,%XMM3

0x42184e PSUBD	%XMM11,%XMM15

0x421853 PXOR	%XMM4,%XMM4

0x421857 PCMPGTD	%XMM15,%XMM4

0x42185c PADDQ	%XMM10,%XMM3

0x421861 PUNPCKLDQ	%XMM4,%XMM15

0x421866 MOVDQA	%XMM13,%XMM5

0x42186b PMULUDQ	%XMM0,%XMM5

0x42186f PSLLQ	$0x3,%XMM3

0x421874 MOVDQA	-0xd0(%RBP),%XMM10    [11]

0x42187d PMULUDQ	%XMM0,%XMM10

0x421882 MOVDQA	%XMM13,%XMM4

0x421887 PADDQ	-0xf0(%RBP),%XMM3    [11]

0x42188f PMULUDQ	%XMM9,%XMM4

0x421894 PADDQ	%XMM10,%XMM4

0x421899 PSLLQ	$0x20,%XMM4

0x42189e MOVQ	%XMM3,%RDI

0x4218a3 PADDQ	%XMM5,%XMM4

0x4218a7 PSUBD	%XMM11,%XMM1

0x4218ac PXOR	%XMM10,%XMM10

0x4218b1 PSHUFD	$-0x12,%XMM3,%XMM3

0x4218b6 PCMPGTD	%XMM1,%XMM10

0x4218bb PUNPCKLDQ	%XMM10,%XMM1

0x4218c0 MOVDQA	%XMM12,%XMM5

0x4218c5 MOVQ	%XMM3,%R10

0x4218ca PMULUDQ	%XMM1,%XMM5

0x4218ce MOVDQA	%XMM12,%XMM3

0x4218d3 PSRLQ	$0x20,%XMM3

0x4218d8 PMULUDQ	%XMM3,%XMM1

0x4218dc PSHUFD	$-0x2c,%XMM10,%XMM10

0x4218e2 PMULUDQ	%XMM12,%XMM10

0x4218e7 PADDQ	%XMM1,%XMM10

0x4218ec PSLLQ	$0x20,%XMM10

0x4218f2 PADDQ	%XMM2,%XMM5

0x4218f6 PADDQ	%XMM10,%XMM5

0x4218fb PADDQ	%XMM4,%XMM15

0x421900 PSLLQ	$0x3,%XMM15

0x421906 PADDQ	%XMM14,%XMM15

0x42190b MOVQ	%XMM15,%RAX

0x421910 PADDQ	%XMM2,%XMM4

0x421914 PSHUFD	$-0x12,%XMM15,%XMM1

0x42191a PSLLQ	$0x3,%XMM4

0x42191f PADDQ	%XMM14,%XMM4

0x421924 MOVQ	%XMM4,%RDX

0x421929 MOVQ	%XMM1,%RSI

0x42192e PSLLQ	$0x3,%XMM5

0x421933 MOVQ	%R15,%XMM1

0x421938 PSHUFD	$0x44,%XMM1,%XMM1

0x42193d PSHUFD	$-0x12,%XMM4,%XMM4

0x421942 PADDQ	%XMM1,%XMM5

0x421946 MOVQ	%XMM5,%R14

0x42194b PSHUFD	$-0x12,%XMM5,%XMM5

0x421950 MOV	%R13,%RBX

0x421953 MOVQ	%XMM4,%R13

0x421958 MOVDQA	%XMM12,%XMM4

0x42195d PMULUDQ	%XMM0,%XMM4

0x421961 PMULUDQ	%XMM0,%XMM3

0x421965 MOVQ	%XMM5,%R8

0x42196a MOVDQA	%XMM12,%XMM5

0x42196f PMULUDQ	%XMM9,%XMM5

0x421974 PADDQ	%XMM3,%XMM5

0x421978 MOVSD	(%RDI),%XMM3    [7]

0x42197c PSLLQ	$0x20,%XMM5

0x421981 PADDQ	%XMM2,%XMM4

0x421985 MOVHPD	(%R10),%XMM3    [9]

0x42198a PADDQ	%XMM5,%XMM4

0x42198e MOVSD	(%RAX),%XMM5    [4]

0x421992 MOVHPD	(%RSI),%XMM5    [10]

0x421996 PSLLQ	$0x3,%XMM4

0x42199b PADDQ	%XMM1,%XMM4

0x42199f MOVQ	%XMM4,%RDI

0x4219a4 MOVSD	(%R14),%XMM1    [13]

0x4219a9 PSHUFD	$-0x12,%XMM4,%XMM4

0x4219ae MOVQ	%XMM4,%R10

0x4219b3 MOVHPD	(%R8),%XMM1    [2]

0x4219b8 MOVSD	(%RDX),%XMM4    [16]

0x4219bc MOVHPD	(%R13),%XMM4    [12]

0x4219c2 ADDPD	%XMM3,%XMM5

0x4219c6 MOVSD	(%RDI),%XMM3    [6]

0x4219ca MOVHPD	(%R10),%XMM3    [8]

0x4219cf ADDPD	%XMM4,%XMM3

0x4219d3 MOVDQA	%XMM6,%XMM4

0x4219d7 PSRLQ	$0x20,%XMM4

0x4219dc PMULUDQ	%XMM0,%XMM4

0x4219e0 ADDPD	%XMM5,%XMM1

0x4219e4 MOVDQA	%XMM6,%XMM5

0x4219e8 PMULUDQ	%XMM9,%XMM5

0x4219ed PADDQ	%XMM4,%XMM5

0x4219f1 SUBPD	%XMM3,%XMM1

0x4219f5 MOVDQA	%XMM6,%XMM3

0x4219f9 PMULUDQ	%XMM0,%XMM3

0x4219fd PSLLQ	$0x20,%XMM5

0x421a02 PADDQ	%XMM2,%XMM3

0x421a06 PADDQ	%XMM5,%XMM3

0x421a0a MOVQ	%R12,%XMM4

0x421a0f PSHUFD	$0x44,%XMM4,%XMM4

0x421a14 PSLLQ	$0x3,%XMM3

0x421a19 PADDQ	%XMM3,%XMM4

0x421a1d MOVQ	%XMM4,%RDI

0x421a22 PSHUFD	$-0x12,%XMM4,%XMM3

0x421a27 MOVQ	%XMM3,%R8

0x421a2c MOVDQA	%XMM8,%XMM3

0x421a31 MOVDQA	%XMM8,%XMM4

0x421a36 PSRLQ	$0x20,%XMM4

0x421a3b PMULUDQ	%XMM0,%XMM3

0x421a3f PMULUDQ	%XMM0,%XMM4

0x421a43 PMULUDQ	%XMM8,%XMM9

0x421a48 PADDQ	%XMM4,%XMM9

0x421a4d PADDQ	%XMM2,%XMM3

0x421a51 MOVLPD	%XMM1,(%RDI)    [5]

0x421a55 MOVHPD	%XMM1,(%R8)    [1]

0x421a5a PSLLQ	$0x20,%XMM9

0x421a60 PADDQ	%XMM9,%XMM3

0x421a65 PSLLQ	$0x3,%XMM3

0x421a6a MOVQ	-0x30(%RBP),%XMM0    [11]

0x421a6f PSHUFD	$0x44,%XMM0,%XMM0

0x421a74 PADDQ	%XMM3,%XMM0

0x421a78 MOVSD	(%RAX),%XMM2    [4]

0x421a7c MOVHPD	(%RSI),%XMM2    [10]

0x421a80 SUBPD	%XMM2,%XMM1

0x421a84 MOVSD	(%RDX),%XMM2    [16]

0x421a88 MOVHPD	(%R13),%XMM2    [12]

0x421a8e MOV	%RBX,%R13

0x421a91 ADDPD	%XMM2,%XMM1

0x421a95 MOVQ	%XMM0,%RAX

0x421a9a PSHUFD	$-0x12,%XMM0,%XMM0

0x421a9f MOVQ	%XMM0,%RDX

0x421aa4 MOVLPD	%XMM1,(%RAX)    [3]

0x421aa8 MOVHPD	%XMM1,(%RDX)    [15]

0x421aac PADDQ	0x7999c(%RIP),%XMM7    [14]

0x421ab4 ADD	$0x2,%R9

0x421ab8 CMP	%RBX,%R9

0x421abb JB	421790

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 45 - 49

--------------------------------------------------------------------------------

45:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

46:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

47:           pre_vol(i, j) = volume(i, j) + (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j));

48:           post_vol(i, j) = pre_vol(i, j) - (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j));

49:         }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.18
CQA speedup if fully vectorized	4.35
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.00
Bottlenecks	P0,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted.37]
Source	advec_cell.cpp:45-49,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	43.50
CQA cycles if no scalar integer	41.50
CQA cycles if FP arith vectorized	37.00
CQA cycles if fully vectorized	10.00
Front-end cycles	29.17
P0 cycles	43.50
P1 cycles	43.33
P2 cycles	8.67
P3 cycles	8.67
P4 cycles	2.00
P5 cycles	43.17
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	8.67
DIV/SQRT cycles	20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	168.00
Nb uops	175.00
Nb loads	26.00
Nb stores	4.00
Nb stack references	10.00
FLOP/cycle	0.28
Nb FLOP add-sub	12.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.17
Bytes prefetched	0.00
Bytes loaded	280.00
Bytes stored	32.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	14.00
Stride indirect	0.00
Vectorization ratio all	73.75
Vectorization ratio load	34.62
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	73.42
Vector-efficiency ratio all	19.84
Vector-efficiency ratio load	15.87
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	20.89

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.18
CQA speedup if fully vectorized	4.35
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.00
Bottlenecks	P0,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted.37]
Source	advec_cell.cpp:45-49,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	43.50
CQA cycles if no scalar integer	41.50
CQA cycles if FP arith vectorized	37.00
CQA cycles if fully vectorized	10.00
Front-end cycles	29.17
P0 cycles	43.50
P1 cycles	43.33
P2 cycles	8.67
P3 cycles	8.67
P4 cycles	2.00
P5 cycles	43.17
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	8.67
DIV/SQRT cycles	20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	168.00
Nb uops	175.00
Nb loads	26.00
Nb stores	4.00
Nb stack references	10.00
FLOP/cycle	0.28
Nb FLOP add-sub	12.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.17
Bytes prefetched	0.00
Bytes loaded	280.00
Bytes stored	32.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	14.00
Stride indirect	0.00
Vectorization ratio all	73.75
Vectorization ratio load	34.62
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	73.42
Vector-efficiency ratio all	19.84
Vector-efficiency ratio load	15.87
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	20.89

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted.37]
Source file and lines	advec_cell.cpp:45-49
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:45-49
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 19% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 43.50 to 10.00 cycles (4.35x speedup).

Details

73% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

34% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
73% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:45
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:45

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 14 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 9 suboptimal vector unaligned load/store instructions.

Details

MOVHPD: 9 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:47
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:47
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:47
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:47
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:47
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:47
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:48
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:48
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:48

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 12 FP arithmetical operations:

12: addition or subtraction

The binary loop is loading 280 bytes (35 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	168
nb uops	175
loop length	817
used x86 registers	13
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	29.17 cycles
front end	29.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	43.50	43.33	8.67	8.67	2.00	43.17	1.00	2.00	2.00	2.00	0.00	8.67
cycles	43.50	43.33	8.67	8.67	2.00	43.17	1.00	2.00	2.00	2.00	0.00	8.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	29.17
Dispatch	43.50
DIV/SQRT	20.00
Data deps.	2.00
Overall L1	43.50

Vectorization ratios

INT

all	82%
load	75%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	71%

all	25%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	73%
load	34%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	73%

Vector efficiency ratios

INT

all	20%
load	19%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	19%
load	15%
store	12%
mul	12%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 43.50 cycles. At this rate:

3% of peak load performance is reached (6.44 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.74 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 421790

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOVQ %XMM7,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVQ -0x98(%RBP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	10	scal (12.5%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PSHUFD $-0x12,%XMM7,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVQ -0x90(%RBP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	10	scal (12.5%)
MOVQ %RSI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
MOVQ %RAX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PUNPCKLQDQ %XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
PSHUFD $-0x18,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDD -0x120(%RBP),%XMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PMULUDQ -0x130(%RBP),%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	5	0.50	vect (12.5%)
MOVDQA %XMM7,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSUBQ %XMM0,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
PSHUFD $-0x18,%XMM2,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PXOR %XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PXOR %XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PADDD -0x110(%RBP),%XMM15	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PCMPGTD %XMM1,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PUNPCKLDQ %XMM9,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
PCMPGTD %XMM15,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
MOVDQA -0xe0(%RBP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM10,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM0,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA -0x100(%RBP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM15,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM0,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PUNPCKLDQ 0x78f6a(%RIP),%XMM9	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (12.5%)
PUNPCKLDQ %XMM4,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
PMULUDQ %XMM9,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM5,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM2,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSUBD %XMM11,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
PXOR %XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PCMPGTD %XMM15,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
PADDQ %XMM10,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PUNPCKLDQ %XMM4,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOVDQA %XMM13,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM0,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSLLQ $0x3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA -0xd0(%RBP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PMULUDQ %XMM0,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM13,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PADDQ -0xf0(%RBP),%XMM3	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PMULUDQ %XMM9,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM10,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %XMM3,%RDI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PADDQ %XMM5,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSUBD %XMM11,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
PXOR %XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSHUFD $-0x12,%XMM3,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PCMPGTD %XMM1,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
PUNPCKLDQ %XMM10,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOVDQA %XMM12,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVQ %XMM3,%R10	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PMULUDQ %XMM1,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM12,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM3,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSHUFD $-0x2c,%XMM10,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PMULUDQ %XMM12,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM1,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM2,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM10,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM4,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM14,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM15,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PADDQ %XMM2,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSHUFD $-0x12,%XMM15,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLQ $0x3,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM14,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM4,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVQ %XMM1,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSLLQ $0x3,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R15,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM4,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM1,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM5,%R14	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM5,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOV %R13,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ %XMM4,%R13	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM12,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM0,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PMULUDQ %XMM0,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVQ %XMM5,%R8	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM12,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM9,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM3,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVSD (%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
PSLLQ $0x20,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM2,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVHPD (%R10),%XMM3	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
PADDQ %XMM5,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVSD (%RAX),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%RSI),%XMM5	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
PSLLQ $0x3,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM1,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM4,%RDI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%R14),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
PSHUFD $-0x12,%XMM4,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM4,%R10	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVHPD (%R8),%XMM1	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
MOVSD (%RDX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%R13),%XMM4	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
ADDPD %XMM3,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVSD (%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%R10),%XMM3	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
ADDPD %XMM4,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVDQA %XMM6,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM0,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
ADDPD %XMM5,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVDQA %XMM6,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM9,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM4,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
SUBPD %XMM3,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVDQA %XMM6,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM0,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSLLQ $0x20,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM2,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM5,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %R12,%XMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM4,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLQ $0x3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM3,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM4,%RDI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM4,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM3,%R8	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM8,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVDQA %XMM8,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM0,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PMULUDQ %XMM0,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PMULUDQ %XMM8,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM4,%XMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM2,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVLPD %XMM1,(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
MOVHPD %XMM1,(%R8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
PSLLQ $0x20,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM9,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ -0x30(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM3,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVSD (%RAX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%RSI),%XMM2	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
SUBPD %XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVSD (%RDX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%R13),%XMM2	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
MOV %RBX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADDPD %XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVQ %XMM0,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVLPD %XMM1,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
MOVHPD %XMM1,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
PADDQ 0x7999c(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
ADD $0x2,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 421790 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.37+0x220>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted.37]
Source file and lines	advec_cell.cpp:45-49
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:45-49
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

73% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

34% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
73% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:45
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:45

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 14 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 9 suboptimal vector unaligned load/store instructions.

Details

MOVHPD: 9 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:47
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:47
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:47
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:47
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:47
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:47
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:48
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:48
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:48

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 12 FP arithmetical operations:

12: addition or subtraction

The binary loop is loading 280 bytes (35 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	168
nb uops	175
loop length	817
used x86 registers	13
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	29.17 cycles
front end	29.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	43.50	43.33	8.67	8.67	2.00	43.17	1.00	2.00	2.00	2.00	0.00	8.67
cycles	43.50	43.33	8.67	8.67	2.00	43.17	1.00	2.00	2.00	2.00	0.00	8.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	29.17
Dispatch	43.50
DIV/SQRT	20.00
Data deps.	2.00
Overall L1	43.50

Vectorization ratios

INT

all	82%
load	75%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	71%

all	25%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	73%
load	34%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	73%

Vector efficiency ratios

INT

all	20%
load	19%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	19%
load	15%
store	12%
mul	12%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 43.50 cycles. At this rate:

3% of peak load performance is reached (6.44 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.74 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 421790

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOVQ %XMM7,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVQ -0x98(%RBP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	10	scal (12.5%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PSHUFD $-0x12,%XMM7,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIVQ -0x90(%RBP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	10	scal (12.5%)
MOVQ %RSI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
MOVQ %RAX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PUNPCKLQDQ %XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
PSHUFD $-0x18,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDD -0x120(%RBP),%XMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PMULUDQ -0x130(%RBP),%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	5	0.50	vect (12.5%)
MOVDQA %XMM7,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSUBQ %XMM0,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
PSHUFD $-0x18,%XMM2,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PXOR %XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PXOR %XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PADDD -0x110(%RBP),%XMM15	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PCMPGTD %XMM1,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PUNPCKLDQ %XMM9,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
PCMPGTD %XMM15,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
MOVDQA -0xe0(%RBP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM10,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM0,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA -0x100(%RBP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVDQA %XMM15,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM0,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PUNPCKLDQ 0x78f6a(%RIP),%XMM9	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (12.5%)
PUNPCKLDQ %XMM4,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
PMULUDQ %XMM9,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM5,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM2,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSUBD %XMM11,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
PXOR %XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PCMPGTD %XMM15,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
PADDQ %XMM10,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PUNPCKLDQ %XMM4,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOVDQA %XMM13,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM0,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSLLQ $0x3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA -0xd0(%RBP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
PMULUDQ %XMM0,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM13,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PADDQ -0xf0(%RBP),%XMM3	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PMULUDQ %XMM9,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM10,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %XMM3,%RDI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PADDQ %XMM5,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSUBD %XMM11,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
PXOR %XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSHUFD $-0x12,%XMM3,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PCMPGTD %XMM1,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
PUNPCKLDQ %XMM10,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
MOVDQA %XMM12,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVQ %XMM3,%R10	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PMULUDQ %XMM1,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVDQA %XMM12,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM3,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSHUFD $-0x2c,%XMM10,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PMULUDQ %XMM12,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM1,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x20,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM2,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM10,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM4,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM14,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM15,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PADDQ %XMM2,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSHUFD $-0x12,%XMM15,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLQ $0x3,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM14,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM4,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVQ %XMM1,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSLLQ $0x3,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R15,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM4,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM1,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM5,%R14	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM5,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOV %R13,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ %XMM4,%R13	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM12,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM0,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PMULUDQ %XMM0,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
MOVQ %XMM5,%R8	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM12,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM9,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM3,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVSD (%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
PSLLQ $0x20,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM2,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVHPD (%R10),%XMM3	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
PADDQ %XMM5,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVSD (%RAX),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%RSI),%XMM5	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
PSLLQ $0x3,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM1,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM4,%RDI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVSD (%R14),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
PSHUFD $-0x12,%XMM4,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM4,%R10	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVHPD (%R8),%XMM1	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
MOVSD (%RDX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%R13),%XMM4	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
ADDPD %XMM3,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVSD (%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%R10),%XMM3	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
ADDPD %XMM4,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVDQA %XMM6,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM0,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
ADDPD %XMM5,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVDQA %XMM6,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM9,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM4,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
SUBPD %XMM3,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVDQA %XMM6,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PMULUDQ %XMM0,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PSLLQ $0x20,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM2,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM5,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %R12,%XMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM4,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PSLLQ $0x3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM3,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVQ %XMM4,%RDI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM4,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM3,%R8	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM8,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOVDQA %XMM8,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PMULUDQ %XMM0,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PMULUDQ %XMM0,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PMULUDQ %XMM8,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	5	0.50	vect (12.5%)
PADDQ %XMM4,%XMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PADDQ %XMM2,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVLPD %XMM1,(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
MOVHPD %XMM1,(%R8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
PSLLQ $0x20,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
PADDQ %XMM9,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
PSLLQ $0x3,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ -0x30(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ %XMM3,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
MOVSD (%RAX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%RSI),%XMM2	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
SUBPD %XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVSD (%RDX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVHPD (%R13),%XMM2	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
MOV %RBX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADDPD %XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	vect (25.0%)
MOVQ %XMM0,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $-0x12,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,%RDX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVLPD %XMM1,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
MOVHPD %XMM1,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	4-12	0.50	scal (12.5%)
PADDQ 0x7999c(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
ADD $0x2,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 421790 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.37+0x220>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code