OV - exec - Function __svml_idiv4

	Function: __svml_idiv4_e9	Module: exec	Source: :0-0	Coverage (incl. loops): 0.02% \| (excl. loops): 0.02%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x48cce0 ENDBR64

0x48cce4 VPXOR	%XMM2,%XMM2,%XMM2

0x48cce8 VPCMPEQD	%XMM2,%XMM1,%XMM2

0x48ccec VTESTPS	%XMM2,%XMM2

0x48ccf1 JE	48ccfa

0x48ccf3 MOV	$0,%EAX

0x48ccf8 DIV	%AL

0x48ccfa VCVTDQ2PS	%XMM1,%XMM2

0x48ccfe VRCPPS	%XMM2,%XMM2

0x48cd02 VCVTPS2PD	%XMM2,%YMM2

0x48cd06 VCVTDQ2PD	%XMM1,%YMM1

0x48cd0a VMULPD	%YMM2,%YMM1,%YMM3

0x48cd0e VBROADCASTSD	0xe909(%RIP),%YMM4

0x48cd17 VSUBPD	%YMM3,%YMM4,%YMM3

0x48cd1b VMULPD	%YMM2,%YMM3,%YMM2

0x48cd1f VCVTDQ2PD	%XMM0,%YMM0

0x48cd23 VMULPD	%YMM0,%YMM2,%YMM0

0x48cd27 VMULPD	%YMM1,%YMM2,%YMM1

0x48cd2b VBROADCASTSD	0x207cc(%RIP),%YMM2

0x48cd34 VSUBPD	%YMM1,%YMM2,%YMM1

0x48cd38 VMULPD	%YMM1,%YMM0,%YMM0

0x48cd3c VCVTTPD2DQ	%YMM0,%XMM0

0x48cd40 VZEROUPPER

0x48cd43 RET

0x48cd44 NOPW	%CS:(%RAX,%RAX,1)

0x48cd4e XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run orig_0

Source file and lines
Module	exec

The structure of this function is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your function is partially vectorized. Only 33% of vector register length is used (average across all SSE/AVX instructions).

Details

87% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
78% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 0 occurrences
VCVTDQ2PD: 0 occurrences
VCVTPS2PD: 0 occurrences
VCVTTPD2DQ: 0 occurrences
VZEROUPPER: 0 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTDQ2PD (INT32 to FP64, SIMD): 0 occurrences
VCVTDQ2PS (INT32 to FP32, SIMD): 0 occurrences
VCVTPS2PD (FP32 to FP64, SIMD): 0 occurrences
VCVTTPD2DQ (FP64 to INT32, SIMD): 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time). 7 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 32 FP arithmetical operations:

8: addition or subtraction
20: multiply
4: fast reciprocal

The binary function is loading 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 2.00 FP operations per loaded or stored byte.

General properties

nb instructions	23
nb uops	28.50
loop length	96.50
used x86 registers	0.50
used mmx registers	0
used xmm registers	3
used ymm registers	5
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.40

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	4.75 cycles
front end	4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.50	7.50	1.00	1.00	0.00	5.50	2.00	0.00	0.00	0.00	0.50	1.00
cycles	7.50	7.50	1.00	1.00	0.00	5.50	2.00	0.00	0.00	0.00	0.50	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	4.75
Dispatch	7.50
DIV/SQRT	3.00
Overall L1	7.50

Vectorization ratios

INT

all	92%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	92%

all	84%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	60%

INT+FP

all	87%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	78%

Vector efficiency ratios

INT

all	23%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	23%

all	38%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	33%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	24%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.50 cycles. At this rate:

1% of peak load performance is reached (2.14 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run orig_0

Source file and lines
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.00 to 7.00 cycles (1.14x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is partially vectorized. Only 32% of vector register length is used (average across all SSE/AVX instructions).

Details

85% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
75% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.00 to 6.00 cycles (1.33x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 8.00 to 7.50 cycles (1.07x speedup).

Special instructions executing on a single port

1.33x slowdown from special instructions executing on a single port.

Details

VCVTDQ2PD: 2 occurrences►
VCVTPS2PD: 1 occurrences►
VCVTTPD2DQ: 1 occurrences►
VTESTPS: 1 occurrences►

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences►
VCVTDQ2PD: 2 occurrences►
VCVTPS2PD: 1 occurrences►
VCVTTPD2DQ: 1 occurrences►
VZEROUPPER: 1 occurrences►

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTDQ2PD (INT32 to FP64, SIMD): 2 occurrences►
VCVTDQ2PS (INT32 to FP32, SIMD): 1 occurrences►
VCVTPS2PD (FP32 to FP64, SIMD): 1 occurrences►
VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences►

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 32 FP arithmetical operations:

8: addition or subtraction
20: multiply
4: fast reciprocal

The binary function is loading 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 2.00 FP operations per loaded or stored byte.

General properties

nb instructions	24
nb uops	31
loop length	100
used x86 registers	1
used mmx registers	0
used xmm registers	3
used ymm registers	5
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.40

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.17 cycles
front end	5.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.00	8.00	1.00	1.00	0.00	6.00	2.00	0.00	0.00	0.00	1.00	1.00
cycles	8.00	8.00	1.00	1.00	0.00	6.00	2.00	0.00	0.00	0.00	1.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	5.17
Dispatch	8.00
DIV/SQRT	6.00
Overall L1	8.00

Vectorization ratios

INT

all	85%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	85%

all	84%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	60%

INT+FP

all	85%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	75%

Vector efficiency ratios

INT

all	22%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	22%

all	38%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	32%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.00 cycles. At this rate:

1% of peak load performance is reached (2.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 48cce0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ENDBR64																N/A
VPXOR %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPCMPEQD %XMM2,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	3	0.50	vect (25.0%)
VTESTPS %XMM2,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	vect (25.0%)
JE 48ccfa <__svml_idiv4_e9+0x1a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
DIV %AL	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	N/A
VCVTDQ2PS %XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VRCPPS %XMM2,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	4	1	vect (25.0%)
VCVTPS2PD %XMM2,%YMM2	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	vect (25.0%)
VCVTDQ2PD %XMM1,%YMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	vect (25.0%)
VMULPD %YMM2,%YMM1,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0xe909(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VSUBPD %YMM3,%YMM4,%YMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM2,%YMM3,%YMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VCVTDQ2PD %XMM0,%YMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	vect (25.0%)
VMULPD %YMM0,%YMM2,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM1,%YMM2,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x207cc(%RIP),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VSUBPD %YMM1,%YMM2,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM1,%YMM0,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VCVTTPD2DQ %YMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run orig_0

Source file and lines
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your function is partially vectorized. Only 34% of vector register length is used (average across all SSE/AVX instructions).

Details

89% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
81% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTDQ2PD: 2 occurrences►
VCVTPS2PD: 1 occurrences►
VCVTTPD2DQ: 1 occurrences►
VZEROUPPER: 1 occurrences►

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTDQ2PD (INT32 to FP64, SIMD): 2 occurrences►
VCVTDQ2PS (INT32 to FP32, SIMD): 1 occurrences►
VCVTPS2PD (FP32 to FP64, SIMD): 1 occurrences►
VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences►

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 32 FP arithmetical operations:

8: addition or subtraction
20: multiply
4: fast reciprocal

The binary function is loading 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 2.00 FP operations per loaded or stored byte.

General properties

nb instructions	22
nb uops	26
loop length	93
used x86 registers	0
used mmx registers	0
used xmm registers	3
used ymm registers	5
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.40

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.33 cycles
front end	4.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.00	7.00	1.00	1.00	0.00	5.00	2.00	0.00	0.00	0.00	0.00	1.00
cycles	7.00	7.00	1.00	1.00	0.00	5.00	2.00	0.00	0.00	0.00	0.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.33
Dispatch	7.00
Overall L1	7.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	84%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	60%

INT+FP

all	89%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	81%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	38%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	34%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

1% of peak load performance is reached (2.29 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 48cce0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ENDBR64																N/A
VPXOR %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPCMPEQD %XMM2,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	3	0.50	vect (25.0%)
VTESTPS %XMM2,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	vect (25.0%)
JE 48ccfa <__svml_idiv4_e9+0x1a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCVTDQ2PS %XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VRCPPS %XMM2,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	4	1	vect (25.0%)
VCVTPS2PD %XMM2,%YMM2	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	vect (25.0%)
VCVTDQ2PD %XMM1,%YMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	vect (25.0%)
VMULPD %YMM2,%YMM1,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0xe909(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VSUBPD %YMM3,%YMM4,%YMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM2,%YMM3,%YMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VCVTDQ2PD %XMM0,%YMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	vect (25.0%)
VMULPD %YMM0,%YMM2,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM1,%YMM2,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0x207cc(%RIP),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VSUBPD %YMM1,%YMM2,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM1,%YMM0,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VCVTTPD2DQ %YMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A

Name	Coverage (%)	Time (s)
○__svml_idiv4_e9	0.02	0.01

Report Configuration

Vectorization

Details

Workaround

512-bits vectorization

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Expensive FP math instructions/calls

Special instructions executing on a single port

Details

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code