OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .extracted.57]

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:44-49 [...]	Coverage (incl. loops): 2.32% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 44 - 49

--------------------------------------------------------------------------------

44: #pragma omp parallel for simd collapse(2)

45:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

46:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

47:         post_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

48:         pre_vol(i, j) = post_vol(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

49:       }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x426980 PUSH	%RBP

0x426981 MOV	%RSP,%RBP

0x426984 PUSH	%R15

0x426986 PUSH	%R14

0x426988 PUSH	%R13

0x42698a PUSH	%R12

0x42698c PUSH	%RBX

0x42698d SUB	$0xe8,%RSP

0x426994 MOV	%R8,%R13

0x426997 MOV	0x38(%RBP),%RAX

0x42699b MOV	0x28(%RBP),%R15

0x42699f MOV	0x20(%RBP),%R8

0x4269a3 MOV	0x10(%RBP),%R14

0x4269a7 MOV	0x18(%RBP),%EBX

0x4269aa MOVL	$0,-0x48(%RBP)

0x4269b1 TEST	%RAX,%RAX

0x4269b4 JS	426ec3

0x4269ba MOV	%RCX,%R12

0x4269bd MOV	%RDX,-0x38(%RBP)

0x4269c1 MOV	%R9,-0x40(%RBP)

0x4269c5 MOV	(%RDI),%ESI

0x4269c7 MOVQ	$0,-0x70(%RBP)

0x4269cf MOV	%RAX,-0x68(%RBP)

0x4269d3 MOVQ	$0x1,-0xa8(%RBP)

0x4269de SUB	$0x8,%RSP

0x4269e2 LEA	-0xa8(%RBP),%RAX

0x4269e9 LEA	-0x48(%RBP),%RCX

0x4269ed MOV	%R8,-0x50(%RBP)

0x4269f1 LEA	-0x70(%RBP),%R8

0x4269f5 LEA	-0x68(%RBP),%R9

0x4269f9 MOV	$0x4b7b50,%EDI

0x4269fe MOV	%ESI,-0x44(%RBP)

0x426a01 MOV	$0x22,%EDX

0x426a06 PUSH	$0x1

0x426a08 PUSH	$0x1

0x426a0a PUSH	%RAX

0x426a0b CALL	4031f0 <__kmpc_for_static_init_8@plt>

0x426a10 MOV	-0x50(%RBP),%R8

0x426a14 ADD	$0x20,%RSP

0x426a18 MOV	-0x70(%RBP),%RCX

0x426a1c MOV	-0x68(%RBP),%R9

0x426a20 CMP	%R9,%RCX

0x426a23 JA	426ea5

0x426a29 MOV	%R15,%RDI

0x426a2c SUB	%R8D,%EDI

0x426a2f MOV	(%R13),%RAX

0x426a33 MOV	%RAX,-0x30(%RBP)

0x426a37 MOV	0x10(%R13),%RAX

0x426a3b MOV	%RAX,-0x58(%RBP)

0x426a3f MOV	(%R12),%R10

0x426a43 MOV	0x10(%R12),%R11

0x426a48 MOV	(%R14),%RSI

0x426a4b MOV	0x10(%R14),%RDX

0x426a4f MOV	%RDX,-0x60(%RBP)

0x426a53 MOV	-0x38(%RBP),%RAX

0x426a57 MOV	(%RAX),%R12

0x426a5a MOV	0x10(%RAX),%R15

0x426a5e MOV	-0x40(%RBP),%RAX

0x426a62 MOV	(%RAX),%RDX

0x426a65 MOV	0x10(%RAX),%R14

0x426a69 INC	%R9

0x426a6c MOV	%R9,%RAX

0x426a6f SUB	%RCX,%RAX

0x426a72 MOV	$-0x2,%R13D

0x426a78 MOV	%RAX,-0x88(%RBP)

0x426a7f AND	%RAX,%R13

0x426a82 MOV	%RSI,-0x40(%RBP)

0x426a86 MOV	%RDX,-0x38(%RBP)

0x426a8a MOV	%R12,-0xa0(%RBP)

0x426a91 JE	426ed5

0x426a97 MOV	%R9,-0x78(%RBP)

0x426a9b MOV	%RDI,-0x80(%RBP)

0x426a9f MOVD	%EDI,%XMM0

0x426aa3 PSHUFD	$0x44,%XMM0,%XMM2

0x426aa8 MOVD	%EBX,%XMM0

0x426aac PSHUFD	$0x50,%XMM0,%XMM0

0x426ab1 MOVDQA	%XMM0,-0x100(%RBP)

0x426ab9 MOVD	%R8D,%XMM0

0x426abe PSHUFD	$0x50,%XMM0,%XMM0

0x426ac3 MOVDQA	%XMM0,-0xf0(%RBP)

0x426acb MOVQ	-0x30(%RBP),%XMM0

0x426ad0 PSHUFD	$0x44,%XMM0,%XMM3

0x426ad5 MOVQ	%R10,%XMM0

0x426ada PSHUFD	$0x44,%XMM0,%XMM4

0x426adf MOVQ	%RSI,%XMM0

0x426ae4 PSHUFD	$0x44,%XMM0,%XMM5

0x426ae9 MOVQ	%R12,%XMM0

0x426aee PSHUFD	$0x44,%XMM0,%XMM12

0x426af4 MOVQ	%RDX,%XMM0

0x426af9 MOVQ	%RCX,%XMM1

0x426afe PSHUFD	$0x44,%XMM1,%XMM7

0x426b03 PADDQ	0x74925(%RIP),%XMM7

0x426b0b PSHUFD	$0x44,%XMM0,%XMM8

0x426b11 XOR	%R12D,%R12D

0x426b14 MOVQ	%XMM2,-0x98(%RBP)

0x426b1c MOVDQA	%XMM2,-0x110(%RBP)

0x426b24 PSHUFD	$-0x12,%XMM2,%XMM0

0x426b29 MOVQ	%XMM0,-0x90(%RBP)

0x426b31 MOVDQA	%XMM3,-0xc0(%RBP)

0x426b39 MOVDQA	%XMM3,%XMM0

0x426b3d PSRLQ	$0x20,%XMM0

0x426b42 MOVDQA	%XMM0,-0xe0(%RBP)

0x426b4a MOVQ	-0x58(%RBP),%XMM0

0x426b4f PSHUFD	$0x44,%XMM0,%XMM0

0x426b54 MOVDQA	%XMM0,-0xd0(%RBP)

0x426b5c MOVDQA	%XMM4,%XMM13

0x426b61 PSRLQ	$0x20,%XMM13

0x426b67 MOVQ	%R11,%XMM0

0x426b6c PSHUFD	$0x44,%XMM0,%XMM14

0x426b72 PCMPEQD	%XMM10,%XMM10

0x426b77 NOPW	(%RAX,%RAX,1)

(184) 0x426b80 MOVQ	%XMM7,%RAX

(184) 0x426b85 XOR	%EDX,%EDX

(184) 0x426b87 DIVQ	-0x98(%RBP)

(184) 0x426b8e MOV	%RAX,%RSI

(184) 0x426b91 PSHUFD	$-0x12,%XMM7,%XMM0

(184) 0x426b96 MOVQ	%XMM0,%RAX

(184) 0x426b9b XOR	%EDX,%EDX

(184) 0x426b9d DIVQ	-0x90(%RBP)

(184) 0x426ba4 MOVQ	%RSI,%XMM1

(184) 0x426ba9 MOVQ	%RAX,%XMM0

(184) 0x426bae PUNPCKLQDQ	%XMM0,%XMM1

(184) 0x426bb2 PSHUFD	$-0x18,%XMM1,%XMM0

(184) 0x426bb7 PADDD	-0x100(%RBP),%XMM0

(184) 0x426bbf PMULUDQ	-0x110(%RBP),%XMM1

(184) 0x426bc7 MOVDQA	%XMM7,%XMM2

(184) 0x426bcb PSUBQ	%XMM1,%XMM2

(184) 0x426bcf PSHUFD	$-0x18,%XMM2,%XMM15

(184) 0x426bd5 PADDD	-0xf0(%RBP),%XMM15

(184) 0x426bde PXOR	%XMM11,%XMM11

(184) 0x426be3 PCMPGTD	%XMM15,%XMM11

(184) 0x426be8 PXOR	%XMM9,%XMM9

(184) 0x426bed PCMPGTD	%XMM0,%XMM9

(184) 0x426bf2 MOVDQA	%XMM0,%XMM1

(184) 0x426bf6 MOVDQA	%XMM15,%XMM2

(184) 0x426bfb PUNPCKLDQ	%XMM9,%XMM1

(184) 0x426c00 MOVDQA	-0xc0(%RBP),%XMM3

(184) 0x426c08 MOVDQA	%XMM3,%XMM6

(184) 0x426c0c PMULUDQ	%XMM1,%XMM6

(184) 0x426c10 PUNPCKLDQ	%XMM11,%XMM2

(184) 0x426c15 MOVDQA	-0xe0(%RBP),%XMM11

(184) 0x426c1e PUNPCKLDQ	0x73b79(%RIP),%XMM9

(184) 0x426c27 PMULUDQ	%XMM1,%XMM11

(184) 0x426c2c PMULUDQ	%XMM9,%XMM3

(184) 0x426c31 PADDQ	%XMM11,%XMM3

(184) 0x426c36 PSLLQ	$0x20,%XMM3

(184) 0x426c3b PADDQ	%XMM2,%XMM6

(184) 0x426c3f PADDQ	%XMM3,%XMM6

(184) 0x426c43 PSUBD	%XMM10,%XMM0

(184) 0x426c48 PXOR	%XMM3,%XMM3

(184) 0x426c4c PSLLQ	$0x3,%XMM6

(184) 0x426c51 PCMPGTD	%XMM0,%XMM3

(184) 0x426c55 PUNPCKLDQ	%XMM3,%XMM0

(184) 0x426c59 MOVDQA	%XMM4,%XMM11

(184) 0x426c5e PADDQ	-0xd0(%RBP),%XMM6

(184) 0x426c66 PMULUDQ	%XMM0,%XMM11

(184) 0x426c6b PMULUDQ	%XMM13,%XMM0

(184) 0x426c70 PSHUFD	$-0x2c,%XMM3,%XMM3

(184) 0x426c75 MOVQ	%XMM6,%RAX

(184) 0x426c7a PMULUDQ	%XMM4,%XMM3

(184) 0x426c7e PADDQ	%XMM0,%XMM3

(184) 0x426c82 PSLLQ	$0x20,%XMM3

(184) 0x426c87 PSHUFD	$-0x12,%XMM6,%XMM0

(184) 0x426c8c PADDQ	%XMM2,%XMM11

(184) 0x426c91 PADDQ	%XMM3,%XMM11

(184) 0x426c96 PSLLQ	$0x3,%XMM11

(184) 0x426c9c MOVQ	%XMM0,%RDX

(184) 0x426ca1 PADDQ	%XMM14,%XMM11

(184) 0x426ca6 MOVDQA	%XMM4,%XMM0

(184) 0x426caa PMULUDQ	%XMM1,%XMM0

(184) 0x426cae MOVQ	%XMM11,%RSI

(184) 0x426cb3 MOVDQA	%XMM13,%XMM3

(184) 0x426cb8 PMULUDQ	%XMM1,%XMM3

(184) 0x426cbc MOVDQA	%XMM4,%XMM6

(184) 0x426cc0 PSHUFD	$-0x12,%XMM11,%XMM11

(184) 0x426cc6 PMULUDQ	%XMM9,%XMM6

(184) 0x426ccb PADDQ	%XMM3,%XMM6

(184) 0x426ccf PSLLQ	$0x20,%XMM6

(184) 0x426cd4 MOVQ	%XMM11,%R9

(184) 0x426cd9 PADDQ	%XMM2,%XMM0

(184) 0x426cdd PADDQ	%XMM6,%XMM0

(184) 0x426ce1 PSLLQ	$0x3,%XMM0

(184) 0x426ce6 PADDQ	%XMM14,%XMM0

(184) 0x426ceb MOVDQA	%XMM5,%XMM3

(184) 0x426cef PMULUDQ	%XMM1,%XMM3

(184) 0x426cf3 MOVDQA	%XMM5,%XMM6

(184) 0x426cf7 MOVQ	%XMM0,%R8

(184) 0x426cfc PSRLQ	$0x20,%XMM6

(184) 0x426d01 PMULUDQ	%XMM1,%XMM6

(184) 0x426d05 MOVDQA	%XMM5,%XMM11

(184) 0x426d0a PSHUFD	$-0x12,%XMM0,%XMM0

(184) 0x426d0f PMULUDQ	%XMM9,%XMM11

(184) 0x426d14 PADDQ	%XMM6,%XMM11

(184) 0x426d19 PSLLQ	$0x20,%XMM11

(184) 0x426d1f MOVQ	%XMM0,%RDI

(184) 0x426d24 PADDQ	%XMM2,%XMM3

(184) 0x426d28 PADDQ	%XMM11,%XMM3

(184) 0x426d2d PSLLQ	$0x3,%XMM3

(184) 0x426d32 MOVSD	(%RAX),%XMM6

(184) 0x426d36 MOVQ	-0x60(%RBP),%XMM0

(184) 0x426d3b PSHUFD	$0x44,%XMM0,%XMM0

(184) 0x426d40 PADDQ	%XMM3,%XMM0

(184) 0x426d44 MOVSD	(%R8),%XMM11

(184) 0x426d49 MOVQ	%XMM0,%RAX

(184) 0x426d4e PSHUFD	$-0x12,%XMM0,%XMM0

(184) 0x426d53 MOVHPD	(%RDX),%XMM6

(184) 0x426d57 MOVQ	%XMM0,%RDX

(184) 0x426d5c PSUBD	%XMM10,%XMM15

(184) 0x426d61 PXOR	%XMM3,%XMM3

(184) 0x426d65 MOVSD	(%RSI),%XMM0

(184) 0x426d69 PCMPGTD	%XMM15,%XMM3

(184) 0x426d6e PUNPCKLDQ	%XMM3,%XMM15

(184) 0x426d73 MOVHPD	(%R9),%XMM0

(184) 0x426d78 MOVDQA	%XMM12,%XMM3

(184) 0x426d7d PSRLQ	$0x20,%XMM3

(184) 0x426d82 PMULUDQ	%XMM1,%XMM3

(184) 0x426d86 ADDPD	%XMM6,%XMM0

(184) 0x426d8a MOVDQA	%XMM12,%XMM6

(184) 0x426d8f PMULUDQ	%XMM9,%XMM6

(184) 0x426d94 MOVHPD	(%RDI),%XMM11

(184) 0x426d99 PADDQ	%XMM3,%XMM6

(184) 0x426d9d MOVDQA	%XMM12,%XMM3

(184) 0x426da2 PMULUDQ	%XMM1,%XMM3

(184) 0x426da6 PSLLQ	$0x20,%XMM6

(184) 0x426dab PADDQ	%XMM3,%XMM6

(184) 0x426daf PADDQ	%XMM6,%XMM15

(184) 0x426db4 PSLLQ	$0x3,%XMM15

(184) 0x426dba SUBPD	%XMM11,%XMM0

(184) 0x426dbf MOVQ	%R15,%XMM3

(184) 0x426dc4 PSHUFD	$0x44,%XMM3,%XMM3

(184) 0x426dc9 PADDQ	%XMM3,%XMM15

(184) 0x426dce MOVQ	%XMM15,%RSI

(184) 0x426dd3 PSHUFD	$-0x12,%XMM15,%XMM11

(184) 0x426dd9 PADDQ	%XMM2,%XMM6

(184) 0x426ddd PSLLQ	$0x3,%XMM6

(184) 0x426de2 MOVQ	%XMM11,%R9

(184) 0x426de7 PADDQ	%XMM3,%XMM6

(184) 0x426deb MOVDQA	%XMM8,%XMM3

(184) 0x426df0 MOVDQA	%XMM8,%XMM11

(184) 0x426df5 PMULUDQ	%XMM1,%XMM3

(184) 0x426df9 PSRLQ	$0x20,%XMM11

(184) 0x426dff PMULUDQ	%XMM1,%XMM11

(184) 0x426e04 PMULUDQ	%XMM8,%XMM9

(184) 0x426e09 PADDQ	%XMM11,%XMM9

(184) 0x426e0e PADDQ	%XMM2,%XMM3

(184) 0x426e12 PSLLQ	$0x20,%XMM9

(184) 0x426e18 PADDQ	%XMM9,%XMM3

(184) 0x426e1d PSLLQ	$0x3,%XMM3

(184) 0x426e22 MOVQ	%R14,%XMM1

(184) 0x426e27 PSHUFD	$0x44,%XMM1,%XMM1

(184) 0x426e2c PADDQ	%XMM3,%XMM1

(184) 0x426e30 MOVLPD	%XMM0,(%RAX)

(184) 0x426e34 MOVHPD	%XMM0,(%RDX)

(184) 0x426e38 MOVQ	%XMM6,%RAX

(184) 0x426e3d PSHUFD	$-0x12,%XMM6,%XMM2

(184) 0x426e42 MOVQ	%XMM2,%RDX

(184) 0x426e47 MOVSD	(%RSI),%XMM2

(184) 0x426e4b MOVHPD	(%R9),%XMM2

(184) 0x426e50 ADDPD	%XMM0,%XMM2

(184) 0x426e54 MOVSD	(%RAX),%XMM0

(184) 0x426e58 MOVHPD	(%RDX),%XMM0

(184) 0x426e5c SUBPD	%XMM0,%XMM2

(184) 0x426e60 MOVQ	%XMM1,%RAX

(184) 0x426e65 PSHUFD	$-0x12,%XMM1,%XMM0

(184) 0x426e6a MOVQ	%XMM0,%RDX

(184) 0x426e6f MOVLPD	%XMM2,(%RAX)

(184) 0x426e73 MOVHPD	%XMM2,(%RDX)

(184) 0x426e77 PADDQ	0x745d1(%RIP),%XMM7

(184) 0x426e7f ADD	$0x2,%R12

(184) 0x426e83 CMP	%R13,%R12

(184) 0x426e86 JB	426b80

0x426e8c CMP	%R13,-0x88(%RBP)

0x426e93 MOV	-0x80(%RBP),%RDI

0x426e97 MOV	-0x50(%RBP),%R8

0x426e9b MOV	-0x78(%RBP),%R9

0x426e9f MOV	-0x30(%RBP),%R12

0x426ea3 JNE	426ede

0x426ea5 MOV	$0x4b7b70,%EDI

0x426eaa MOV	-0x44(%RBP),%ESI

0x426ead ADD	$0xe8,%RSP

0x426eb4 POP	%RBX

0x426eb5 POP	%R12

0x426eb7 POP	%R13

0x426eb9 POP	%R14

0x426ebb POP	%R15

0x426ebd POP	%RBP

0x426ebe JMP	403050

0x426ec3 ADD	$0xe8,%RSP

0x426eca POP	%RBX

0x426ecb POP	%R12

0x426ecd POP	%R13

0x426ecf POP	%R14

0x426ed1 POP	%R15

0x426ed3 POP	%RBP

0x426ed4 RET

0x426ed5 MOV	-0x30(%RBP),%R12

0x426ed9 JMP	426f87

0x426ede ADD	%R13,%RCX

0x426ee1 JMP	426f87

0x426ee6 NOPW	%CS:(%RAX,%RAX,1)

(183) 0x426ef0 MOV	%RCX,%RAX

(183) 0x426ef3 XOR	%EDX,%EDX

(183) 0x426ef5 DIV	%RDI

(183) 0x426ef8 LEA	(%RAX,%RBX,1),%ESI

(183) 0x426efb ADD	%R8D,%EDX

(183) 0x426efe MOVSXD	%EDX,%RDX

(183) 0x426f01 MOVSXD	%ESI,%RSI

(183) 0x426f04 ADD	%EBX,%EAX

(183) 0x426f06 INC	%EAX

(183) 0x426f08 CLTQ

(183) 0x426f0a IMUL	%R10,%RAX

(183) 0x426f0e ADD	%RDX,%RAX

(183) 0x426f11 MOVSD	(%R11,%RAX,8),%XMM0

(183) 0x426f17 MOV	%R12,%RAX

(183) 0x426f1a IMUL	%RSI,%RAX

(183) 0x426f1e ADD	%RDX,%RAX

(183) 0x426f21 MOV	-0x58(%RBP),%R13

(183) 0x426f25 ADDSD	(%R13,%RAX,8),%XMM0

(183) 0x426f2c MOV	%R10,%RAX

(183) 0x426f2f IMUL	%RSI,%RAX

(183) 0x426f33 ADD	%RDX,%RAX

(183) 0x426f36 SUBSD	(%R11,%RAX,8),%XMM0

(183) 0x426f3c MOV	-0x40(%RBP),%RAX

(183) 0x426f40 IMUL	%RSI,%RAX

(183) 0x426f44 ADD	%RDX,%RAX

(183) 0x426f47 MOV	-0x60(%RBP),%R13

(183) 0x426f4b MOVSD	%XMM0,(%R13,%RAX,8)

(183) 0x426f52 MOV	-0xa0(%RBP),%RAX

(183) 0x426f59 IMUL	%RSI,%RAX

(183) 0x426f5d ADD	%RDX,%RAX

(183) 0x426f60 ADDSD	0x8(%R15,%RAX,8),%XMM0

(183) 0x426f67 SUBSD	(%R15,%RAX,8),%XMM0

(183) 0x426f6d IMUL	-0x38(%RBP),%RSI

(183) 0x426f72 ADD	%RDX,%RSI

(183) 0x426f75 MOVSD	%XMM0,(%R14,%RSI,8)

(183) 0x426f7b INC	%RCX

(183) 0x426f7e CMP	%RCX,%R9

(183) 0x426f81 JE	426ea5

(183) 0x426f87 MOV	%RCX,%RAX

(183) 0x426f8a SHR	$0x20,%RAX

(183) 0x426f8e JNE	426ef0

(183) 0x426f94 MOV	%ECX,%EAX

(183) 0x426f96 XOR	%EDX,%EDX

(183) 0x426f98 DIV	%EDI

(183) 0x426f9a JMP	426ef8

0x426f9f NOP

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:44-49
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:44-49
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.67 to 10.50 cycles (2.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 23.67 to 2.57 cycles (9.21x speedup).

Details

30% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
24% of SSE/AVX stores are used in vector version.
14% of SSE/AVX addition or subtraction instructions are used in vector version.
56% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:44

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 244 bytes. The binary function is storing 240 bytes.

General properties

nb instructions	141
nb uops	142
loop length	613
used x86 registers	16
used mmx registers	0
used xmm registers	12
used ymm registers	0
used zmm registers	0
nb stack references	28

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.67 cycles
front end	23.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.70	10.50	14.67	14.67	17.50	10.50	7.70	17.50	17.50	17.50	7.60	14.67
cycles	7.70	10.50	14.67	14.67	17.50	10.50	7.70	17.50	17.50	17.50	7.60	14.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.67
Dispatch	17.50
Overall L1	23.67

Vectorization ratios

all	30%
load	5%
store	24%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	56%

Vector efficiency ratios

all	15%
load	12%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.67 cycles. At this rate:

5% of peak load performance is reached (10.31 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (10.14 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 23.67 to 17.50 cycles (1.35x speedup).

ASM code

In the binary file, the address of the function is: 426980

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xe8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R8,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 426ec3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.57+0x543>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xa8(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x48(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x70(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x68(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b7b50,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x50(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x70(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 426ea5 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.57+0x525>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R8D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV (%R13),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%R13),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%R12),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R12),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RDX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RAX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RAX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $-0x2,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND %RAX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RSI,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 426ed5 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.57+0x555>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %EDI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVD %EBX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVD %R8D,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ -0x30(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R10,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RSI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R12,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RDX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
MOVQ %RCX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x74925(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PSHUFD $0x44,%XMM0,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ %XMM2,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM2,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM2,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM3,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM0,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ -0x58(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM4,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R11,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PCMPEQD %XMM10,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R13,-0x88(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x80(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x78(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 426ede <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.57+0x55e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b7b70,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0xe8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0xe8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV -0x30(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 426f87 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.57+0x607>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD %R13,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 426f87 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.57+0x607>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:44-49
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:44-49
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

30% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
24% of SSE/AVX stores are used in vector version.
14% of SSE/AVX addition or subtraction instructions are used in vector version.
56% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:44

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 244 bytes. The binary function is storing 240 bytes.

General properties

nb instructions	141
nb uops	142
loop length	613
used x86 registers	16
used mmx registers	0
used xmm registers	12
used ymm registers	0
used zmm registers	0
nb stack references	28

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.67 cycles
front end	23.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.70	10.50	14.67	14.67	17.50	10.50	7.70	17.50	17.50	17.50	7.60	14.67
cycles	7.70	10.50	14.67	14.67	17.50	10.50	7.70	17.50	17.50	17.50	7.60	14.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.67
Dispatch	17.50
Overall L1	23.67

Vectorization ratios

all	30%
load	5%
store	24%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	56%

Vector efficiency ratios

all	15%
load	12%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.67 cycles. At this rate:

5% of peak load performance is reached (10.31 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (10.14 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 426980

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xe8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R8,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 426ec3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.57+0x543>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xa8(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x48(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x70(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x68(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b7b50,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x50(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x70(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 426ea5 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.57+0x525>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R8D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV (%R13),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%R13),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%R12),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R12),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RDX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RAX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RAX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $-0x2,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND %RAX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RSI,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 426ed5 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.57+0x555>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %EDI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVD %EBX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVD %R8D,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ -0x30(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R10,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RSI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R12,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RDX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
MOVQ %RCX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x74925(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PSHUFD $0x44,%XMM0,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ %XMM2,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM2,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM2,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM3,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM0,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ -0x58(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM4,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R11,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PCMPEQD %XMM10,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R13,-0x88(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x80(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x78(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 426ede <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.57+0x55e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b7b70,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0xe8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0xe8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV -0x30(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 426f87 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.57+0x607>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD %R13,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 426f87 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.57+0x607>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.32	0.92
○Loop 184 - advec_mom.cpp:45-49 - exec	2.32	0.91
○Loop 183 - advec_mom.cpp:45-49 - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

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