OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .extracted.52]

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:53-58 [...]	Coverage (incl. loops): 2.27% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 53 - 58

--------------------------------------------------------------------------------

53: #pragma omp parallel for simd collapse(2)

54:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

55:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

56:         post_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

57:         pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

58:       }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x426340 PUSH	%RBP

0x426341 MOV	%RSP,%RBP

0x426344 PUSH	%R15

0x426346 PUSH	%R14

0x426348 PUSH	%R13

0x42634a PUSH	%R12

0x42634c PUSH	%RBX

0x42634d SUB	$0xf8,%RSP

0x426354 MOV	%RDX,%R12

0x426357 MOV	0x38(%RBP),%RAX

0x42635b MOV	0x28(%RBP),%R15

0x42635f MOV	0x20(%RBP),%RDX

0x426363 MOV	0x10(%RBP),%R14

0x426367 MOV	0x18(%RBP),%EBX

0x42636a MOVL	$0,-0x48(%RBP)

0x426371 TEST	%RAX,%RAX

0x426374 JS	426897

0x42637a MOV	%R8,%R13

0x42637d MOV	%RCX,-0x30(%RBP)

0x426381 MOV	%R9,-0x40(%RBP)

0x426385 MOV	%RDX,-0x58(%RBP)

0x426389 MOV	(%RDI),%ESI

0x42638b MOVQ	$0,-0x70(%RBP)

0x426393 MOV	%RAX,-0x68(%RBP)

0x426397 MOVQ	$0x1,-0xa8(%RBP)

0x4263a2 SUB	$0x8,%RSP

0x4263a6 LEA	-0xa8(%RBP),%RAX

0x4263ad LEA	-0x48(%RBP),%RCX

0x4263b1 LEA	-0x70(%RBP),%R8

0x4263b5 LEA	-0x68(%RBP),%R9

0x4263b9 MOV	$0x4b7af0,%EDI

0x4263be MOV	%ESI,-0x44(%RBP)

0x4263c1 MOV	$0x22,%EDX

0x4263c6 PUSH	$0x1

0x4263c8 PUSH	$0x1

0x4263ca PUSH	%RAX

0x4263cb CALL	4031f0 <__kmpc_for_static_init_8@plt>

0x4263d0 ADD	$0x20,%RSP

0x4263d4 MOV	-0x70(%RBP),%RCX

0x4263d8 MOV	-0x68(%RBP),%RAX

0x4263dc CMP	%RAX,%RCX

0x4263df JA	426879

0x4263e5 MOV	%R15,%R10

0x4263e8 MOV	%RAX,%RDX

0x4263eb MOV	-0x58(%RBP),%RAX

0x4263ef SUB	%EAX,%R10D

0x4263f2 MOV	(%R13),%RSI

0x4263f6 MOV	%RSI,-0x38(%RBP)

0x4263fa MOV	0x10(%R13),%RDI

0x4263fe MOV	%RDI,-0x50(%RBP)

0x426402 MOV	(%R12),%R8

0x426406 MOV	0x10(%R12),%R11

0x42640b MOV	(%R14),%R12

0x42640e MOV	0x10(%R14),%RSI

0x426412 MOV	-0x30(%RBP),%RDI

0x426416 MOV	(%RDI),%R9

0x426419 MOV	0x10(%RDI),%R15

0x42641d MOV	-0x40(%RBP),%R14

0x426421 MOV	(%R14),%RDI

0x426424 MOV	0x10(%R14),%R14

0x426428 INC	%RDX

0x42642b MOV	%RDX,-0x40(%RBP)

0x42642f SUB	%RCX,%RDX

0x426432 MOV	$-0x2,%R13D

0x426438 MOV	%RDX,-0x80(%RBP)

0x42643c AND	%RDX,%R13

0x42643f MOV	%R8,-0x30(%RBP)

0x426443 MOV	%R12,-0xa0(%RBP)

0x42644a MOV	%RSI,-0x60(%RBP)

0x42644e MOV	%RDI,-0x98(%RBP)

0x426455 JE	4268a9

0x42645b MOV	%R10,-0x78(%RBP)

0x42645f MOVD	%R10D,%XMM0

0x426464 PSHUFD	$0x44,%XMM0,%XMM2

0x426469 MOVD	%EBX,%XMM0

0x42646d PSHUFD	$0x50,%XMM0,%XMM0

0x426472 MOVDQA	%XMM0,-0x110(%RBP)

0x42647a MOVD	%EAX,%XMM0

0x42647e PSHUFD	$0x50,%XMM0,%XMM0

0x426483 MOVDQA	%XMM0,-0x100(%RBP)

0x42648b MOVQ	-0x38(%RBP),%XMM0

0x426490 PSHUFD	$0x44,%XMM0,%XMM3

0x426495 MOVQ	%R8,%XMM0

0x42649a PSHUFD	$0x44,%XMM0,%XMM13

0x4264a0 MOVQ	%R12,%XMM0

0x4264a5 PSHUFD	$0x44,%XMM0,%XMM5

0x4264aa MOVQ	%R9,%XMM0

0x4264af PSHUFD	$0x44,%XMM0,%XMM6

0x4264b4 MOVQ	%RDI,%XMM0

0x4264b9 MOVQ	%RCX,%XMM1

0x4264be PSHUFD	$0x44,%XMM1,%XMM7

0x4264c3 PADDQ	0x74f65(%RIP),%XMM7

0x4264cb PSHUFD	$0x44,%XMM0,%XMM8

0x4264d1 XOR	%R8D,%R8D

0x4264d4 MOVQ	%XMM2,-0x90(%RBP)

0x4264dc MOVDQA	%XMM2,-0x120(%RBP)

0x4264e4 PSHUFD	$-0x12,%XMM2,%XMM0

0x4264e9 MOVQ	%XMM0,-0x88(%RBP)

0x4264f1 MOVDQA	%XMM3,-0xd0(%RBP)

0x4264f9 MOVDQA	%XMM3,%XMM0

0x4264fd PSRLQ	$0x20,%XMM0

0x426502 MOVDQA	%XMM0,-0xf0(%RBP)

0x42650a MOVQ	-0x50(%RBP),%XMM0

0x42650f PSHUFD	$0x44,%XMM0,%XMM0

0x426514 MOVDQA	%XMM0,-0xe0(%RBP)

0x42651c MOVDQA	%XMM13,%XMM0

0x426521 PSRLQ	$0x20,%XMM0

0x426526 MOVDQA	%XMM0,-0xc0(%RBP)

0x42652e MOVQ	%R11,%XMM0

0x426533 PSHUFD	$0x44,%XMM0,%XMM14

0x426539 PCMPEQD	%XMM11,%XMM11

0x42653e XCHG	%AX,%AX

(182) 0x426540 MOVQ	%XMM7,%RAX

(182) 0x426545 XOR	%EDX,%EDX

(182) 0x426547 DIVQ	-0x90(%RBP)

(182) 0x42654e MOV	%RAX,%RSI

(182) 0x426551 PSHUFD	$-0x12,%XMM7,%XMM0

(182) 0x426556 MOVQ	%XMM0,%RAX

(182) 0x42655b XOR	%EDX,%EDX

(182) 0x42655d DIVQ	-0x88(%RBP)

(182) 0x426564 MOVQ	%RSI,%XMM0

(182) 0x426569 MOVQ	%RAX,%XMM1

(182) 0x42656e PUNPCKLQDQ	%XMM1,%XMM0

(182) 0x426572 PSHUFD	$-0x18,%XMM0,%XMM1

(182) 0x426577 PADDD	-0x110(%RBP),%XMM1

(182) 0x42657f PMULUDQ	-0x120(%RBP),%XMM0

(182) 0x426587 MOVDQA	%XMM7,%XMM2

(182) 0x42658b PSUBQ	%XMM0,%XMM2

(182) 0x42658f PSHUFD	$-0x18,%XMM2,%XMM15

(182) 0x426595 PXOR	%XMM4,%XMM4

(182) 0x426599 PXOR	%XMM9,%XMM9

(182) 0x42659e PADDD	-0x100(%RBP),%XMM15

(182) 0x4265a7 PCMPGTD	%XMM1,%XMM9

(182) 0x4265ac MOVDQA	%XMM1,%XMM2

(182) 0x4265b0 PUNPCKLDQ	%XMM9,%XMM2

(182) 0x4265b5 PCMPGTD	%XMM15,%XMM4

(182) 0x4265ba MOVDQA	-0xd0(%RBP),%XMM10

(182) 0x4265c3 MOVDQA	%XMM10,%XMM3

(182) 0x4265c8 PMULUDQ	%XMM2,%XMM3

(182) 0x4265cc MOVDQA	-0xf0(%RBP),%XMM12

(182) 0x4265d5 MOVDQA	%XMM15,%XMM0

(182) 0x4265da PMULUDQ	%XMM2,%XMM12

(182) 0x4265df PUNPCKLDQ	0x741b8(%RIP),%XMM9

(182) 0x4265e8 PUNPCKLDQ	%XMM4,%XMM0

(182) 0x4265ec PMULUDQ	%XMM9,%XMM10

(182) 0x4265f1 PADDQ	%XMM12,%XMM10

(182) 0x4265f6 PSUBD	%XMM11,%XMM15

(182) 0x4265fb PSLLQ	$0x20,%XMM10

(182) 0x426601 PXOR	%XMM4,%XMM4

(182) 0x426605 PCMPGTD	%XMM15,%XMM4

(182) 0x42660a MOVDQA	-0xc0(%RBP),%XMM12

(182) 0x426613 PUNPCKLDQ	%XMM4,%XMM15

(182) 0x426618 PMULUDQ	%XMM2,%XMM12

(182) 0x42661d MOVDQA	%XMM13,%XMM4

(182) 0x426622 PMULUDQ	%XMM9,%XMM4

(182) 0x426627 PADDQ	%XMM0,%XMM3

(182) 0x42662b PADDQ	%XMM12,%XMM4

(182) 0x426630 MOVDQA	%XMM13,%XMM12

(182) 0x426635 PMULUDQ	%XMM2,%XMM12

(182) 0x42663a PADDQ	%XMM10,%XMM3

(182) 0x42663f PSLLQ	$0x20,%XMM4

(182) 0x426644 PADDQ	%XMM12,%XMM4

(182) 0x426649 MOVDQA	%XMM5,%XMM10

(182) 0x42664e PSRLQ	$0x20,%XMM10

(182) 0x426654 PMULUDQ	%XMM2,%XMM10

(182) 0x426659 MOVDQA	%XMM5,%XMM12

(182) 0x42665e PMULUDQ	%XMM9,%XMM12

(182) 0x426663 PADDQ	%XMM10,%XMM12

(182) 0x426668 PSLLQ	$0x3,%XMM3

(182) 0x42666d PADDQ	-0xe0(%RBP),%XMM3

(182) 0x426675 MOVQ	%XMM3,%RSI

(182) 0x42667a PSHUFD	$-0x12,%XMM3,%XMM3

(182) 0x42667f PADDQ	%XMM4,%XMM15

(182) 0x426684 PSLLQ	$0x3,%XMM15

(182) 0x42668a PADDQ	%XMM14,%XMM15

(182) 0x42668f MOVQ	%XMM3,%R12

(182) 0x426694 MOVDQA	%XMM5,%XMM3

(182) 0x426698 PMULUDQ	%XMM2,%XMM3

(182) 0x42669c PSLLQ	$0x20,%XMM12

(182) 0x4266a2 PADDQ	%XMM0,%XMM3

(182) 0x4266a6 PADDQ	%XMM12,%XMM3

(182) 0x4266ab MOVQ	-0x60(%RBP),%XMM10

(182) 0x4266b1 PSHUFD	$0x44,%XMM10,%XMM10

(182) 0x4266b7 PSLLQ	$0x3,%XMM3

(182) 0x4266bc PADDQ	%XMM3,%XMM10

(182) 0x4266c1 PSHUFD	$-0x12,%XMM15,%XMM12

(182) 0x4266c7 MOVQ	%XMM10,%RAX

(182) 0x4266cc MOVQ	%XMM15,%RDI

(182) 0x4266d1 PSHUFD	$-0x12,%XMM10,%XMM3

(182) 0x4266d7 PSUBD	%XMM11,%XMM1

(182) 0x4266dc PXOR	%XMM10,%XMM10

(182) 0x4266e1 MOVQ	%XMM3,%RDX

(182) 0x4266e6 PCMPGTD	%XMM1,%XMM10

(182) 0x4266eb PUNPCKLDQ	%XMM10,%XMM1

(182) 0x4266f0 MOVDQA	%XMM6,%XMM3

(182) 0x4266f4 MOVQ	%XMM12,%R10

(182) 0x4266f9 PMULUDQ	%XMM1,%XMM3

(182) 0x4266fd MOVDQA	%XMM6,%XMM15

(182) 0x426702 PSRLQ	$0x20,%XMM15

(182) 0x426708 PMULUDQ	%XMM15,%XMM1

(182) 0x42670d PSHUFD	$-0x2c,%XMM10,%XMM10

(182) 0x426713 PMULUDQ	%XMM6,%XMM10

(182) 0x426718 PADDQ	%XMM1,%XMM10

(182) 0x42671d MOVSD	(%RSI),%XMM12

(182) 0x426722 PADDQ	%XMM0,%XMM4

(182) 0x426726 PSLLQ	$0x3,%XMM4

(182) 0x42672b MOVHPD	(%R12),%XMM12

(182) 0x426731 PADDQ	%XMM14,%XMM4

(182) 0x426736 MOVQ	%XMM4,%RSI

(182) 0x42673b PSHUFD	$-0x12,%XMM4,%XMM1

(182) 0x426740 MOVQ	%XMM1,%R12

(182) 0x426745 MOVSD	(%RDI),%XMM1

(182) 0x426749 MOVHPD	(%R10),%XMM1

(182) 0x42674e ADDPD	%XMM12,%XMM1

(182) 0x426753 PSLLQ	$0x20,%XMM10

(182) 0x426759 PADDQ	%XMM0,%XMM3

(182) 0x42675d PADDQ	%XMM10,%XMM3

(182) 0x426762 MOVSD	(%RSI),%XMM4

(182) 0x426766 MOVHPD	(%R12),%XMM4

(182) 0x42676c PMULUDQ	%XMM2,%XMM15

(182) 0x426771 SUBPD	%XMM4,%XMM1

(182) 0x426775 MOVDQA	%XMM6,%XMM10

(182) 0x42677a PMULUDQ	%XMM9,%XMM10

(182) 0x42677f PADDQ	%XMM15,%XMM10

(182) 0x426784 MOVDQA	%XMM6,%XMM4

(182) 0x426788 PMULUDQ	%XMM2,%XMM4

(182) 0x42678c PSLLQ	$0x20,%XMM10

(182) 0x426792 PADDQ	%XMM0,%XMM4

(182) 0x426796 PSLLQ	$0x3,%XMM3

(182) 0x42679b PADDQ	%XMM10,%XMM4

(182) 0x4267a0 MOVQ	%R15,%XMM10

(182) 0x4267a5 PSHUFD	$0x44,%XMM10,%XMM10

(182) 0x4267ab PADDQ	%XMM10,%XMM3

(182) 0x4267b0 MOVQ	%XMM3,%RSI

(182) 0x4267b5 PSHUFD	$-0x12,%XMM3,%XMM3

(182) 0x4267ba PSLLQ	$0x3,%XMM4

(182) 0x4267bf MOVQ	%XMM3,%R12

(182) 0x4267c4 PADDQ	%XMM10,%XMM4

(182) 0x4267c9 MOVDQA	%XMM8,%XMM3

(182) 0x4267ce MOVDQA	%XMM8,%XMM10

(182) 0x4267d3 PMULUDQ	%XMM2,%XMM3

(182) 0x4267d7 PSRLQ	$0x20,%XMM10

(182) 0x4267dd PMULUDQ	%XMM2,%XMM10

(182) 0x4267e2 PMULUDQ	%XMM8,%XMM9

(182) 0x4267e7 PADDQ	%XMM10,%XMM9

(182) 0x4267ec PADDQ	%XMM0,%XMM3

(182) 0x4267f0 PSLLQ	$0x20,%XMM9

(182) 0x4267f6 PADDQ	%XMM9,%XMM3

(182) 0x4267fb PSLLQ	$0x3,%XMM3

(182) 0x426800 MOVQ	%R14,%XMM0

(182) 0x426805 PSHUFD	$0x44,%XMM0,%XMM0

(182) 0x42680a PADDQ	%XMM3,%XMM0

(182) 0x42680e MOVLPD	%XMM1,(%RAX)

(182) 0x426812 MOVHPD	%XMM1,(%RDX)

(182) 0x426816 MOVQ	%XMM4,%RAX

(182) 0x42681b PSHUFD	$-0x12,%XMM4,%XMM2

(182) 0x426820 MOVQ	%XMM2,%RDX

(182) 0x426825 MOVSD	(%RSI),%XMM2

(182) 0x426829 MOVHPD	(%R12),%XMM2

(182) 0x42682f ADDPD	%XMM1,%XMM2

(182) 0x426833 MOVSD	(%RAX),%XMM1

(182) 0x426837 MOVHPD	(%RDX),%XMM1

(182) 0x42683b SUBPD	%XMM1,%XMM2

(182) 0x42683f MOVQ	%XMM0,%RAX

(182) 0x426844 PSHUFD	$-0x12,%XMM0,%XMM0

(182) 0x426849 MOVQ	%XMM0,%RDX

(182) 0x42684e MOVLPD	%XMM2,(%RAX)

(182) 0x426852 MOVHPD	%XMM2,(%RDX)

(182) 0x426856 PADDQ	0x74bf2(%RIP),%XMM7

(182) 0x42685e ADD	$0x2,%R8

(182) 0x426862 CMP	%R13,%R8

(182) 0x426865 JB	426540

0x42686b CMP	%R13,-0x80(%RBP)

0x42686f MOV	-0x78(%RBP),%R10

0x426873 MOV	-0x38(%RBP),%R12

0x426877 JNE	4268b2

0x426879 MOV	$0x4b7b10,%EDI

0x42687e MOV	-0x44(%RBP),%ESI

0x426881 ADD	$0xf8,%RSP

0x426888 POP	%RBX

0x426889 POP	%R12

0x42688b POP	%R13

0x42688d POP	%R14

0x42688f POP	%R15

0x426891 POP	%RBP

0x426892 JMP	403050

0x426897 ADD	$0xf8,%RSP

0x42689e POP	%RBX

0x42689f POP	%R12

0x4268a1 POP	%R13

0x4268a3 POP	%R14

0x4268a5 POP	%R15

0x4268a7 POP	%RBP

0x4268a8 RET

0x4268a9 MOV	-0x38(%RBP),%R12

0x4268ad JMP	42695a

0x4268b2 ADD	%R13,%RCX

0x4268b5 JMP	42695a

0x4268ba NOPW	(%RAX,%RAX,1)

(181) 0x4268c0 MOV	%RCX,%RAX

(181) 0x4268c3 XOR	%EDX,%EDX

(181) 0x4268c5 DIV	%R10

(181) 0x4268c8 MOV	-0x30(%RBP),%R8

(181) 0x4268cc LEA	(%RAX,%RBX,1),%ESI

(181) 0x4268cf ADD	-0x58(%RBP),%EDX

(181) 0x4268d2 MOVSXD	%EDX,%RDX

(181) 0x4268d5 MOVSXD	%ESI,%RSI

(181) 0x4268d8 MOV	%R12,%RDI

(181) 0x4268db IMUL	%RSI,%RDI

(181) 0x4268df ADD	%RDX,%RDI

(181) 0x4268e2 IMUL	%RSI,%R8

(181) 0x4268e6 ADD	%RDX,%R8

(181) 0x4268e9 MOVSD	0x8(%R11,%R8,8),%XMM0

(181) 0x4268f0 MOV	-0x50(%RBP),%R13

(181) 0x4268f4 ADDSD	(%R13,%RDI,8),%XMM0

(181) 0x4268fb SUBSD	(%R11,%R8,8),%XMM0

(181) 0x426901 MOV	-0xa0(%RBP),%RDI

(181) 0x426908 IMUL	%RSI,%RDI

(181) 0x42690c ADD	%RDX,%RDI

(181) 0x42690f MOV	-0x60(%RBP),%R8

(181) 0x426913 MOVSD	%XMM0,(%R8,%RDI,8)

(181) 0x426919 ADD	%EBX,%EAX

(181) 0x42691b INC	%EAX

(181) 0x42691d CLTQ

(181) 0x42691f IMUL	%R9,%RAX

(181) 0x426923 ADD	%RDX,%RAX

(181) 0x426926 ADDSD	(%R15,%RAX,8),%XMM0

(181) 0x42692c MOV	%R9,%RAX

(181) 0x42692f IMUL	%RSI,%RAX

(181) 0x426933 ADD	%RDX,%RAX

(181) 0x426936 SUBSD	(%R15,%RAX,8),%XMM0

(181) 0x42693c IMUL	-0x98(%RBP),%RSI

(181) 0x426944 ADD	%RDX,%RSI

(181) 0x426947 MOVSD	%XMM0,(%R14,%RSI,8)

(181) 0x42694d INC	%RCX

(181) 0x426950 CMP	%RCX,-0x40(%RBP)

(181) 0x426954 JE	426879

(181) 0x42695a MOV	%RCX,%RAX

(181) 0x42695d SHR	$0x20,%RAX

(181) 0x426961 JNE	4268c0

(181) 0x426967 MOV	%ECX,%EAX

(181) 0x426969 XOR	%EDX,%EDX

(181) 0x42696b DIV	%R10D

(181) 0x42696e JMP	4268c8

0x426973 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:53-58
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:53-58
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.50 to 10.50 cycles (2.24x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 23.50 to 2.57 cycles (9.14x speedup).

Details

30% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

6% of SSE/AVX loads are used in vector version.
26% of SSE/AVX stores are used in vector version.
11% of SSE/AVX addition or subtraction instructions are used in vector version.
51% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:53

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 228 bytes. The binary function is storing 256 bytes.

General properties

nb instructions	140
nb uops	141
loop length	610
used x86 registers	16
used mmx registers	0
used xmm registers	11
used ymm registers	0
used zmm registers	0
nb stack references	29

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.50 cycles
front end	23.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.70	10.50	14.00	14.00	18.00	10.50	7.70	18.00	18.00	18.00	7.60	14.00
cycles	7.70	10.50	14.00	14.00	18.00	10.50	7.70	18.00	18.00	18.00	7.60	14.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.50
Dispatch	18.00
Overall L1	23.50

Vectorization ratios

all	30%
load	6%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	51%

Vector efficiency ratios

all	15%
load	12%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.50 cycles. At this rate:

5% of peak load performance is reached (9.70 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (10.89 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 23.50 to 18.00 cycles (1.31x speedup).

ASM code

In the binary file, the address of the function is: 426340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xf8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 426897 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.52+0x557>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xa8(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x48(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x70(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x68(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b7af0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x70(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 426879 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.52+0x539>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EAX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%R13),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RSI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%R13),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%R12),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R12),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R14),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RDI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV $-0x2,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND %RDX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R8,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 4268a9 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.52+0x569>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R10,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %R10D,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVD %EBX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVD %EAX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ -0x38(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R8,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R12,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R9,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RDI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
MOVQ %RCX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x74f65(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PSHUFD $0x44,%XMM0,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOVQ %XMM2,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM2,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM2,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM3,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM0,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ -0x50(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM0,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R11,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PCMPEQD %XMM11,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R13,-0x80(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x78(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x38(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 4268b2 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.52+0x572>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b7b10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0xf8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0xf8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV -0x38(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 42695a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.52+0x61a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD %R13,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 42695a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.52+0x61a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:53-58
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:53-58
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

30% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

6% of SSE/AVX loads are used in vector version.
26% of SSE/AVX stores are used in vector version.
11% of SSE/AVX addition or subtraction instructions are used in vector version.
51% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:53

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 228 bytes. The binary function is storing 256 bytes.

General properties

nb instructions	140
nb uops	141
loop length	610
used x86 registers	16
used mmx registers	0
used xmm registers	11
used ymm registers	0
used zmm registers	0
nb stack references	29

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.50 cycles
front end	23.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.70	10.50	14.00	14.00	18.00	10.50	7.70	18.00	18.00	18.00	7.60	14.00
cycles	7.70	10.50	14.00	14.00	18.00	10.50	7.70	18.00	18.00	18.00	7.60	14.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.50
Dispatch	18.00
Overall L1	23.50

Vectorization ratios

all	30%
load	6%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	51%

Vector efficiency ratios

all	15%
load	12%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.50 cycles. At this rate:

5% of peak load performance is reached (9.70 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (10.89 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 426340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xf8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 426897 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.52+0x557>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xa8(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x48(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x70(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x68(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b7af0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x70(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 426879 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.52+0x539>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EAX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%R13),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RSI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%R13),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%R12),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R12),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R14),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RDI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV $-0x2,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND %RDX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R8,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 4268a9 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.52+0x569>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R10,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %R10D,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVD %EBX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVD %EAX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ -0x38(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R8,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R12,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R9,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RDI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
MOVQ %RCX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x74f65(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PSHUFD $0x44,%XMM0,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOVQ %XMM2,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM2,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM2,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM3,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM0,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ -0x50(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM0,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R11,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PCMPEQD %XMM11,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R13,-0x80(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x78(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x38(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 4268b2 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.52+0x572>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b7b10,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0xf8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0xf8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV -0x38(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 42695a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.52+0x61a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD %R13,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 42695a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.52+0x61a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.27	0.90
○Loop 182 - advec_mom.cpp:54-58 - exec	2.27	0.89
○Loop 181 - advec_mom.cpp:54-58 - exec	0.00	0.00

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