OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .extracted.32]

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:95-101 [...]	Coverage (incl. loops): 2.87% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 95 - 101

--------------------------------------------------------------------------------

95: #pragma omp parallel for simd collapse(2)

96:       for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

97:         for (int i = (x_min - 1 + 1); i < (x_max + 2 + 2); i++) {

98:           node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) +

99:                                          density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0));

100:           node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i - 1, j + 0) + node_flux(i, j);

101:         }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x424c40 PUSH	%RBP

0x424c41 MOV	%RSP,%RBP

0x424c44 PUSH	%R15

0x424c46 PUSH	%R14

0x424c48 PUSH	%R13

0x424c4a PUSH	%R12

0x424c4c PUSH	%RBX

0x424c4d SUB	$0x158,%RSP

0x424c54 MOV	%RCX,%R15

0x424c57 MOV	%RDX,%R13

0x424c5a MOV	0x38(%RBP),%RAX

0x424c5e MOV	0x28(%RBP),%RBX

0x424c62 MOV	0x20(%RBP),%RCX

0x424c66 MOV	0x10(%RBP),%R14

0x424c6a MOV	0x18(%RBP),%EDX

0x424c6d MOV	%RDX,-0x50(%RBP)

0x424c71 MOVL	$0,-0x38(%RBP)

0x424c78 TEST	%RAX,%RAX

0x424c7b JS	425314

0x424c81 MOV	%R8,%R12

0x424c84 MOV	%R9,-0x30(%RBP)

0x424c88 MOV	%RCX,-0x48(%RBP)

0x424c8c MOV	(%RDI),%ESI

0x424c8e MOVQ	$0,-0x68(%RBP)

0x424c96 MOV	%RAX,-0x60(%RBP)

0x424c9a MOVQ	$0x1,-0xb8(%RBP)

0x424ca5 SUB	$0x8,%RSP

0x424ca9 LEA	-0xb8(%RBP),%RAX

0x424cb0 LEA	-0x38(%RBP),%RCX

0x424cb4 LEA	-0x68(%RBP),%R8

0x424cb8 LEA	-0x60(%RBP),%R9

0x424cbc MOV	$0x4b7970,%EDI

0x424cc1 MOV	%ESI,-0x34(%RBP)

0x424cc4 MOV	$0x22,%EDX

0x424cc9 PUSH	$0x1

0x424ccb PUSH	$0x1

0x424ccd PUSH	%RAX

0x424cce CALL	4031f0 <__kmpc_for_static_init_8@plt>

0x424cd3 ADD	$0x20,%RSP

0x424cd7 MOV	-0x68(%RBP),%RCX

0x424cdb MOV	-0x60(%RBP),%RAX

0x424cdf CMP	%RAX,%RCX

0x424ce2 JA	4252f6

0x424ce8 MOV	%RAX,%RDX

0x424ceb MOV	-0x48(%RBP),%RAX

0x424cef SUB	%EAX,%EBX

0x424cf1 MOV	(%R13),%RSI

0x424cf5 MOV	0x10(%R13),%R9

0x424cf9 MOV	(%R14),%R10

0x424cfc MOV	0x10(%R14),%R11

0x424d00 MOV	(%R12),%R13

0x424d04 MOV	0x10(%R12),%R12

0x424d09 MOV	(%R15),%RDI

0x424d0c MOV	0x10(%R15),%R8

0x424d10 MOV	%R8,-0x58(%RBP)

0x424d14 MOV	-0x30(%RBP),%R14

0x424d18 MOV	(%R14),%R8

0x424d1b MOV	0x10(%R14),%R15

0x424d1f INC	%RDX

0x424d22 MOV	%RDX,-0xb0(%RBP)

0x424d29 MOV	%RDX,%R14

0x424d2c SUB	%RCX,%R14

0x424d2f MOV	$-0x2,%EDX

0x424d34 AND	%R14,%RDX

0x424d37 MOV	%RBX,-0x30(%RBP)

0x424d3b MOV	%RDI,-0xa8(%RBP)

0x424d42 MOV	%R8,-0xa0(%RBP)

0x424d49 JE	425326

0x424d4f MOV	%R14,-0x70(%RBP)

0x424d53 MOVD	%EBX,%XMM0

0x424d57 PSHUFD	$0x44,%XMM0,%XMM2

0x424d5c MOVD	-0x50(%RBP),%XMM0

0x424d61 PSHUFD	$0x50,%XMM0,%XMM0

0x424d66 MOVDQA	%XMM0,-0x170(%RBP)

0x424d6e MOVD	%EAX,%XMM0

0x424d72 PSHUFD	$0x50,%XMM0,%XMM0

0x424d77 MOVDQA	%XMM0,-0x160(%RBP)

0x424d7f MOV	%RSI,-0x88(%RBP)

0x424d86 MOVQ	%RSI,%XMM0

0x424d8b PSHUFD	$0x44,%XMM0,%XMM0

0x424d90 MOV	%R10,-0x78(%RBP)

0x424d94 MOVQ	%R10,%XMM1

0x424d99 PSHUFD	$0x44,%XMM1,%XMM3

0x424d9e MOV	%R13,-0x80(%RBP)

0x424da2 MOVQ	%R13,%XMM1

0x424da7 PSHUFD	$0x44,%XMM1,%XMM1

0x424dac MOVDQA	%XMM1,-0x140(%RBP)

0x424db4 MOVQ	%RDI,%XMM1

0x424db9 PSHUFD	$0x44,%XMM1,%XMM1

0x424dbe MOVDQA	%XMM1,-0x130(%RBP)

0x424dc6 MOVQ	%R8,%XMM1

0x424dcb PSHUFD	$0x44,%XMM1,%XMM1

0x424dd0 MOVDQA	%XMM1,-0x120(%RBP)

0x424dd8 MOVQ	%RCX,%XMM1

0x424ddd PSHUFD	$0x44,%XMM1,%XMM8

0x424de3 PADDQ	0x76644(%RIP),%XMM8

0x424dec XOR	%EDI,%EDI

0x424dee MOVQ	%XMM2,-0x98(%RBP)

0x424df6 MOVDQA	%XMM2,-0x180(%RBP)

0x424dfe PSHUFD	$-0x12,%XMM2,%XMM1

0x424e03 MOVQ	%XMM1,-0x90(%RBP)

0x424e0b MOVDQA	%XMM0,-0x150(%RBP)

0x424e13 PSRLQ	$0x20,%XMM0

0x424e18 MOVDQA	%XMM0,-0x100(%RBP)

0x424e20 MOVQ	%R9,%XMM1

0x424e25 PSHUFD	$0x44,%XMM1,%XMM0

0x424e2a MOVDQA	%XMM0,-0xf0(%RBP)

0x424e32 MOVDQA	%XMM3,-0x110(%RBP)

0x424e3a PSRLQ	$0x20,%XMM3

0x424e3f MOVDQA	%XMM3,-0xe0(%RBP)

0x424e47 MOVQ	%R11,%XMM1

0x424e4c PSHUFD	$0x44,%XMM1,%XMM0

0x424e51 MOVDQA	%XMM0,-0xd0(%RBP)

0x424e59 MOV	%R15,-0x40(%RBP)

0x424e5d NOPL	(%RAX)

(174) 0x424e60 MOVQ	%XMM8,%RAX

(174) 0x424e65 MOV	%RDX,%R15

(174) 0x424e68 XOR	%EDX,%EDX

(174) 0x424e6a DIVQ	-0x98(%RBP)

(174) 0x424e71 MOV	%RAX,%RSI

(174) 0x424e74 PSHUFD	$-0x12,%XMM8,%XMM1

(174) 0x424e7a MOVQ	%XMM1,%RAX

(174) 0x424e7f XOR	%EDX,%EDX

(174) 0x424e81 DIVQ	-0x90(%RBP)

(174) 0x424e88 MOVQ	%RSI,%XMM2

(174) 0x424e8d MOVQ	%RAX,%XMM1

(174) 0x424e92 PUNPCKLQDQ	%XMM1,%XMM2

(174) 0x424e96 PSHUFD	$-0x18,%XMM2,%XMM1

(174) 0x424e9b PADDD	-0x170(%RBP),%XMM1

(174) 0x424ea3 PMULUDQ	-0x180(%RBP),%XMM2

(174) 0x424eab MOVDQA	%XMM8,%XMM3

(174) 0x424eb0 PSUBQ	%XMM2,%XMM3

(174) 0x424eb4 PXOR	%XMM9,%XMM9

(174) 0x424eb9 MOVDQA	%XMM1,%XMM5

(174) 0x424ebd PCMPEQD	%XMM0,%XMM0

(174) 0x424ec1 PADDD	%XMM0,%XMM5

(174) 0x424ec5 PSHUFD	$-0x18,%XMM3,%XMM15

(174) 0x424ecb PXOR	%XMM10,%XMM10

(174) 0x424ed0 PCMPGTD	%XMM5,%XMM10

(174) 0x424ed5 PUNPCKLDQ	%XMM10,%XMM5

(174) 0x424eda PADDD	-0x160(%RBP),%XMM15

(174) 0x424ee3 MOVDQA	-0x150(%RBP),%XMM0

(174) 0x424eeb MOVDQA	%XMM0,%XMM4

(174) 0x424eef PMULUDQ	%XMM5,%XMM4

(174) 0x424ef3 MOVDQA	-0x100(%RBP),%XMM7

(174) 0x424efb MOVDQA	%XMM7,%XMM11

(174) 0x424f00 PCMPGTD	%XMM15,%XMM9

(174) 0x424f05 PMULUDQ	%XMM5,%XMM11

(174) 0x424f0a PXOR	%XMM6,%XMM6

(174) 0x424f0e PUNPCKLDQ	%XMM6,%XMM10

(174) 0x424f13 MOVDQA	%XMM0,%XMM3

(174) 0x424f17 MOVDQA	%XMM15,%XMM2

(174) 0x424f1c PMULUDQ	%XMM10,%XMM3

(174) 0x424f21 MOVDQA	-0x110(%RBP),%XMM13

(174) 0x424f2a MOVDQA	%XMM13,%XMM12

(174) 0x424f2f PMULUDQ	%XMM5,%XMM12

(174) 0x424f34 PUNPCKLDQ	%XMM9,%XMM2

(174) 0x424f39 MOVDQA	-0xe0(%RBP),%XMM14

(174) 0x424f42 PMULUDQ	%XMM14,%XMM5

(174) 0x424f47 PMULUDQ	%XMM13,%XMM10

(174) 0x424f4c PXOR	%XMM9,%XMM9

(174) 0x424f51 PADDQ	%XMM11,%XMM3

(174) 0x424f56 PCMPGTD	%XMM1,%XMM9

(174) 0x424f5b PUNPCKLDQ	%XMM9,%XMM1

(174) 0x424f60 PADDQ	%XMM5,%XMM10

(174) 0x424f65 PMULUDQ	%XMM1,%XMM7

(174) 0x424f69 PUNPCKLDQ	%XMM6,%XMM9

(174) 0x424f6e MOVDQA	%XMM0,%XMM11

(174) 0x424f73 PSLLQ	$0x20,%XMM3

(174) 0x424f78 PMULUDQ	%XMM9,%XMM11

(174) 0x424f7d PADDQ	%XMM7,%XMM11

(174) 0x424f82 MOVDQA	%XMM0,%XMM5

(174) 0x424f86 PSLLQ	$0x20,%XMM10

(174) 0x424f8c PMULUDQ	%XMM1,%XMM5

(174) 0x424f90 PSLLQ	$0x20,%XMM11

(174) 0x424f96 PADDQ	%XMM5,%XMM11

(174) 0x424f9b PADDQ	%XMM4,%XMM3

(174) 0x424f9f MOVDQA	%XMM13,%XMM5

(174) 0x424fa4 PMULUDQ	%XMM1,%XMM14

(174) 0x424fa9 PADDQ	%XMM12,%XMM10

(174) 0x424fae MOVDQA	%XMM13,%XMM4

(174) 0x424fb3 PMULUDQ	%XMM9,%XMM4

(174) 0x424fb8 PADDQ	%XMM14,%XMM4

(174) 0x424fbd MOVDQA	%XMM3,%XMM7

(174) 0x424fc1 PMULUDQ	%XMM1,%XMM5

(174) 0x424fc5 PSLLQ	$0x20,%XMM4

(174) 0x424fca PADDQ	%XMM5,%XMM4

(174) 0x424fce PADDQ	%XMM2,%XMM7

(174) 0x424fd2 MOVDQA	%XMM11,%XMM5

(174) 0x424fd7 PADDQ	%XMM2,%XMM5

(174) 0x424fdb PSLLQ	$0x3,%XMM5

(174) 0x424fe0 PSLLQ	$0x3,%XMM7

(174) 0x424fe5 MOVDQA	-0xf0(%RBP),%XMM6

(174) 0x424fed PADDQ	%XMM6,%XMM5

(174) 0x424ff1 MOVQ	%XMM5,%R14

(174) 0x424ff6 PSHUFD	$-0x12,%XMM5,%XMM5

(174) 0x424ffb MOVQ	%XMM5,%RSI

(174) 0x425000 MOVDQA	%XMM4,%XMM5

(174) 0x425004 PADDQ	%XMM2,%XMM5

(174) 0x425008 PSLLQ	$0x3,%XMM5

(174) 0x42500d PADDQ	%XMM6,%XMM7

(174) 0x425011 MOVDQA	-0xd0(%RBP),%XMM12

(174) 0x42501a PADDQ	%XMM12,%XMM5

(174) 0x42501f MOVQ	%XMM5,%RBX

(174) 0x425024 PSHUFD	$-0x12,%XMM5,%XMM5

(174) 0x425029 MOVQ	%XMM7,%R13

(174) 0x42502e MOV	%R12,%R10

(174) 0x425031 MOVQ	%XMM5,%R12

(174) 0x425036 MOVDQA	%XMM10,%XMM5

(174) 0x42503b PADDQ	%XMM2,%XMM5

(174) 0x42503f PSHUFD	$-0x12,%XMM7,%XMM7

(174) 0x425044 PSLLQ	$0x3,%XMM5

(174) 0x425049 PADDQ	%XMM12,%XMM5

(174) 0x42504e MOVQ	%XMM5,%RDX

(174) 0x425053 MOVQ	%XMM7,%RAX

(174) 0x425058 PADDD	0x7655f(%RIP),%XMM15

(174) 0x425061 PXOR	%XMM7,%XMM7

(174) 0x425065 PCMPGTD	%XMM15,%XMM7

(174) 0x42506a PSHUFD	$-0x12,%XMM5,%XMM0

(174) 0x42506f PUNPCKLDQ	%XMM7,%XMM15

(174) 0x425074 PADDQ	%XMM15,%XMM3

(174) 0x425079 PSLLQ	$0x3,%XMM3

(174) 0x42507e MOVSD	(%R14),%XMM13

(174) 0x425083 PADDQ	%XMM6,%XMM3

(174) 0x425087 MOVQ	%XMM3,%R14

(174) 0x42508c MOVHPD	(%RSI),%XMM13

(174) 0x425091 PSHUFD	$-0x12,%XMM3,%XMM3

(174) 0x425096 MOVQ	%XMM3,%RSI

(174) 0x42509b MOVSD	(%RBX),%XMM5

(174) 0x42509f MOVQ	%XMM0,%R8

(174) 0x4250a4 PADDQ	%XMM15,%XMM10

(174) 0x4250a9 PSLLQ	$0x3,%XMM10

(174) 0x4250af MOVHPD	(%R12),%XMM5

(174) 0x4250b5 PADDQ	%XMM12,%XMM10

(174) 0x4250ba MOVQ	%XMM10,%RBX

(174) 0x4250bf PSHUFD	$-0x12,%XMM10,%XMM0

(174) 0x4250c5 MOVSD	(%R13),%XMM3

(174) 0x4250cb MOVQ	%XMM0,%R12

(174) 0x4250d0 PADDQ	%XMM15,%XMM11

(174) 0x4250d5 PSLLQ	$0x3,%XMM11

(174) 0x4250db MOVSD	(%RDX),%XMM10

(174) 0x4250e0 PADDQ	%XMM6,%XMM11

(174) 0x4250e5 MOVQ	%XMM11,%RDX

(174) 0x4250ea MOVHPD	(%RAX),%XMM3

(174) 0x4250ee PSHUFD	$-0x12,%XMM11,%XMM0

(174) 0x4250f4 MOVQ	%XMM0,%RAX

(174) 0x4250f9 MOVHPD	(%R8),%XMM10

(174) 0x4250fe MOVSD	(%RDX),%XMM0

(174) 0x425102 MOVHPD	(%RAX),%XMM0

(174) 0x425106 MULPD	%XMM13,%XMM5

(174) 0x42510b MOVSD	(%R14),%XMM7

(174) 0x425110 PADDQ	%XMM15,%XMM4

(174) 0x425115 PSLLQ	$0x3,%XMM4

(174) 0x42511a MULPD	%XMM3,%XMM10

(174) 0x42511f PADDQ	%XMM12,%XMM4

(174) 0x425124 MOVQ	%XMM4,%RAX

(174) 0x425129 PSHUFD	$-0x12,%XMM4,%XMM3

(174) 0x42512e MOVSD	(%RBX),%XMM4

(174) 0x425132 MOVQ	%XMM3,%RDX

(174) 0x425137 MOVSD	(%RAX),%XMM3

(174) 0x42513b MOVHPD	(%RSI),%XMM7

(174) 0x42513f MOVHPD	(%RDX),%XMM3

(174) 0x425143 MOVHPD	(%R12),%XMM4

(174) 0x425149 MOV	%R10,%R12

(174) 0x42514c MULPD	%XMM7,%XMM4

(174) 0x425150 MULPD	%XMM0,%XMM3

(174) 0x425154 MOVDQA	-0x140(%RBP),%XMM7

(174) 0x42515c MOVDQA	%XMM7,%XMM0

(174) 0x425160 ADDPD	%XMM4,%XMM3

(174) 0x425164 PSRLQ	$0x20,%XMM0

(174) 0x425169 PMULUDQ	%XMM1,%XMM0

(174) 0x42516d MOVDQA	%XMM7,%XMM4

(174) 0x425171 PMULUDQ	%XMM9,%XMM4

(174) 0x425176 PADDQ	%XMM0,%XMM4

(174) 0x42517a MOVDQA	%XMM7,%XMM0

(174) 0x42517e PMULUDQ	%XMM1,%XMM0

(174) 0x425182 PSLLQ	$0x20,%XMM4

(174) 0x425187 PADDQ	%XMM2,%XMM0

(174) 0x42518b PADDQ	%XMM4,%XMM0

(174) 0x42518f MOVQ	%R10,%XMM4

(174) 0x425194 PSLLQ	$0x3,%XMM0

(174) 0x425199 PSHUFD	$0x44,%XMM4,%XMM7

(174) 0x42519e PADDQ	%XMM0,%XMM7

(174) 0x4251a2 MOVDQA	-0x130(%RBP),%XMM11

(174) 0x4251ab MOVDQA	%XMM11,%XMM0

(174) 0x4251b0 ADDPD	%XMM10,%XMM5

(174) 0x4251b5 PSRLQ	$0x20,%XMM0

(174) 0x4251ba PMULUDQ	%XMM1,%XMM0

(174) 0x4251be MOVDQA	%XMM11,%XMM4

(174) 0x4251c3 PMULUDQ	%XMM9,%XMM4

(174) 0x4251c8 PADDQ	%XMM0,%XMM4

(174) 0x4251cc MOVQ	%XMM7,%RAX

(174) 0x4251d1 PSHUFD	$-0x12,%XMM7,%XMM0

(174) 0x4251d6 ADDPD	%XMM5,%XMM3

(174) 0x4251da MOVDQA	%XMM11,%XMM5

(174) 0x4251df PMULUDQ	%XMM1,%XMM5

(174) 0x4251e3 PSLLQ	$0x20,%XMM4

(174) 0x4251e8 MOVQ	%XMM0,%RDX

(174) 0x4251ed PADDQ	%XMM5,%XMM4

(174) 0x4251f1 MOVDQA	-0x120(%RBP),%XMM7

(174) 0x4251f9 MOVDQA	%XMM7,%XMM5

(174) 0x4251fd MOVDQA	%XMM7,%XMM0

(174) 0x425201 PMULUDQ	%XMM1,%XMM5

(174) 0x425205 PSRLQ	$0x20,%XMM0

(174) 0x42520a PMULUDQ	%XMM1,%XMM0

(174) 0x42520e PADDQ	%XMM4,%XMM15

(174) 0x425213 PMULUDQ	%XMM7,%XMM9

(174) 0x425218 PADDQ	%XMM0,%XMM9

(174) 0x42521d MOVQ	-0x58(%RBP),%XMM0

(174) 0x425222 PSHUFD	$0x44,%XMM0,%XMM0

(174) 0x425227 PSLLQ	$0x3,%XMM15

(174) 0x42522d PADDQ	%XMM0,%XMM15

(174) 0x425232 PADDQ	%XMM2,%XMM4

(174) 0x425236 PSLLQ	$0x3,%XMM4

(174) 0x42523b PADDQ	%XMM0,%XMM4

(174) 0x42523f PADDQ	%XMM2,%XMM5

(174) 0x425243 MOVQ	%XMM15,%RSI

(174) 0x425248 PSHUFD	$-0x12,%XMM15,%XMM0

(174) 0x42524e MOVQ	%XMM0,%R8

(174) 0x425253 PSLLQ	$0x20,%XMM9

(174) 0x425259 PADDQ	%XMM9,%XMM5

(174) 0x42525e MOVQ	-0x40(%RBP),%XMM0

(174) 0x425263 PSLLQ	$0x3,%XMM5

(174) 0x425268 PSHUFD	$0x44,%XMM0,%XMM0

(174) 0x42526d PADDQ	%XMM5,%XMM0

(174) 0x425271 MULPD	0x761c7(%RIP),%XMM3

(174) 0x425279 MOVLPD	%XMM3,(%RAX)

(174) 0x42527d MOVHPD	%XMM3,(%RDX)

(174) 0x425281 MOVQ	%XMM4,%RAX

(174) 0x425286 PSHUFD	$-0x12,%XMM4,%XMM1

(174) 0x42528b MOVQ	%XMM1,%RDX

(174) 0x425290 MOVSD	(%RSI),%XMM1

(174) 0x425294 MOVHPD	(%R8),%XMM1

(174) 0x425299 SUBPD	%XMM1,%XMM3

(174) 0x42529d MOVSD	(%RAX),%XMM1

(174) 0x4252a1 MOVHPD	(%RDX),%XMM1

(174) 0x4252a5 ADDPD	%XMM3,%XMM1

(174) 0x4252a9 MOVQ	%XMM0,%RAX

(174) 0x4252ae PSHUFD	$-0x12,%XMM0,%XMM0

(174) 0x4252b3 MOVQ	%XMM0,%RDX

(174) 0x4252b8 MOVLPD	%XMM1,(%RAX)

(174) 0x4252bc MOVHPD	%XMM1,(%RDX)

(174) 0x4252c0 MOV	%R15,%RDX

(174) 0x4252c3 PADDQ	0x76184(%RIP),%XMM8

(174) 0x4252cc ADD	$0x2,%RDI

(174) 0x4252d0 CMP	%R15,%RDI

(174) 0x4252d3 JB	424e60

0x4252d9 MOV	-0x40(%RBP),%R15

0x4252dd CMP	%RDX,-0x70(%RBP)

0x4252e1 MOV	-0x30(%RBP),%RBX

0x4252e5 MOV	-0x88(%RBP),%R14

0x4252ec MOV	-0x80(%RBP),%R13

0x4252f0 MOV	-0x78(%RBP),%R10

0x4252f4 JNE	42532e

0x4252f6 MOV	$0x4b7990,%EDI

0x4252fb MOV	-0x34(%RBP),%ESI

0x4252fe ADD	$0x158,%RSP

0x425305 POP	%RBX

0x425306 POP	%R12

0x425308 POP	%R13

0x42530a POP	%R14

0x42530c POP	%R15

0x42530e POP	%RBP

0x42530f JMP	403050

0x425314 ADD	$0x158,%RSP

0x42531b POP	%RBX

0x42531c POP	%R12

0x42531e POP	%R13

0x425320 POP	%R14

0x425322 POP	%R15

0x425324 POP	%RBP

0x425325 RET

0x425326 MOV	%RSI,%R14

0x425329 JMP	42544d

0x42532e ADD	%RDX,%RCX

0x425331 JMP	42544d

0x425336 NOPW	%CS:(%RAX,%RAX,1)

(173) 0x425340 MOV	%RCX,%RAX

(173) 0x425343 XOR	%EDX,%EDX

(173) 0x425345 DIV	%RBX

(173) 0x425348 ADD	-0x48(%RBP),%EDX

(173) 0x42534b MOVSXD	%EDX,%RDX

(173) 0x42534e MOV	%EAX,%R8D

(173) 0x425351 MOV	-0x50(%RBP),%RSI

(173) 0x425355 ADD	%ESI,%R8D

(173) 0x425358 ADD	%ESI,%EAX

(173) 0x42535a DEC	%EAX

(173) 0x42535c MOVSXD	%EAX,%RDI

(173) 0x42535f MOV	%R14,%RSI

(173) 0x425362 IMUL	%RDI,%RSI

(173) 0x425366 IMUL	%R10,%RDI

(173) 0x42536a MOVSXD	%R8D,%RAX

(173) 0x42536d MOV	%R10,%R8

(173) 0x425370 IMUL	%RAX,%R8

(173) 0x425374 LEA	(%RDI,%RDX,1),%RBX

(173) 0x425378 DEC	%RBX

(173) 0x42537b MOVSD	(%R11,%RBX,8),%XMM0

(173) 0x425381 LEA	(%R8,%RDX,1),%RBX

(173) 0x425385 DEC	%RBX

(173) 0x425388 MOVHPD	(%R11,%RBX,8),%XMM0

(173) 0x42538e ADD	%RDX,%R8

(173) 0x425391 MOVSD	(%R11,%R8,8),%XMM1

(173) 0x425397 MOV	%R14,%R8

(173) 0x42539a ADD	%RDX,%RDI

(173) 0x42539d MOVHPD	(%R11,%RDI,8),%XMM1

(173) 0x4253a3 IMUL	%RAX,%R8

(173) 0x4253a7 LEA	(%RSI,%RDX,1),%RDI

(173) 0x4253ab DEC	%RDI

(173) 0x4253ae MOVSD	(%R9,%RDI,8),%XMM2

(173) 0x4253b4 LEA	(%R8,%RDX,1),%RDI

(173) 0x4253b8 DEC	%RDI

(173) 0x4253bb MOVHPD	(%R9,%RDI,8),%XMM2

(173) 0x4253c1 ADD	%RDX,%RSI

(173) 0x4253c4 ADD	%RDX,%R8

(173) 0x4253c7 MULPD	%XMM0,%XMM2

(173) 0x4253cb MOVSD	(%R9,%R8,8),%XMM0

(173) 0x4253d1 MOVHPD	(%R9,%RSI,8),%XMM0

(173) 0x4253d7 MULPD	%XMM1,%XMM0

(173) 0x4253db ADDPD	%XMM2,%XMM0

(173) 0x4253df MOVAPD	%XMM0,%XMM1

(173) 0x4253e3 UNPCKHPD	%XMM0,%XMM1

(173) 0x4253e7 ADDSD	%XMM0,%XMM1

(173) 0x4253eb MULSD	0x7602d(%RIP),%XMM1

(173) 0x4253f3 MOV	%R13,%RSI

(173) 0x4253f6 IMUL	%RAX,%RSI

(173) 0x4253fa ADD	%RDX,%RSI

(173) 0x4253fd MOVSD	%XMM1,(%R12,%RSI,8)

(173) 0x425403 MOV	-0xa8(%RBP),%RSI

(173) 0x42540a IMUL	%RAX,%RSI

(173) 0x42540e LEA	(%RSI,%RDX,1),%RDI

(173) 0x425412 DEC	%RDI

(173) 0x425415 MOV	-0x58(%RBP),%R8

(173) 0x425419 SUBSD	(%R8,%RDI,8),%XMM1

(173) 0x42541f ADD	%RDX,%RSI

(173) 0x425422 ADDSD	(%R8,%RSI,8),%XMM1

(173) 0x425428 IMUL	-0xa0(%RBP),%RAX

(173) 0x425430 ADD	%RDX,%RAX

(173) 0x425433 MOVSD	%XMM1,(%R15,%RAX,8)

(173) 0x425439 INC	%RCX

(173) 0x42543c CMP	%RCX,-0xb0(%RBP)

(173) 0x425443 MOV	-0x30(%RBP),%RBX

(173) 0x425447 JE	4252f6

(173) 0x42544d MOV	%RCX,%RAX

(173) 0x425450 SHR	$0x20,%RAX

(173) 0x425454 JNE	425340

(173) 0x42545a MOV	%ECX,%EAX

(173) 0x42545c XOR	%EDX,%EDX

(173) 0x42545e DIV	%EBX

(173) 0x425460 JMP	425348

0x425465 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:95-101
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95-101
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.50 to 11.00 cycles (2.23x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 24.50 to 2.94 cycles (8.34x speedup).

Details

34% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

7% of SSE/AVX loads are used in vector version.
37% of SSE/AVX stores are used in vector version.
14% of SSE/AVX addition or subtraction instructions are used in vector version.
51% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 224 bytes. The binary function is storing 344 bytes.

General properties

nb instructions	146
nb uops	147
loop length	658
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	36

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	24.50 cycles
front end	24.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.30	11.00	14.00	14.00	21.00	11.00	7.30	21.00	21.00	21.00	7.40	14.00
cycles	7.30	11.00	14.00	14.00	21.00	11.00	7.30	21.00	21.00	21.00	7.40	14.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	24.50
Dispatch	21.00
Overall L1	24.50

Vectorization ratios

all	34%
load	7%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	51%

Vector efficiency ratios

all	16%
load	12%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.50 cycles. At this rate:

4% of peak load performance is reached (9.14 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (14.04 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 24.50 to 21.00 cycles (1.17x speedup).

ASM code

In the binary file, the address of the function is: 424c40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x158,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 425314 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.32+0x6d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xb8(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x68(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x60(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b7970,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x68(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 4252f6 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.32+0x6b6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EAX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%R13),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R13),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R14),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R12),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R12),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R15),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R15),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R8,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x30(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RCX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $-0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %R14,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RBX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 425326 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.32+0x6e6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %EBX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVD -0x50(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x170(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVD %EAX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x160(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %RSI,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %RSI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOV %R10,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %R10,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOV %R13,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %R13,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM1,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RDI,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM1,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R8,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM1,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RCX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x76644(%RIP),%XMM8	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ %XMM2,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM2,-0x180(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM0,-0x150(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSRLQ $0x20,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM0,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R9,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM3,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSRLQ $0x20,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM3,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R11,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %R15,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x40(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDX,-0x70(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x88(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x80(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x78(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JNE 42532e <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.32+0x6ee>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b7990,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x158,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0x158,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 42544d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.32+0x80d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 42544d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.32+0x80d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:95-101
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95-101
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

34% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

7% of SSE/AVX loads are used in vector version.
37% of SSE/AVX stores are used in vector version.
14% of SSE/AVX addition or subtraction instructions are used in vector version.
51% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 224 bytes. The binary function is storing 344 bytes.

General properties

nb instructions	146
nb uops	147
loop length	658
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	36

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	24.50 cycles
front end	24.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.30	11.00	14.00	14.00	21.00	11.00	7.30	21.00	21.00	21.00	7.40	14.00
cycles	7.30	11.00	14.00	14.00	21.00	11.00	7.30	21.00	21.00	21.00	7.40	14.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	24.50
Dispatch	21.00
Overall L1	24.50

Vectorization ratios

all	34%
load	7%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	51%

Vector efficiency ratios

all	16%
load	12%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.50 cycles. At this rate:

4% of peak load performance is reached (9.14 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (14.04 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 424c40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x158,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 425314 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.32+0x6d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xb8(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x68(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x60(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b7970,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x68(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 4252f6 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.32+0x6b6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EAX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%R13),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R13),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R14),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R12),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R12),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R15),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R15),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R8,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x30(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RCX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $-0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %R14,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RBX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 425326 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.32+0x6e6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %EBX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVD -0x50(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x170(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVD %EAX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x160(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %RSI,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %RSI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOV %R10,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %R10,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOV %R13,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %R13,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM1,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RDI,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM1,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R8,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM1,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RCX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x76644(%RIP),%XMM8	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ %XMM2,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM2,-0x180(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM0,-0x150(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSRLQ $0x20,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM0,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R9,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM3,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSRLQ $0x20,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM3,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R11,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %R15,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x40(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDX,-0x70(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x88(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x80(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x78(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JNE 42532e <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.32+0x6ee>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b7990,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x158,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0x158,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 42544d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.32+0x80d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 42544d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.32+0x80d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.87	1.14
○Loop 174 - advec_mom.cpp:96-101 - exec	2.87	1.13
○Loop 173 - advec_mom.cpp:96-101 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code