OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .extracted.27]

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:108-139 [...]	Coverage (incl. loops): 6.16% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 108 - 139

--------------------------------------------------------------------------------

108: #pragma omp parallel for simd collapse(2)

109:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

110:       for (int i = (x_min - 1 + 1); i < (x_max + 1 + 2); i++)

111:         ({

112:           int upwind, donor, downwind, dif;

113:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

114:           if (node_flux(i, j) < 0.0) {

115:             upwind = i + 2;

116:             donor = i + 1;

117:             downwind = i;

118:             dif = donor;

119:           } else {

120:             upwind = i - 1;

121:             donor = i;

122:             downwind = i + 1;

123:             dif = upwind;

124:           }

125:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(donor, j));

126:           width = celldx[i];

127:           vdiffuw = vel1(donor, j) - vel1(upwind, j);

128:           vdiffdw = vel1(downwind, j) - vel1(donor, j);

129:           limiter = 0.0;

130:           if (vdiffuw * vdiffdw > 0.0) {

131:             auw = std::fabs(vdiffuw);

132:             adw = std::fabs(vdiffdw);

133:             wind = 1.0;

134:             if (vdiffdw <= 0.0) wind = -1.0;

135:             limiter =

136:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldx[dif]) / 6.0, auw), adw);

137:           }

138:           advec_vel_s = vel1(donor, j) + (1.0 - sigma) * limiter;

139:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x424330 PUSH	%RBP

0x424331 MOV	%RSP,%RBP

0x424334 PUSH	%R15

0x424336 PUSH	%R14

0x424338 PUSH	%R13

0x42433a PUSH	%R12

0x42433c PUSH	%RBX

0x42433d SUB	$0x108,%RSP

0x424344 MOV	%RCX,%R13

0x424347 MOV	%RDX,%R15

0x42434a MOV	0x38(%RBP),%RAX

0x42434e MOV	0x28(%RBP),%R14

0x424352 MOV	0x20(%RBP),%RBX

0x424356 MOV	0x18(%RBP),%RDX

0x42435a MOV	0x10(%RBP),%RCX

0x42435e MOV	%RCX,-0x58(%RBP)

0x424362 MOVL	$0,-0x38(%RBP)

0x424369 TEST	%RAX,%RAX

0x42436c JS	4249e3

0x424372 MOV	%R8,%R12

0x424375 MOV	%R9,-0x30(%RBP)

0x424379 MOV	(%RDI),%ESI

0x42437b MOVQ	$0,-0x68(%RBP)

0x424383 MOV	%RAX,-0x60(%RBP)

0x424387 MOVQ	$0x1,-0x90(%RBP)

0x424392 SUB	$0x8,%RSP

0x424396 LEA	-0x90(%RBP),%RAX

0x42439d LEA	-0x38(%RBP),%RCX

0x4243a1 LEA	-0x68(%RBP),%R8

0x4243a5 LEA	-0x60(%RBP),%R9

0x4243a9 MOV	$0x4b7910,%EDI

0x4243ae MOV	%RDX,-0x40(%RBP)

0x4243b2 MOV	%ESI,-0x34(%RBP)

0x4243b5 MOV	$0x22,%EDX

0x4243ba PUSH	$0x1

0x4243bc PUSH	$0x1

0x4243be PUSH	%RAX

0x4243bf CALL	4031f0 <__kmpc_for_static_init_8@plt>

0x4243c4 MOV	-0x40(%RBP),%RSI

0x4243c8 ADD	$0x20,%RSP

0x4243cc MOV	-0x68(%RBP),%RCX

0x4243d0 MOV	-0x60(%RBP),%RDX

0x4243d4 CMP	%RDX,%RCX

0x4243d7 JA	4249ff

0x4243dd MOV	%R14,%R11

0x4243e0 MOV	%RDX,%RAX

0x4243e3 SUB	%EBX,%R11D

0x4243e6 MOV	(%R13),%RDX

0x4243ea MOV	0x10(%R13),%R9

0x4243ee MOV	(%R12),%RDI

0x4243f2 MOV	0x10(%R12),%R10

0x4243f7 MOV	(%R15),%R8

0x4243fa MOV	0x10(%R15),%R15

0x4243fe MOV	-0x30(%RBP),%R14

0x424402 MOV	(%R14),%R12

0x424405 MOV	0x10(%R14),%R14

0x424409 INC	%RAX

0x42440c MOV	%RAX,-0x30(%RBP)

0x424410 SUB	%RCX,%RAX

0x424413 MOV	$-0x2,%R13D

0x424419 AND	%RAX,%R13

0x42441c MOV	%R9,-0x50(%RBP)

0x424420 MOV	%RDI,-0x48(%RBP)

0x424424 MOV	%R8,-0x80(%RBP)

0x424428 MOV	%R12,-0x78(%RBP)

0x42442c MOV	%RDX,-0x88(%RBP)

0x424433 JE	424a20

0x424439 MOV	%RAX,-0x70(%RBP)

0x42443d MOVD	%R11D,%XMM0

0x424442 PSHUFD	$0x44,%XMM0,%XMM1

0x424447 MOVQ	%RSI,%XMM0

0x42444c PSHUFD	$0x44,%XMM0,%XMM0

0x424451 MOVDQA	%XMM0,-0x120(%RBP)

0x424459 MOVD	%EBX,%XMM0

0x42445d PSHUFD	$0x50,%XMM0,%XMM0

0x424462 MOVDQA	%XMM0,-0x110(%RBP)

0x42446a MOVQ	%RDX,%XMM0

0x42446f PSHUFD	$0x44,%XMM0,%XMM2

0x424474 MOVQ	%RDI,%XMM0

0x424479 PSHUFD	$0x44,%XMM0,%XMM3

0x42447e MOVQ	%R8,%XMM0

0x424483 PSHUFD	$0x44,%XMM0,%XMM0

0x424488 MOVDQA	%XMM0,-0xe0(%RBP)

0x424490 MOVQ	%R12,%XMM0

0x424495 PSHUFD	$0x44,%XMM0,%XMM0

0x42449a MOVDQA	%XMM0,-0xd0(%RBP)

0x4244a2 MOVQ	%RCX,%XMM0

0x4244a7 PSHUFD	$0x44,%XMM0,%XMM7

0x4244ac PADDQ	0x76f7c(%RIP),%XMM7

0x4244b4 XOR	%R8D,%R8D

0x4244b7 MOVQ	%XMM1,%R12

0x4244bc MOVDQA	%XMM1,-0x130(%RBP)

0x4244c4 PSHUFD	$-0x12,%XMM1,%XMM0

0x4244c9 MOVQ	%XMM0,%RDI

0x4244ce XORPD	%XMM4,%XMM4

0x4244d2 MOVDQA	%XMM2,-0x100(%RBP)

0x4244da PSRLQ	$0x20,%XMM2

0x4244df MOVDQA	%XMM2,-0xc0(%RBP)

0x4244e7 MOVQ	%R9,%XMM0

0x4244ec PSHUFD	$0x44,%XMM0,%XMM0

0x4244f1 MOVDQA	%XMM0,-0xb0(%RBP)

0x4244f9 MOVDQA	%XMM3,-0xf0(%RBP)

0x424501 PSRLQ	$0x20,%XMM3

0x424506 MOVDQA	%XMM3,-0xa0(%RBP)

0x42450e JMP	424645

0x424513 NOPW	%CS:(%RAX,%RAX,1)

(172) 0x424520 DIVPD	%XMM1,%XMM9

(172) 0x424525 MOVAPD	%XMM14,%XMM1

(172) 0x42452a ANDPD	0x765bd(%RIP),%XMM14

(172) 0x424533 MOVAPD	0x770b5(%RIP),%XMM4

(172) 0x42453b SUBPD	%XMM0,%XMM4

(172) 0x42453f MULPD	%XMM14,%XMM4

(172) 0x424544 DIVPD	%XMM11,%XMM4

(172) 0x424549 ADDPD	%XMM9,%XMM4

(172) 0x42454e MULPD	%XMM4,%XMM3

(172) 0x424552 MOVAPD	%XMM2,%XMM4

(172) 0x424556 MINPD	%XMM3,%XMM4

(172) 0x42455a CMPPD	$0x3,%XMM3,%XMM3

(172) 0x42455f ANDPD	%XMM3,%XMM2

(172) 0x424563 ANDNPD	%XMM4,%XMM3

(172) 0x424567 ORPD	%XMM2,%XMM3

(172) 0x42456b MOVAPD	%XMM14,%XMM2

(172) 0x424570 MINPD	%XMM3,%XMM2

(172) 0x424574 CMPPD	$0x3,%XMM3,%XMM3

(172) 0x424579 ANDPD	%XMM3,%XMM14

(172) 0x42457e ANDNPD	%XMM2,%XMM3

(172) 0x424582 XORPD	%XMM4,%XMM4

(172) 0x424586 CMPPD	$0x6,%XMM4,%XMM1

(172) 0x42458b ORPD	%XMM14,%XMM3

(172) 0x424590 MOVAPD	%XMM3,%XMM2

(172) 0x424594 XORPD	0x77074(%RIP),%XMM2

(172) 0x42459c ANDPD	%XMM1,%XMM3

(172) 0x4245a0 ANDNPD	%XMM2,%XMM1

(172) 0x4245a4 ORPD	%XMM3,%XMM1

(172) 0x4245a8 ANDPD	%XMM1,%XMM10

(172) 0x4245ad MOVAPD	0x7702b(%RIP),%XMM1

(172) 0x4245b5 SUBPD	%XMM0,%XMM1

(172) 0x4245b9 MULPD	%XMM10,%XMM1

(172) 0x4245be ADDPD	%XMM13,%XMM1

(172) 0x4245c3 MULPD	%XMM6,%XMM1

(172) 0x4245c7 MOVDQA	-0xd0(%RBP),%XMM3

(172) 0x4245cf MOVDQA	%XMM3,%XMM0

(172) 0x4245d3 PSRLQ	$0x20,%XMM0

(172) 0x4245d8 PMULUDQ	%XMM15,%XMM0

(172) 0x4245dd MOVDQA	%XMM3,%XMM2

(172) 0x4245e1 PMULUDQ	%XMM15,%XMM2

(172) 0x4245e6 PSRLQ	$0x20,%XMM15

(172) 0x4245ec PMULUDQ	%XMM3,%XMM15

(172) 0x4245f1 PADDQ	%XMM0,%XMM15

(172) 0x4245f6 PADDQ	%XMM12,%XMM2

(172) 0x4245fb PSLLQ	$0x20,%XMM15

(172) 0x424601 PADDQ	%XMM15,%XMM2

(172) 0x424606 PSLLQ	$0x3,%XMM2

(172) 0x42460b MOVQ	%R14,%XMM0

(172) 0x424610 PSHUFD	$0x44,%XMM0,%XMM0

(172) 0x424615 PADDQ	%XMM2,%XMM0

(172) 0x424619 MOVQ	%XMM0,%RAX

(172) 0x42461e PSHUFD	$-0x12,%XMM0,%XMM0

(172) 0x424623 MOVQ	%XMM0,%RDX

(172) 0x424628 MOVLPD	%XMM1,(%RAX)

(172) 0x42462c MOVHPD	%XMM1,(%RDX)

(172) 0x424630 PADDQ	0x76e18(%RIP),%XMM7

(172) 0x424638 ADD	$0x2,%R8

(172) 0x42463c CMP	%R13,%R8

(172) 0x42463f JAE	4249f5

(172) 0x424645 MOV	%R11,%RSI

(172) 0x424648 MOVQ	%XMM7,%RAX

(172) 0x42464d XOR	%EDX,%EDX

(172) 0x42464f DIV	%R12

(172) 0x424652 MOVQ	%RAX,%XMM0

(172) 0x424657 PSHUFD	$-0x12,%XMM7,%XMM1

(172) 0x42465c MOVQ	%XMM1,%RAX

(172) 0x424661 XOR	%EDX,%EDX

(172) 0x424663 DIV	%RDI

(172) 0x424666 MOVQ	%RAX,%XMM1

(172) 0x42466b PUNPCKLQDQ	%XMM1,%XMM0

(172) 0x42466f MOVDQA	%XMM0,%XMM11

(172) 0x424674 PADDQ	-0x120(%RBP),%XMM11

(172) 0x42467d PMULUDQ	-0x130(%RBP),%XMM0

(172) 0x424685 MOVDQA	%XMM7,%XMM1

(172) 0x424689 PSUBQ	%XMM0,%XMM1

(172) 0x42468d PSHUFD	$-0x18,%XMM1,%XMM2

(172) 0x424692 PADDD	-0x110(%RBP),%XMM2

(172) 0x42469a PXOR	%XMM0,%XMM0

(172) 0x42469e PCMPGTD	%XMM2,%XMM0

(172) 0x4246a2 MOVDQA	%XMM2,%XMM12

(172) 0x4246a7 PUNPCKLDQ	%XMM0,%XMM12

(172) 0x4246ac PSHUFD	$-0x18,%XMM11,%XMM15

(172) 0x4246b2 PSLLQ	$0x20,%XMM11

(172) 0x4246b8 PSRAD	$0x1f,%XMM11

(172) 0x4246be PSHUFD	$-0x13,%XMM11,%XMM0

(172) 0x4246c4 PUNPCKLDQ	%XMM0,%XMM15

(172) 0x4246c9 MOVDQA	-0x100(%RBP),%XMM3

(172) 0x4246d1 MOVDQA	%XMM3,%XMM0

(172) 0x4246d5 PMULUDQ	%XMM15,%XMM0

(172) 0x4246da MOVDQA	-0xc0(%RBP),%XMM1

(172) 0x4246e2 PMULUDQ	%XMM15,%XMM1

(172) 0x4246e7 PSRLQ	$0x20,%XMM11

(172) 0x4246ed PMULUDQ	%XMM11,%XMM3

(172) 0x4246f2 PADDQ	%XMM1,%XMM3

(172) 0x4246f6 PSLLQ	$0x20,%XMM3

(172) 0x4246fb PADDQ	%XMM12,%XMM0

(172) 0x424700 PADDQ	%XMM3,%XMM0

(172) 0x424704 PSLLQ	$0x3,%XMM0

(172) 0x424709 PADDQ	-0xb0(%RBP),%XMM0

(172) 0x424711 MOVQ	%XMM0,%RAX

(172) 0x424716 PSHUFD	$-0x12,%XMM0,%XMM0

(172) 0x42471b MOVQ	%XMM0,%RDX

(172) 0x424720 MOVSD	(%RAX),%XMM6

(172) 0x424724 MOVHPD	(%RDX),%XMM6

(172) 0x424728 MOVAPD	%XMM6,%XMM8

(172) 0x42472d CMPPD	$0x1,%XMM4,%XMM8

(172) 0x424733 MOVDQA	%XMM2,%XMM3

(172) 0x424737 PCMPEQD	%XMM0,%XMM0

(172) 0x42473b PSUBD	%XMM0,%XMM3

(172) 0x42473f MOVDQA	%XMM2,%XMM9

(172) 0x424744 PADDD	%XMM0,%XMM9

(172) 0x424749 XORPD	%XMM4,%XMM4

(172) 0x42474d PCMPGTD	%XMM3,%XMM4

(172) 0x424751 MOVDQA	%XMM3,%XMM0

(172) 0x424755 PUNPCKLDQ	%XMM4,%XMM0

(172) 0x424759 PADDD	0x78d6f(%RIP),%XMM2

(172) 0x424761 MOVAPD	%XMM8,%XMM5

(172) 0x424766 ANDNPD	%XMM0,%XMM5

(172) 0x42476a MOVDQA	%XMM12,%XMM4

(172) 0x42476f PAND	%XMM8,%XMM4

(172) 0x424774 POR	%XMM5,%XMM4

(172) 0x424778 MOVDQA	%XMM8,%XMM5

(172) 0x42477d PANDN	%XMM12,%XMM5

(172) 0x424782 PAND	%XMM8,%XMM0

(172) 0x424787 POR	%XMM5,%XMM0

(172) 0x42478b MOVDQA	-0xe0(%RBP),%XMM10

(172) 0x424794 MOVDQA	%XMM10,%XMM5

(172) 0x424799 PMULUDQ	%XMM15,%XMM5

(172) 0x42479e MOVDQA	%XMM10,%XMM13

(172) 0x4247a3 PSRLQ	$0x20,%XMM13

(172) 0x4247a9 PMULUDQ	%XMM15,%XMM13

(172) 0x4247ae PMULUDQ	%XMM11,%XMM10

(172) 0x4247b3 PADDQ	%XMM13,%XMM10

(172) 0x4247b8 PSLLQ	$0x20,%XMM10

(172) 0x4247be PADDQ	%XMM5,%XMM10

(172) 0x4247c3 MOVDQA	%XMM10,%XMM13

(172) 0x4247c8 PADDQ	%XMM0,%XMM13

(172) 0x4247cd PSLLQ	$0x3,%XMM13

(172) 0x4247d3 MOVQ	%R15,%XMM5

(172) 0x4247d8 PSHUFD	$0x44,%XMM5,%XMM5

(172) 0x4247dd PADDQ	%XMM5,%XMM13

(172) 0x4247e2 MOVQ	%XMM13,%RAX

(172) 0x4247e7 PSHUFD	$-0x12,%XMM13,%XMM13

(172) 0x4247ed MOVQ	%XMM13,%RDX

(172) 0x4247f2 PXOR	%XMM13,%XMM13

(172) 0x4247f7 PCMPGTD	%XMM9,%XMM13

(172) 0x4247fc MOVDQA	%XMM9,%XMM14

(172) 0x424801 PUNPCKLDQ	%XMM13,%XMM14

(172) 0x424806 MOVDQA	%XMM8,%XMM1

(172) 0x42480b PANDN	%XMM14,%XMM1

(172) 0x424810 PXOR	%XMM13,%XMM13

(172) 0x424815 PCMPGTD	%XMM2,%XMM13

(172) 0x42481a PUNPCKLDQ	%XMM13,%XMM2

(172) 0x42481f MOVSD	(%RAX),%XMM13

(172) 0x424824 MOVHPD	(%RDX),%XMM13

(172) 0x424829 PAND	%XMM8,%XMM2

(172) 0x42482e POR	%XMM1,%XMM2

(172) 0x424832 PADDQ	%XMM10,%XMM2

(172) 0x424837 PSLLQ	$0x3,%XMM2

(172) 0x42483c PADDQ	%XMM5,%XMM2

(172) 0x424840 MOVQ	%XMM2,%RAX

(172) 0x424845 PSHUFD	$-0x12,%XMM2,%XMM1

(172) 0x42484a MOVQ	%XMM1,%RDX

(172) 0x42484f MOVSD	(%RAX),%XMM1

(172) 0x424853 MOVHPD	(%RDX),%XMM1

(172) 0x424857 PADDQ	%XMM4,%XMM10

(172) 0x42485c MOVAPD	%XMM13,%XMM2

(172) 0x424861 PSLLQ	$0x3,%XMM10

(172) 0x424867 PADDQ	%XMM5,%XMM10

(172) 0x42486c MOVQ	%XMM10,%RAX

(172) 0x424871 PSHUFD	$-0x12,%XMM10,%XMM4

(172) 0x424877 MOVQ	%XMM4,%RDX

(172) 0x42487c MOVSD	(%RAX),%XMM14

(172) 0x424881 MOVHPD	(%RDX),%XMM14

(172) 0x424886 SUBPD	%XMM1,%XMM2

(172) 0x42488a SUBPD	%XMM13,%XMM14

(172) 0x42488f MOVAPD	%XMM14,%XMM1

(172) 0x424894 MULPD	%XMM2,%XMM1

(172) 0x424898 PXOR	%XMM10,%XMM10

(172) 0x42489d CMPPD	$0x1,%XMM1,%XMM10

(172) 0x4248a3 MOVMSKPD	%XMM10,%EAX

(172) 0x4248a8 TEST	%EAX,%EAX

(172) 0x4248aa JE	4248b4

(172) 0x4248ac MOV	-0x58(%RBP),%RDX

(172) 0x4248b0 MOV	0x8(%RDX),%RDX

(172) 0x4248b4 MOVDQA	-0xf0(%RBP),%XMM5

(172) 0x4248bc MOVDQA	%XMM5,%XMM1

(172) 0x4248c0 PMULUDQ	%XMM15,%XMM1

(172) 0x4248c5 MOVDQA	-0xa0(%RBP),%XMM4

(172) 0x4248cd PMULUDQ	%XMM15,%XMM4

(172) 0x4248d2 PMULUDQ	%XMM5,%XMM11

(172) 0x4248d7 PADDQ	%XMM4,%XMM11

(172) 0x4248dc PSLLQ	$0x20,%XMM11

(172) 0x4248e2 PADDQ	%XMM1,%XMM11

(172) 0x4248e7 PADDQ	%XMM0,%XMM11

(172) 0x4248ec PSLLQ	$0x3,%XMM11

(172) 0x4248f2 MOVQ	%R10,%XMM0

(172) 0x4248f7 PSHUFD	$0x44,%XMM0,%XMM0

(172) 0x4248fc PADDQ	%XMM11,%XMM0

(172) 0x424901 MOVQ	%XMM0,%R9

(172) 0x424906 PSHUFD	$-0x12,%XMM0,%XMM0

(172) 0x42490b MOVQ	%XMM0,%R11

(172) 0x424910 MOVSD	(%R9),%XMM5

(172) 0x424915 MOVHPD	(%R11),%XMM5

(172) 0x42491a MOVDQA	%XMM12,%XMM0

(172) 0x42491f PSLLQ	$0x3,%XMM0

(172) 0x424924 MOVQ	%RDX,%XMM1

(172) 0x424929 PSHUFD	$0x44,%XMM1,%XMM4

(172) 0x42492e PADDQ	%XMM4,%XMM0

(172) 0x424932 TEST	$0x1,%AL

(172) 0x424934 JE	424940

(172) 0x424936 MOVQ	%XMM0,%RDX

(172) 0x42493b MOVSD	(%RDX),%XMM11

(172) 0x424940 TEST	$0x2,%AL

(172) 0x424942 JE	424953

(172) 0x424944 PSHUFD	$-0x12,%XMM0,%XMM0

(172) 0x424949 MOVQ	%XMM0,%RDX

(172) 0x42494e MOVHPD	(%RDX),%XMM11

(172) 0x424953 MOV	%RSI,%R11

(172) 0x424956 SHUFPS	$-0x18,%XMM8,%XMM8

(172) 0x42495b PAND	%XMM8,%XMM3

(172) 0x424960 PANDN	%XMM9,%XMM8

(172) 0x424965 POR	%XMM3,%XMM8

(172) 0x42496a MOVAPD	%XMM6,%XMM0

(172) 0x42496e ANDPD	0x7617a(%RIP),%XMM0

(172) 0x424976 DIVPD	%XMM5,%XMM0

(172) 0x42497a MOVAPD	%XMM11,%XMM3

(172) 0x42497f MULPD	0x76c79(%RIP),%XMM3

(172) 0x424987 MOVAPD	%XMM0,%XMM9

(172) 0x42498c ADDPD	0x76c4b(%RIP),%XMM9

(172) 0x424995 PXOR	%XMM1,%XMM1

(172) 0x424999 PCMPGTD	%XMM8,%XMM1

(172) 0x42499e PUNPCKLDQ	%XMM1,%XMM8

(172) 0x4249a3 PSLLQ	$0x3,%XMM8

(172) 0x4249a9 PADDQ	%XMM8,%XMM4

(172) 0x4249ae TEST	$0x1,%AL

(172) 0x4249b0 JE	4249bb

(172) 0x4249b2 MOVQ	%XMM4,%RDX

(172) 0x4249b7 MOVSD	(%RDX),%XMM1

(172) 0x4249bb ANDPD	0x7612d(%RIP),%XMM2

(172) 0x4249c3 MULPD	%XMM2,%XMM9

(172) 0x4249c8 TEST	$0x2,%AL

(172) 0x4249ca JE	424520

(172) 0x4249d0 PSHUFD	$-0x12,%XMM4,%XMM4

(172) 0x4249d5 MOVQ	%XMM4,%RAX

(172) 0x4249da MOVHPD	(%RAX),%XMM1

(172) 0x4249de JMP	424520

0x4249e3 ADD	$0x108,%RSP

0x4249ea POP	%RBX

0x4249eb POP	%R12

0x4249ed POP	%R13

0x4249ef POP	%R14

0x4249f1 POP	%R15

0x4249f3 POP	%RBP

0x4249f4 RET

0x4249f5 CMP	%R13,-0x70(%RBP)

0x4249f9 MOV	-0x40(%RBP),%RSI

0x4249fd JNE	424a1d

0x4249ff MOV	$0x4b7930,%EDI

0x424a04 MOV	-0x34(%RBP),%ESI

0x424a07 ADD	$0x108,%RSP

0x424a0e POP	%RBX

0x424a0f POP	%R12

0x424a11 POP	%R13

0x424a13 POP	%R14

0x424a15 POP	%R15

0x424a17 POP	%RBP

0x424a18 JMP	403050

0x424a1d ADD	%R13,%RCX

0x424a20 PXOR	%XMM0,%XMM0

0x424a24 MOVAPD	0x760c4(%RIP),%XMM1

0x424a2c MOVSD	0x76bec(%RIP),%XMM2

0x424a34 MOVSD	0x7605c(%RIP),%XMM3

0x424a3c MOVSD	0x76be4(%RIP),%XMM4

0x424a44 MOVAPD	0x76bc4(%RIP),%XMM5

0x424a4c JMP	424a84

0x424a4e XCHG	%AX,%AX

(171) 0x424a50 MOVAPD	%XMM3,%XMM9

(171) 0x424a55 SUBSD	%XMM7,%XMM9

(171) 0x424a5a MULSD	%XMM11,%XMM9

(171) 0x424a5f ADDSD	%XMM8,%XMM9

(171) 0x424a64 MULSD	%XMM6,%XMM9

(171) 0x424a69 IMUL	-0x78(%RBP),%RAX

(171) 0x424a6e ADD	%RDI,%RAX

(171) 0x424a71 MOVSD	%XMM9,(%R14,%RAX,8)

(171) 0x424a77 INC	%RCX

(171) 0x424a7a CMP	%RCX,-0x30(%RBP)

(171) 0x424a7e JE	4249ff

(171) 0x424a84 MOV	%RCX,%RAX

(171) 0x424a87 SHR	$0x20,%RAX

(171) 0x424a8b JE	424aa0

(171) 0x424a8d MOV	%RCX,%RAX

(171) 0x424a90 XOR	%EDX,%EDX

(171) 0x424a92 DIV	%R11

(171) 0x424a95 JMP	424aa7

0x424a97 NOPW	(%RAX,%RAX,1)

(171) 0x424aa0 MOV	%ECX,%EAX

(171) 0x424aa2 XOR	%EDX,%EDX

(171) 0x424aa4 DIV	%R11D

(171) 0x424aa7 MOV	-0x50(%RBP),%R12

(171) 0x424aab ADD	%ESI,%EAX

(171) 0x424aad LEA	(%RDX,%RBX,1),%R8D

(171) 0x424ab1 MOVSXD	%R8D,%RDI

(171) 0x424ab4 CLTQ

(171) 0x424ab6 MOV	-0x88(%RBP),%R9

(171) 0x424abd IMUL	%RAX,%R9

(171) 0x424ac1 ADD	%RDI,%R9

(171) 0x424ac4 MOVSD	(%R12,%R9,8),%XMM6

(171) 0x424aca UCOMISD	%XMM6,%XMM0

(171) 0x424ace LEA	0x1(%RDX,%RBX,1),%EDX

(171) 0x424ad2 MOVSXD	%EDX,%R12

(171) 0x424ad5 JBE	424ae0

(171) 0x424ad7 ADD	$0x2,%R8D

(171) 0x424adb MOV	%RDI,%R13

(171) 0x424ade JMP	424aec

(171) 0x424ae0 DEC	%R8D

(171) 0x424ae3 MOV	%R12,%R13

(171) 0x424ae6 MOV	%RDI,%R12

(171) 0x424ae9 MOV	%R8D,%EDX

(171) 0x424aec MOV	-0x48(%RBP),%R9

(171) 0x424af0 MOVAPD	%XMM6,%XMM7

(171) 0x424af4 ANDPD	%XMM1,%XMM7

(171) 0x424af8 IMUL	%RAX,%R9

(171) 0x424afc ADD	%R12,%R9

(171) 0x424aff DIVSD	(%R10,%R9,8),%XMM7

(171) 0x424b05 MOV	-0x80(%RBP),%R9

(171) 0x424b09 IMUL	%RAX,%R9

(171) 0x424b0d ADD	%R9,%R12

(171) 0x424b10 MOVSD	(%R15,%R12,8),%XMM8

(171) 0x424b16 MOVSXD	%R8D,%R8

(171) 0x424b19 ADD	%R9,%R8

(171) 0x424b1c ADD	%R13,%R9

(171) 0x424b1f MOVAPD	%XMM8,%XMM10

(171) 0x424b24 MOVHPD	(%R15,%R9,8),%XMM10

(171) 0x424b2a MOVSD	(%R15,%R8,8),%XMM9

(171) 0x424b30 UNPCKLPD	%XMM8,%XMM9

(171) 0x424b35 SUBPD	%XMM9,%XMM10

(171) 0x424b3a MOVAPD	%XMM10,%XMM9

(171) 0x424b3f UNPCKHPD	%XMM10,%XMM9

(171) 0x424b44 MOVAPD	%XMM9,%XMM12

(171) 0x424b49 MULSD	%XMM10,%XMM12

(171) 0x424b4e XORPD	%XMM11,%XMM11

(171) 0x424b53 UCOMISD	%XMM11,%XMM12

(171) 0x424b58 JBE	424a50

(171) 0x424b5e MOV	-0x58(%RBP),%R8

(171) 0x424b62 MOV	0x8(%R8),%R8

(171) 0x424b66 MOVSD	(%R8,%RDI,8),%XMM11

(171) 0x424b6c ANDPD	%XMM1,%XMM10

(171) 0x424b71 MOVAPD	%XMM2,%XMM12

(171) 0x424b76 SUBSD	%XMM7,%XMM12

(171) 0x424b7b MOVAPD	%XMM7,%XMM13

(171) 0x424b80 ADDSD	%XMM3,%XMM13

(171) 0x424b85 UNPCKLPD	%XMM12,%XMM13

(171) 0x424b8a MOVSXD	%EDX,%RDX

(171) 0x424b8d MULPD	%XMM10,%XMM13

(171) 0x424b92 MOVSD	(%R8,%RDX,8),%XMM12

(171) 0x424b98 UNPCKLPD	%XMM11,%XMM12

(171) 0x424b9d DIVPD	%XMM12,%XMM13

(171) 0x424ba2 MOVAPD	%XMM13,%XMM12

(171) 0x424ba7 UNPCKHPD	%XMM13,%XMM12

(171) 0x424bac ADDSD	%XMM13,%XMM12

(171) 0x424bb1 MULSD	%XMM4,%XMM11

(171) 0x424bb6 MULSD	%XMM12,%XMM11

(171) 0x424bbb MOVAPD	%XMM10,%XMM12

(171) 0x424bc0 MINSD	%XMM11,%XMM12

(171) 0x424bc5 CMPSD	$0x3,%XMM11,%XMM11

(171) 0x424bcb MOVAPD	%XMM11,%XMM13

(171) 0x424bd0 ANDNPD	%XMM12,%XMM13

(171) 0x424bd5 ANDPD	%XMM10,%XMM11

(171) 0x424bda ORPD	%XMM13,%XMM11

(171) 0x424bdf PSHUFD	$-0x12,%XMM10,%XMM10

(171) 0x424be5 MOVDQA	%XMM10,%XMM12

(171) 0x424bea MINSD	%XMM11,%XMM12

(171) 0x424bef CMPSD	$0x3,%XMM11,%XMM11

(171) 0x424bf5 MOVAPD	%XMM11,%XMM13

(171) 0x424bfa ANDNPD	%XMM12,%XMM13

(171) 0x424bff ANDPD	%XMM10,%XMM11

(171) 0x424c04 ORPD	%XMM13,%XMM11

(171) 0x424c09 CMPSD	$0x6,%XMM0,%XMM9

(171) 0x424c0f MOVAPD	%XMM9,%XMM10

(171) 0x424c14 ANDPD	%XMM11,%XMM10

(171) 0x424c19 XORPD	%XMM5,%XMM11

(171) 0x424c1e ANDNPD	%XMM11,%XMM9

(171) 0x424c23 ORPD	%XMM10,%XMM9

(171) 0x424c28 MOVAPD	%XMM9,%XMM11

(171) 0x424c2d JMP	424a50

0x424c32 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:108-139
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108-139
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.17 to 9.50 cycles (2.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 23.17 to 2.56 cycles (9.05x speedup).

Details

34% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

16% of SSE/AVX loads are used in vector version.
40% of SSE/AVX stores are used in vector version.
14% of SSE/AVX addition or subtraction instructions are used in vector version.
45% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 232 bytes. The binary function is storing 272 bytes.

General properties

nb instructions	138
nb uops	139
loop length	628
used x86 registers	16
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	29

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.17 cycles
front end	23.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.10	9.50	13.33	13.33	17.50	9.50	7.90	17.50	17.50	17.50	8.00	13.33
cycles	8.10	9.50	13.33	13.33	17.50	9.50	7.90	17.50	17.50	17.50	8.00	13.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.17
Dispatch	17.50
Overall L1	23.17

Vectorization ratios

INT

all	32%
load	7%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
other	43%

all	50%
load	40%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	34%
load	16%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

Vector efficiency ratios

INT

all	15%
load	12%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
other	17%

all	18%
load	17%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	15%
load	13%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.17 cycles. At this rate:

5% of peak load performance is reached (10.01 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (11.74 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 23.17 to 17.50 cycles (1.32x speedup).

ASM code

In the binary file, the address of the function is: 424330

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x108,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RCX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 4249e3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x6b3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x90(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x68(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x60(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b7910,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x40(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x68(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 4249ff <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x6cf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EBX,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%R13),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R13),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R12),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R12),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R15),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R15),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $-0x2,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %RAX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 424a20 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x6f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %R11D,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RSI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVD %EBX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RDX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RDI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R8,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R12,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RCX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x76f7c(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOVQ %XMM1,%R12	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM1,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,%RDI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XORPD %XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVDQA %XMM2,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSRLQ $0x20,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM2,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R9,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM3,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSRLQ $0x20,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM3,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
JMP 424645 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x315>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x108,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
CMP %R13,-0x70(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JNE 424a1d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x6ed>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b7930,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x108,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD %R13,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PXOR %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD 0x760c4(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVSD 0x76bec(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSD 0x7605c(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSD 0x76be4(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVAPD 0x76bc4(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
JMP 424a84 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x754>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:108-139
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108-139
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.17 to 9.50 cycles (2.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

34% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

16% of SSE/AVX loads are used in vector version.
40% of SSE/AVX stores are used in vector version.
14% of SSE/AVX addition or subtraction instructions are used in vector version.
45% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 232 bytes. The binary function is storing 272 bytes.

General properties

nb instructions	138
nb uops	139
loop length	628
used x86 registers	16
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	29

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.17 cycles
front end	23.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.10	9.50	13.33	13.33	17.50	9.50	7.90	17.50	17.50	17.50	8.00	13.33
cycles	8.10	9.50	13.33	13.33	17.50	9.50	7.90	17.50	17.50	17.50	8.00	13.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.17
Dispatch	17.50
Overall L1	23.17

Vectorization ratios

INT

all	32%
load	7%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
other	43%

all	50%
load	40%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	34%
load	16%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

Vector efficiency ratios

INT

all	15%
load	12%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
other	17%

all	18%
load	17%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	15%
load	13%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.17 cycles. At this rate:

5% of peak load performance is reached (10.01 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (11.74 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 424330

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x108,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RCX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 4249e3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x6b3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x90(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x68(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x60(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b7910,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x40(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x68(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 4249ff <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x6cf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EBX,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%R13),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R13),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R12),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R12),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R15),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R15),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $-0x2,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %RAX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 424a20 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x6f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %R11D,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RSI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVD %EBX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RDX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RDI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R8,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R12,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RCX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x76f7c(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOVQ %XMM1,%R12	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM1,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,%RDI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XORPD %XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVDQA %XMM2,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSRLQ $0x20,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM2,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R9,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM3,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSRLQ $0x20,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM3,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
JMP 424645 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x315>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x108,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
CMP %R13,-0x70(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JNE 424a1d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x6ed>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b7930,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x108,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD %R13,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PXOR %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD 0x760c4(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVSD 0x76bec(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSD 0x7605c(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSD 0x76be4(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVAPD 0x76bc4(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
JMP 424a84 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.27+0x754>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	6.16	2.44
○Loop 172 - advec_mom.cpp:109-139 - exec	6.16	2.43
○Loop 171 - advec_mom.cpp:109-139 - exec	0.00	0.00

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Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code