OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .extracted.17]

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:157-161 [...]	Coverage (incl. loops): 1.39% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 157 - 161

--------------------------------------------------------------------------------

157: #pragma omp parallel for simd collapse(2)

158:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

159:         for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

160:           node_flux(i, j) = 0.25 * (mass_flux_y(i - 1, j + 0) + mass_flux_y(i, j) + mass_flux_y(i - 1, j + 1) + mass_flux_y(i + 0, j + 1));

161:         }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x4239c0 PUSH	%RBP

0x4239c1 MOV	%RSP,%RBP

0x4239c4 PUSH	%R15

0x4239c6 PUSH	%R14

0x4239c8 PUSH	%R13

0x4239ca PUSH	%R12

0x4239cc PUSH	%RBX

0x4239cd SUB	$0x78,%RSP

0x4239d1 MOV	0x20(%RBP),%RAX

0x4239d5 MOV	0x10(%RBP),%R15

0x4239d9 MOVL	$0,-0x30(%RBP)

0x4239e0 TEST	%RAX,%RAX

0x4239e3 JS	423d65

0x4239e9 MOV	%R9,%RBX

0x4239ec MOV	%R8,%R14

0x4239ef MOV	%RCX,%R12

0x4239f2 MOV	%RDX,%R13

0x4239f5 MOV	(%RDI),%ESI

0x4239f7 MOVQ	$0,-0x40(%RBP)

0x4239ff MOV	%RAX,-0x38(%RBP)

0x423a03 MOVQ	$0x1,-0x70(%RBP)

0x423a0b SUB	$0x8,%RSP

0x423a0f LEA	-0x70(%RBP),%RAX

0x423a13 LEA	-0x30(%RBP),%RCX

0x423a17 LEA	-0x40(%RBP),%R8

0x423a1b LEA	-0x38(%RBP),%R9

0x423a1f MOV	$0x4b7850,%EDI

0x423a24 MOV	%ESI,-0x2c(%RBP)

0x423a27 MOV	$0x22,%EDX

0x423a2c PUSH	$0x1

0x423a2e PUSH	$0x1

0x423a30 PUSH	%RAX

0x423a31 CALL	4031f0 <__kmpc_for_static_init_8@plt>

0x423a36 ADD	$0x20,%RSP

0x423a3a MOV	-0x40(%RBP),%RCX

0x423a3e MOV	-0x38(%RBP),%RSI

0x423a42 CMP	%RSI,%RCX

0x423a45 JA	423d4a

0x423a4b SUB	%EBX,%R15D

0x423a4e MOV	(%R13),%RDI

0x423a52 MOV	0x10(%R13),%R8

0x423a56 MOV	(%R12),%R13

0x423a5a MOV	0x10(%R12),%R12

0x423a5f INC	%RSI

0x423a62 MOV	%RSI,%RAX

0x423a65 SUB	%RCX,%RAX

0x423a68 MOV	$-0x2,%R11D

0x423a6e AND	%RAX,%R11

0x423a71 JE	423df3

0x423a77 MOV	%RAX,-0x48(%RBP)

0x423a7b MOV	%R15,-0x60(%RBP)

0x423a7f MOVD	%R15D,%XMM0

0x423a84 PSHUFD	$0x44,%XMM0,%XMM0

0x423a89 MOVD	%R14D,%XMM1

0x423a8e PSHUFD	$0x50,%XMM1,%XMM1

0x423a93 MOVDQA	%XMM1,-0xa0(%RBP)

0x423a9b MOV	%RBX,-0x68(%RBP)

0x423a9f MOVD	%EBX,%XMM1

0x423aa3 PSHUFD	$0x50,%XMM1,%XMM1

0x423aa8 MOVDQA	%XMM1,-0x90(%RBP)

0x423ab0 MOVQ	%RDI,%XMM1

0x423ab5 PSHUFD	$0x44,%XMM1,%XMM8

0x423abb MOV	%R13,-0x58(%RBP)

0x423abf MOVQ	%R13,%XMM1

0x423ac4 PSHUFD	$0x44,%XMM1,%XMM4

0x423ac9 MOVQ	%RCX,%XMM1

0x423ace PSHUFD	$0x44,%XMM1,%XMM5

0x423ad3 PADDQ	0x77955(%RIP),%XMM5

0x423adb XOR	%R13D,%R13D

0x423ade MOV	%R12,%RAX

0x423ae1 MOVQ	%XMM0,%R12

0x423ae6 MOVDQA	%XMM0,-0x80(%RBP)

0x423aeb PSHUFD	$-0x12,%XMM0,%XMM1

0x423af0 MOVQ	%XMM1,%R9

0x423af5 MOVDQA	%XMM8,%XMM6

0x423afa PSRLQ	$0x20,%XMM6

0x423aff MOVQ	%R8,%XMM2

0x423b04 PSHUFD	$0x44,%XMM2,%XMM9

0x423b0a MOVDQA	%XMM4,%XMM11

0x423b0f PSRLQ	$0x20,%XMM11

0x423b15 MOV	%RAX,-0x50(%RBP)

0x423b19 MOVQ	%RAX,%XMM2

0x423b1e PSHUFD	$0x44,%XMM2,%XMM12

0x423b24 PCMPEQD	%XMM0,%XMM0

0x423b28 NOPL	(%RAX,%RAX,1)

(168) 0x423b30 MOVQ	%XMM5,%RAX

(168) 0x423b35 XOR	%EDX,%EDX

(168) 0x423b37 DIV	%R12

(168) 0x423b3a MOVQ	%RAX,%XMM2

(168) 0x423b3f PSHUFD	$-0x12,%XMM5,%XMM3

(168) 0x423b44 MOVQ	%XMM3,%RAX

(168) 0x423b49 XOR	%EDX,%EDX

(168) 0x423b4b DIV	%R9

(168) 0x423b4e MOVQ	%RAX,%XMM3

(168) 0x423b53 PUNPCKLQDQ	%XMM3,%XMM2

(168) 0x423b57 PSHUFD	$-0x18,%XMM2,%XMM7

(168) 0x423b5c PADDD	-0xa0(%RBP),%XMM7

(168) 0x423b64 PMULUDQ	-0x80(%RBP),%XMM2

(168) 0x423b69 MOVDQA	%XMM5,%XMM3

(168) 0x423b6d PSUBQ	%XMM2,%XMM3

(168) 0x423b71 PSHUFD	$-0x18,%XMM3,%XMM10

(168) 0x423b77 PXOR	%XMM2,%XMM2

(168) 0x423b7b PADDD	-0x90(%RBP),%XMM10

(168) 0x423b84 PXOR	%XMM15,%XMM15

(168) 0x423b89 PCMPGTD	%XMM7,%XMM15

(168) 0x423b8e MOVDQA	%XMM7,%XMM13

(168) 0x423b93 MOVDQA	%XMM10,%XMM14

(168) 0x423b98 PUNPCKLDQ	%XMM15,%XMM13

(168) 0x423b9d MOVDQA	%XMM6,%XMM1

(168) 0x423ba1 PMULUDQ	%XMM13,%XMM1

(168) 0x423ba6 PADDD	%XMM0,%XMM14

(168) 0x423bab PUNPCKLDQ	0x76bec(%RIP),%XMM15

(168) 0x423bb4 MOVDQA	%XMM8,%XMM3

(168) 0x423bb9 PMULUDQ	%XMM15,%XMM3

(168) 0x423bbe PADDQ	%XMM1,%XMM3

(168) 0x423bc2 PXOR	%XMM1,%XMM1

(168) 0x423bc6 PCMPGTD	%XMM10,%XMM1

(168) 0x423bcb PUNPCKLDQ	%XMM1,%XMM10

(168) 0x423bd0 PCMPGTD	%XMM14,%XMM2

(168) 0x423bd5 MOVDQA	%XMM8,%XMM1

(168) 0x423bda PMULUDQ	%XMM13,%XMM1

(168) 0x423bdf PSLLQ	$0x20,%XMM3

(168) 0x423be4 PUNPCKLDQ	%XMM2,%XMM14

(168) 0x423be9 PSUBD	%XMM0,%XMM7

(168) 0x423bed PXOR	%XMM2,%XMM2

(168) 0x423bf1 PCMPGTD	%XMM7,%XMM2

(168) 0x423bf5 PADDQ	%XMM1,%XMM3

(168) 0x423bf9 PUNPCKLDQ	%XMM2,%XMM7

(168) 0x423bfd MOVDQA	%XMM8,%XMM1

(168) 0x423c02 PMULUDQ	%XMM7,%XMM1

(168) 0x423c06 PMULUDQ	%XMM6,%XMM7

(168) 0x423c0a PSHUFD	$-0x2c,%XMM2,%XMM2

(168) 0x423c0f PMULUDQ	%XMM8,%XMM2

(168) 0x423c14 PADDQ	%XMM7,%XMM2

(168) 0x423c18 PSLLQ	$0x20,%XMM2

(168) 0x423c1d PADDQ	%XMM1,%XMM2

(168) 0x423c21 MOVDQA	%XMM3,%XMM1

(168) 0x423c25 PADDQ	%XMM10,%XMM3

(168) 0x423c2a PSLLQ	$0x3,%XMM3

(168) 0x423c2f PADDQ	%XMM9,%XMM3

(168) 0x423c34 MOVQ	%XMM3,%RAX

(168) 0x423c39 PSHUFD	$-0x12,%XMM3,%XMM3

(168) 0x423c3e MOVQ	%XMM3,%RDX

(168) 0x423c43 PADDQ	%XMM14,%XMM1

(168) 0x423c48 PSLLQ	$0x3,%XMM1

(168) 0x423c4d PADDQ	%XMM9,%XMM1

(168) 0x423c52 MOVQ	%XMM1,%R10

(168) 0x423c57 PSHUFD	$-0x12,%XMM1,%XMM1

(168) 0x423c5c PADDQ	%XMM2,%XMM14

(168) 0x423c61 PSLLQ	$0x3,%XMM14

(168) 0x423c67 MOVQ	%XMM1,%RBX

(168) 0x423c6c PADDQ	%XMM9,%XMM14

(168) 0x423c71 MOVQ	%XMM14,%R15

(168) 0x423c76 PSHUFD	$-0x12,%XMM14,%XMM1

(168) 0x423c7c MOVSD	(%RAX),%XMM3

(168) 0x423c80 MOVQ	%XMM1,%RAX

(168) 0x423c85 PADDQ	%XMM10,%XMM2

(168) 0x423c8a PSLLQ	$0x3,%XMM2

(168) 0x423c8f MOVSD	(%R10),%XMM1

(168) 0x423c94 PADDQ	%XMM9,%XMM2

(168) 0x423c99 MOVQ	%XMM2,%R10

(168) 0x423c9e MOVHPD	(%RDX),%XMM3

(168) 0x423ca2 PSHUFD	$-0x12,%XMM2,%XMM2

(168) 0x423ca7 MOVQ	%XMM2,%RDX

(168) 0x423cac MOVHPD	(%RBX),%XMM1

(168) 0x423cb0 MOVSD	(%R15),%XMM7

(168) 0x423cb5 MOVHPD	(%RAX),%XMM7

(168) 0x423cb9 ADDPD	%XMM1,%XMM3

(168) 0x423cbd MOVSD	(%R10),%XMM2

(168) 0x423cc2 MOVHPD	(%RDX),%XMM2

(168) 0x423cc6 ADDPD	%XMM7,%XMM2

(168) 0x423cca ADDPD	%XMM3,%XMM2

(168) 0x423cce MOVDQA	%XMM4,%XMM1

(168) 0x423cd2 PMULUDQ	%XMM13,%XMM1

(168) 0x423cd7 PMULUDQ	%XMM11,%XMM13

(168) 0x423cdc PMULUDQ	%XMM4,%XMM15

(168) 0x423ce1 PADDQ	%XMM13,%XMM15

(168) 0x423ce6 PADDQ	%XMM10,%XMM1

(168) 0x423ceb PSLLQ	$0x20,%XMM15

(168) 0x423cf1 PADDQ	%XMM15,%XMM1

(168) 0x423cf6 PSLLQ	$0x3,%XMM1

(168) 0x423cfb PADDQ	%XMM12,%XMM1

(168) 0x423d00 MOVQ	%XMM1,%RAX

(168) 0x423d05 PSHUFD	$-0x12,%XMM1,%XMM1

(168) 0x423d0a MOVQ	%XMM1,%RDX

(168) 0x423d0f MULPD	0x77729(%RIP),%XMM2

(168) 0x423d17 MOVLPD	%XMM2,(%RAX)

(168) 0x423d1b MOVHPD	%XMM2,(%RDX)

(168) 0x423d1f PADDQ	0x77729(%RIP),%XMM5

(168) 0x423d27 ADD	$0x2,%R13

(168) 0x423d2b CMP	%R11,%R13

(168) 0x423d2e JB	423b30

0x423d34 CMP	%R11,-0x48(%RBP)

0x423d38 MOV	-0x68(%RBP),%RBX

0x423d3c MOV	-0x60(%RBP),%R15

0x423d40 MOV	-0x58(%RBP),%R13

0x423d44 MOV	-0x50(%RBP),%R12

0x423d48 JNE	423d74

0x423d4a MOV	$0x4b7870,%EDI

0x423d4f MOV	-0x2c(%RBP),%ESI

0x423d52 ADD	$0x78,%RSP

0x423d56 POP	%RBX

0x423d57 POP	%R12

0x423d59 POP	%R13

0x423d5b POP	%R14

0x423d5d POP	%R15

0x423d5f POP	%RBP

0x423d60 JMP	403050

0x423d65 ADD	$0x78,%RSP

0x423d69 POP	%RBX

0x423d6a POP	%R12

0x423d6c POP	%R13

0x423d6e POP	%R14

0x423d70 POP	%R15

0x423d72 POP	%RBP

0x423d73 RET

0x423d74 ADD	%R11,%RCX

0x423d77 JMP	423df3

0x423d79 NOPL	(%RAX)

(167) 0x423d80 MOV	%RCX,%RAX

(167) 0x423d83 XOR	%EDX,%EDX

(167) 0x423d85 DIV	%R15

(167) 0x423d88 LEA	(%RAX,%R14,1),%R9D

(167) 0x423d8c ADD	%EBX,%EDX

(167) 0x423d8e MOVSXD	%R9D,%R9

(167) 0x423d91 MOV	%RDI,%R10

(167) 0x423d94 IMUL	%R9,%R10

(167) 0x423d98 MOVSXD	%EDX,%RDX

(167) 0x423d9b LEA	(%R10,%RDX,1),%R11

(167) 0x423d9f DEC	%R11

(167) 0x423da2 ADD	%RDX,%R10

(167) 0x423da5 MOVSD	(%R8,%R10,8),%XMM0

(167) 0x423dab ADDSD	(%R8,%R11,8),%XMM0

(167) 0x423db1 ADD	%R14D,%EAX

(167) 0x423db4 INC	%EAX

(167) 0x423db6 CLTQ

(167) 0x423db8 IMUL	%RDI,%RAX

(167) 0x423dbc LEA	(%RAX,%RDX,1),%R10

(167) 0x423dc0 DEC	%R10

(167) 0x423dc3 ADDSD	(%R8,%R10,8),%XMM0

(167) 0x423dc9 ADD	%RDX,%RAX

(167) 0x423dcc ADDSD	(%R8,%RAX,8),%XMM0

(167) 0x423dd2 MULSD	0x77646(%RIP),%XMM0

(167) 0x423dda IMUL	%R13,%R9

(167) 0x423dde ADD	%RDX,%R9

(167) 0x423de1 MOVSD	%XMM0,(%R12,%R9,8)

(167) 0x423de7 INC	%RCX

(167) 0x423dea CMP	%RCX,%RSI

(167) 0x423ded JE	423d4a

(167) 0x423df3 MOV	%RCX,%RAX

(167) 0x423df6 SHR	$0x20,%RAX

(167) 0x423dfa JNE	423d80

(167) 0x423dfc MOV	%ECX,%EAX

(167) 0x423dfe XOR	%EDX,%EDX

(167) 0x423e00 DIV	%R15D

(167) 0x423e03 JMP	423d88

0x423e05 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:157-161
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:157-161
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.00 to 8.50 cycles (2.24x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 19.00 to 1.90 cycles (9.99x speedup).

Details

31% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

11% of SSE/AVX loads are used in vector version.
23% of SSE/AVX stores are used in vector version.
12% of SSE/AVX addition or subtraction instructions are used in vector version.
46% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:157

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 128 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	113
nb uops	114
loop length	455
used x86 registers	15
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.00 cycles
front end	19.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.30	8.50	9.67	9.67	11.50	8.50	7.30	11.50	11.50	11.50	7.40	9.67
cycles	7.30	8.50	9.67	9.67	11.50	8.50	7.30	11.50	11.50	11.50	7.40	9.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.00
Dispatch	11.50
Overall L1	19.00

Vectorization ratios

all	31%
load	11%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	46%

Vector efficiency ratios

all	15%
load	12%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.00 cycles. At this rate:

3% of peak load performance is reached (6.74 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.32 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 19.00 to 11.50 cycles (1.65x speedup).

ASM code

In the binary file, the address of the function is: 4239c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 423d65 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.17+0x3a5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x70(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x40(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b7850,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x40(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %RSI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 423d4a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.17+0x38a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %EBX,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%R13),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R13),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R12),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R12),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $-0x2,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %RAX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 423df3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.17+0x433>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %R15D,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVD %R14D,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM1,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %RBX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %EBX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM1,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RDI,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOV %R13,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %R13,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RCX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x77955(%RIP),%XMM5	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ %XMM0,%R12	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM0,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%R9	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM8,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R8,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM2,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM4,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %RAX,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM2,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PCMPEQD %XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R11,-0x48(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x68(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x60(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x58(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 423d74 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.17+0x3b4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b7870,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x2c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
ADD %R11,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 423df3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.17+0x433>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:157-161
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:157-161
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.00 to 8.50 cycles (2.24x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

31% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

11% of SSE/AVX loads are used in vector version.
23% of SSE/AVX stores are used in vector version.
12% of SSE/AVX addition or subtraction instructions are used in vector version.
46% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:157

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 128 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	113
nb uops	114
loop length	455
used x86 registers	15
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.00 cycles
front end	19.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.30	8.50	9.67	9.67	11.50	8.50	7.30	11.50	11.50	11.50	7.40	9.67
cycles	7.30	8.50	9.67	9.67	11.50	8.50	7.30	11.50	11.50	11.50	7.40	9.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.00
Dispatch	11.50
Overall L1	19.00

Vectorization ratios

all	31%
load	11%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	46%

Vector efficiency ratios

all	15%
load	12%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.00 cycles. At this rate:

3% of peak load performance is reached (6.74 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.32 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4239c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 423d65 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.17+0x3a5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x70(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x40(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b7850,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x40(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %RSI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 423d4a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.17+0x38a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %EBX,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%R13),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R13),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R12),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R12),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $-0x2,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %RAX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 423df3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.17+0x433>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %R15D,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVD %R14D,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM1,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %RBX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %EBX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM1,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RDI,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOV %R13,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %R13,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RCX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x77955(%RIP),%XMM5	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ %XMM0,%R12	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM0,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM1,%R9	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM8,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R8,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM2,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM4,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %RAX,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM2,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PCMPEQD %XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0-1	0.50	vect (25.0%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R11,-0x48(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x68(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x60(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x58(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 423d74 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.17+0x3b4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b7870,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x2c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
ADD %R11,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 423df3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.17+0x433>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	1.39	0.55
○Loop 168 - advec_mom.cpp:158-161 - exec	1.39	0.55
○Loop 167 - advec_mom.cpp:158-161 - exec	0.00	0.00

Report Configuration

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Matching between your function (in the source code) and the binary function

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Cycles summary

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ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code