OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .extracted.7]

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:180-211 [...]	Coverage (incl. loops): 7.06% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 180 - 211

--------------------------------------------------------------------------------

180: #pragma omp parallel for simd collapse(2)

181:     for (int j = (y_min - 1 + 1); j < (y_max + 1 + 2); j++) {

182:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++)

183:         ({

184:           int upwind, donor, downwind, dif;

185:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

186:           if (node_flux(i, j) < 0.0) {

187:             upwind = j + 2;

188:             donor = j + 1;

189:             downwind = j;

190:             dif = donor;

191:           } else {

192:             upwind = j - 1;

193:             donor = j;

194:             downwind = j + 1;

195:             dif = upwind;

196:           }

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x4227f0 PUSH	%RBP

0x4227f1 MOV	%RSP,%RBP

0x4227f4 PUSH	%R15

0x4227f6 PUSH	%R14

0x4227f8 PUSH	%R13

0x4227fa PUSH	%R12

0x4227fc PUSH	%RBX

0x4227fd SUB	$0x118,%RSP

0x422804 MOV	%RCX,%R13

0x422807 MOV	0x38(%RBP),%RAX

0x42280b MOV	0x28(%RBP),%RBX

0x42280f MOV	0x20(%RBP),%R14

0x422813 MOV	0x10(%RBP),%RCX

0x422817 MOV	%RCX,-0x50(%RBP)

0x42281b MOV	0x18(%RBP),%ECX

0x42281e MOV	%RCX,-0x48(%RBP)

0x422822 MOVL	$0,-0x30(%RBP)

0x422829 TEST	%RAX,%RAX

0x42282c JS	422ef1

0x422832 MOV	%R8,%R12

0x422835 MOV	%RDX,%R15

0x422838 MOV	%R9,-0x70(%RBP)

0x42283c MOV	(%RDI),%ESI

0x42283e MOVQ	$0,-0x60(%RBP)

0x422846 MOV	%RAX,-0x58(%RBP)

0x42284a MOVQ	$0x1,-0xa0(%RBP)

0x422855 SUB	$0x8,%RSP

0x422859 LEA	-0xa0(%RBP),%RAX

0x422860 LEA	-0x30(%RBP),%RCX

0x422864 LEA	-0x60(%RBP),%R8

0x422868 LEA	-0x58(%RBP),%R9

0x42286c MOV	$0x4b7790,%EDI

0x422871 MOV	%ESI,-0x2c(%RBP)

0x422874 MOV	$0x22,%EDX

0x422879 PUSH	$0x1

0x42287b PUSH	$0x1

0x42287d PUSH	%RAX

0x42287e CALL	4031f0 <__kmpc_for_static_init_8@plt>

0x422883 ADD	$0x20,%RSP

0x422887 MOV	-0x60(%RBP),%RCX

0x42288b MOV	-0x58(%RBP),%RDX

0x42288f CMP	%RDX,%RCX

0x422892 JA	422f09

0x422898 MOV	%RBX,%R9

0x42289b MOV	%R14,%RBX

0x42289e MOV	%RDX,%RAX

0x4228a1 SUB	%EBX,%R9D

0x4228a4 MOV	(%R13),%RDX

0x4228a8 MOV	0x10(%R13),%RSI

0x4228ac MOV	(%R12),%RDI

0x4228b0 MOV	0x10(%R12),%R10

0x4228b5 MOV	(%R15),%R11

0x4228b8 MOV	0x10(%R15),%R15

0x4228bc MOV	-0x70(%RBP),%R14

0x4228c0 MOV	(%R14),%R8

0x4228c3 MOV	0x10(%R14),%R14

0x4228c7 INC	%RAX

0x4228ca MOV	%RAX,-0x98(%RBP)

0x4228d1 SUB	%RCX,%RAX

0x4228d4 MOV	$-0x2,%R13D

0x4228da AND	%RAX,%R13

0x4228dd MOV	%RSI,-0x40(%RBP)

0x4228e1 MOV	%RDI,-0x38(%RBP)

0x4228e5 MOV	%R8,-0x88(%RBP)

0x4228ec MOV	%RDX,-0x90(%RBP)

0x4228f3 JE	422f2a

0x4228f9 MOV	%RAX,-0x78(%RBP)

0x4228fd MOVD	%R9D,%XMM0

0x422902 PSHUFD	$0x44,%XMM0,%XMM1

0x422907 MOVD	-0x48(%RBP),%XMM0

0x42290c PSHUFD	$0x50,%XMM0,%XMM0

0x422911 MOVDQA	%XMM0,-0x130(%RBP)

0x422919 MOVQ	%RBX,%XMM0

0x42291e PSHUFD	$0x44,%XMM0,%XMM0

0x422923 MOVDQA	%XMM0,-0x120(%RBP)

0x42292b MOVQ	%RDX,%XMM0

0x422930 PSHUFD	$0x44,%XMM0,%XMM2

0x422935 MOVQ	%RDI,%XMM0

0x42293a PSHUFD	$0x44,%XMM0,%XMM3

0x42293f MOVQ	%R11,%XMM0

0x422944 PSHUFD	$0x44,%XMM0,%XMM0

0x422949 MOVDQA	%XMM0,-0xf0(%RBP)

0x422951 MOVQ	%R8,%XMM0

0x422956 PSHUFD	$0x44,%XMM0,%XMM0

0x42295b MOVDQA	%XMM0,-0xe0(%RBP)

0x422963 MOVQ	%RCX,%XMM0

0x422968 PSHUFD	$0x44,%XMM0,%XMM7

0x42296d PADDQ	0x78abb(%RIP),%XMM7

0x422975 XOR	%R8D,%R8D

0x422978 MOVQ	%XMM1,-0x80(%RBP)

0x42297d MOVDQA	%XMM1,-0x140(%RBP)

0x422985 PSHUFD	$-0x12,%XMM1,%XMM0

0x42298a MOVQ	%XMM0,%RDI

0x42298f XORPD	%XMM5,%XMM5

0x422993 MOVDQA	%XMM2,-0x110(%RBP)

0x42299b PSRLQ	$0x20,%XMM2

0x4229a0 MOVDQA	%XMM2,-0xd0(%RBP)

0x4229a8 MOVQ	%RSI,%XMM0

0x4229ad PSHUFD	$0x44,%XMM0,%XMM0

0x4229b2 MOVDQA	%XMM0,-0xc0(%RBP)

0x4229ba MOVDQA	%XMM3,-0x100(%RBP)

0x4229c2 PSRLQ	$0x20,%XMM3

0x4229c7 MOVDQA	%XMM3,-0xb0(%RBP)

0x4229cf JMP	422b09

0x4229d4 NOPW	%CS:(%RAX,%RAX,1)

(164) 0x4229e0 DIVPD	%XMM1,%XMM13

(164) 0x4229e5 MOVAPD	%XMM9,%XMM1

(164) 0x4229ea ANDPD	%XMM2,%XMM9

(164) 0x4229ef MOVAPD	0x78bf9(%RIP),%XMM4

(164) 0x4229f7 SUBPD	%XMM3,%XMM4

(164) 0x4229fb MULPD	%XMM9,%XMM4

(164) 0x422a00 DIVPD	%XMM11,%XMM4

(164) 0x422a05 ADDPD	%XMM13,%XMM4

(164) 0x422a0a MULPD	%XMM4,%XMM10

(164) 0x422a0f MOVAPD	%XMM8,%XMM4

(164) 0x422a14 MINPD	%XMM10,%XMM4

(164) 0x422a19 CMPPD	$0x3,%XMM10,%XMM10

(164) 0x422a1f ANDPD	%XMM10,%XMM8

(164) 0x422a24 ANDNPD	%XMM4,%XMM10

(164) 0x422a29 ORPD	%XMM8,%XMM10

(164) 0x422a2e MOVAPD	%XMM9,%XMM4

(164) 0x422a33 MINPD	%XMM10,%XMM4

(164) 0x422a38 CMPPD	$0x3,%XMM10,%XMM10

(164) 0x422a3e ANDPD	%XMM10,%XMM9

(164) 0x422a43 ANDNPD	%XMM4,%XMM10

(164) 0x422a48 CMPPD	$0x6,%XMM5,%XMM1

(164) 0x422a4d ORPD	%XMM9,%XMM10

(164) 0x422a52 MOVAPD	%XMM10,%XMM4

(164) 0x422a57 XORPD	0x78bb1(%RIP),%XMM4

(164) 0x422a5f ANDPD	%XMM1,%XMM10

(164) 0x422a64 ANDNPD	%XMM4,%XMM1

(164) 0x422a68 ORPD	%XMM10,%XMM1

(164) 0x422a6d ANDPD	%XMM1,%XMM0

(164) 0x422a71 MOVAPD	0x78b67(%RIP),%XMM1

(164) 0x422a79 SUBPD	%XMM3,%XMM1

(164) 0x422a7d MULPD	%XMM0,%XMM1

(164) 0x422a81 ADDPD	%XMM14,%XMM1

(164) 0x422a86 MULPD	-0x70(%RBP),%XMM1

(164) 0x422a8b MOVDQA	-0xe0(%RBP),%XMM3

(164) 0x422a93 MOVDQA	%XMM3,%XMM0

(164) 0x422a97 PSRLQ	$0x20,%XMM0

(164) 0x422a9c PMULUDQ	%XMM12,%XMM0

(164) 0x422aa1 MOVDQA	%XMM3,%XMM2

(164) 0x422aa5 PMULUDQ	%XMM12,%XMM2

(164) 0x422aaa PSRLQ	$0x20,%XMM12

(164) 0x422ab0 PMULUDQ	%XMM3,%XMM12

(164) 0x422ab5 PADDQ	%XMM0,%XMM12

(164) 0x422aba PADDQ	%XMM15,%XMM2

(164) 0x422abf PSLLQ	$0x20,%XMM12

(164) 0x422ac5 PADDQ	%XMM12,%XMM2

(164) 0x422aca PSLLQ	$0x3,%XMM2

(164) 0x422acf MOVQ	%R14,%XMM0

(164) 0x422ad4 PSHUFD	$0x44,%XMM0,%XMM0

(164) 0x422ad9 PADDQ	%XMM2,%XMM0

(164) 0x422add MOVQ	%XMM0,%RAX

(164) 0x422ae2 PSHUFD	$-0x12,%XMM0,%XMM0

(164) 0x422ae7 MOVQ	%XMM0,%RDX

(164) 0x422aec MOVLPD	%XMM1,(%RAX)

(164) 0x422af0 MOVHPD	%XMM1,(%RDX)

(164) 0x422af4 PADDQ	0x78954(%RIP),%XMM7

(164) 0x422afc ADD	$0x2,%R8

(164) 0x422b00 CMP	%R13,%R8

(164) 0x422b03 JAE	422f03

(164) 0x422b09 MOV	%R9,%R12

(164) 0x422b0c MOVQ	%XMM7,%RAX

(164) 0x422b11 XOR	%EDX,%EDX

(164) 0x422b13 DIVQ	-0x80(%RBP)

(164) 0x422b17 MOVQ	%RAX,%XMM1

(164) 0x422b1c PSHUFD	$-0x12,%XMM7,%XMM0

(164) 0x422b21 MOVQ	%XMM0,%RAX

(164) 0x422b26 XOR	%EDX,%EDX

(164) 0x422b28 DIV	%RDI

(164) 0x422b2b MOVQ	%RAX,%XMM0

(164) 0x422b30 PUNPCKLQDQ	%XMM0,%XMM1

(164) 0x422b34 PSHUFD	$-0x18,%XMM1,%XMM0

(164) 0x422b39 PADDD	-0x130(%RBP),%XMM0

(164) 0x422b41 PMULUDQ	-0x140(%RBP),%XMM1

(164) 0x422b49 MOVDQA	%XMM7,%XMM2

(164) 0x422b4d PSUBQ	%XMM1,%XMM2

(164) 0x422b51 PADDQ	-0x120(%RBP),%XMM2

(164) 0x422b59 PSLLQ	$0x20,%XMM2

(164) 0x422b5e PSHUFD	$-0x13,%XMM2,%XMM15

(164) 0x422b64 MOVDQA	%XMM15,%XMM1

(164) 0x422b69 PSRAD	$0x1f,%XMM1

(164) 0x422b6e PUNPCKLDQ	%XMM1,%XMM15

(164) 0x422b73 PXOR	%XMM1,%XMM1

(164) 0x422b77 PCMPGTD	%XMM0,%XMM1

(164) 0x422b7b MOVDQA	%XMM0,%XMM12

(164) 0x422b80 PUNPCKLDQ	%XMM1,%XMM12

(164) 0x422b85 MOVDQA	-0x110(%RBP),%XMM4

(164) 0x422b8d MOVDQA	%XMM4,%XMM2

(164) 0x422b91 PMULUDQ	%XMM12,%XMM2

(164) 0x422b96 MOVDQA	-0xd0(%RBP),%XMM3

(164) 0x422b9e PMULUDQ	%XMM12,%XMM3

(164) 0x422ba3 PSHUFD	$-0x2c,%XMM1,%XMM1

(164) 0x422ba8 PMULUDQ	%XMM4,%XMM1

(164) 0x422bac PADDQ	%XMM3,%XMM1

(164) 0x422bb0 PSLLQ	$0x20,%XMM1

(164) 0x422bb5 PADDQ	%XMM2,%XMM1

(164) 0x422bb9 PADDQ	%XMM15,%XMM1

(164) 0x422bbe PSLLQ	$0x3,%XMM1

(164) 0x422bc3 PADDQ	-0xc0(%RBP),%XMM1

(164) 0x422bcb MOVQ	%XMM1,%RAX

(164) 0x422bd0 PSHUFD	$-0x12,%XMM1,%XMM1

(164) 0x422bd5 MOVQ	%XMM1,%RDX

(164) 0x422bda MOVSD	(%RAX),%XMM1

(164) 0x422bde MOVHPD	(%RDX),%XMM1

(164) 0x422be2 MOVAPD	%XMM1,-0x70(%RBP)

(164) 0x422be7 CMPPD	$0x1,%XMM5,%XMM1

(164) 0x422bec MOVDQA	%XMM0,%XMM13

(164) 0x422bf1 PCMPEQD	%XMM2,%XMM2

(164) 0x422bf5 PSUBD	%XMM2,%XMM13

(164) 0x422bfa MOVDQA	%XMM0,%XMM10

(164) 0x422bff PADDD	%XMM2,%XMM10

(164) 0x422c04 PXOR	%XMM3,%XMM3

(164) 0x422c08 PCMPGTD	%XMM13,%XMM3

(164) 0x422c0d MOVDQA	%XMM13,%XMM11

(164) 0x422c12 PUNPCKLDQ	%XMM3,%XMM11

(164) 0x422c17 PADDD	0x7a8b1(%RIP),%XMM0

(164) 0x422c1f MOVAPD	%XMM1,%XMM3

(164) 0x422c23 ANDNPD	%XMM11,%XMM3

(164) 0x422c28 MOVDQA	%XMM12,%XMM8

(164) 0x422c2d PAND	%XMM1,%XMM8

(164) 0x422c32 POR	%XMM3,%XMM8

(164) 0x422c37 MOVDQA	%XMM1,%XMM3

(164) 0x422c3b PANDN	%XMM12,%XMM3

(164) 0x422c40 PAND	%XMM1,%XMM11

(164) 0x422c45 POR	%XMM3,%XMM11

(164) 0x422c4a MOVDQA	%XMM11,%XMM3

(164) 0x422c4f PSRLQ	$0x20,%XMM3

(164) 0x422c54 MOVDQA	-0xf0(%RBP),%XMM9

(164) 0x422c5d MOVDQA	%XMM9,%XMM2

(164) 0x422c62 PSRLQ	$0x20,%XMM2

(164) 0x422c67 MOVDQA	%XMM2,%XMM4

(164) 0x422c6b PMULUDQ	%XMM11,%XMM4

(164) 0x422c70 MOVDQA	%XMM9,%XMM6

(164) 0x422c75 PMULUDQ	%XMM3,%XMM6

(164) 0x422c79 PADDQ	%XMM4,%XMM6

(164) 0x422c7d PSLLQ	$0x20,%XMM6

(164) 0x422c82 MOVDQA	%XMM9,%XMM14

(164) 0x422c87 PMULUDQ	%XMM11,%XMM14

(164) 0x422c8c PADDQ	%XMM15,%XMM14

(164) 0x422c91 PADDQ	%XMM6,%XMM14

(164) 0x422c96 PSLLQ	$0x3,%XMM14

(164) 0x422c9c MOVQ	%R15,%XMM4

(164) 0x422ca1 PSHUFD	$0x44,%XMM4,%XMM4

(164) 0x422ca6 PADDQ	%XMM4,%XMM14

(164) 0x422cab MOVQ	%XMM14,%RAX

(164) 0x422cb0 PSHUFD	$-0x12,%XMM14,%XMM6

(164) 0x422cb6 MOVQ	%XMM6,%RDX

(164) 0x422cbb PXOR	%XMM6,%XMM6

(164) 0x422cbf PCMPGTD	%XMM10,%XMM6

(164) 0x422cc4 MOVDQA	%XMM10,%XMM14

(164) 0x422cc9 PUNPCKLDQ	%XMM6,%XMM14

(164) 0x422cce MOVDQA	%XMM1,%XMM6

(164) 0x422cd2 PANDN	%XMM14,%XMM6

(164) 0x422cd7 PXOR	%XMM14,%XMM14

(164) 0x422cdc PCMPGTD	%XMM0,%XMM14

(164) 0x422ce1 PUNPCKLDQ	%XMM14,%XMM0

(164) 0x422ce6 PAND	%XMM1,%XMM0

(164) 0x422cea POR	%XMM6,%XMM0

(164) 0x422cee MOVDQA	%XMM2,%XMM6

(164) 0x422cf2 PMULUDQ	%XMM0,%XMM6

(164) 0x422cf6 MOVDQA	%XMM9,%XMM5

(164) 0x422cfb PMULUDQ	%XMM0,%XMM5

(164) 0x422cff PSRLQ	$0x20,%XMM0

(164) 0x422d04 PMULUDQ	%XMM9,%XMM0

(164) 0x422d09 PADDQ	%XMM6,%XMM0

(164) 0x422d0d PSLLQ	$0x20,%XMM0

(164) 0x422d12 PADDQ	%XMM15,%XMM5

(164) 0x422d17 PADDQ	%XMM0,%XMM5

(164) 0x422d1b MOVSD	(%RAX),%XMM14

(164) 0x422d20 MOVHPD	(%RDX),%XMM14

(164) 0x422d25 PSLLQ	$0x3,%XMM5

(164) 0x422d2a PADDQ	%XMM4,%XMM5

(164) 0x422d2e MOVQ	%XMM5,%RAX

(164) 0x422d33 PSHUFD	$-0x12,%XMM5,%XMM0

(164) 0x422d38 MOVQ	%XMM0,%RDX

(164) 0x422d3d PMULUDQ	%XMM8,%XMM2

(164) 0x422d42 MOVDQA	%XMM9,%XMM0

(164) 0x422d47 PMULUDQ	%XMM8,%XMM0

(164) 0x422d4c PSRLQ	$0x20,%XMM8

(164) 0x422d52 PMULUDQ	%XMM9,%XMM8

(164) 0x422d57 PADDQ	%XMM2,%XMM8

(164) 0x422d5c MOVSD	(%RAX),%XMM5

(164) 0x422d60 MOVHPD	(%RDX),%XMM5

(164) 0x422d64 PSLLQ	$0x20,%XMM8

(164) 0x422d6a PADDQ	%XMM15,%XMM0

(164) 0x422d6f PADDQ	%XMM8,%XMM0

(164) 0x422d74 MOVAPD	%XMM14,%XMM8

(164) 0x422d79 PSLLQ	$0x3,%XMM0

(164) 0x422d7e PADDQ	%XMM4,%XMM0

(164) 0x422d82 MOVQ	%XMM0,%RAX

(164) 0x422d87 PSHUFD	$-0x12,%XMM0,%XMM0

(164) 0x422d8c MOVQ	%XMM0,%RDX

(164) 0x422d91 MOVSD	(%RAX),%XMM9

(164) 0x422d96 MOVHPD	(%RDX),%XMM9

(164) 0x422d9b SUBPD	%XMM5,%XMM8

(164) 0x422da0 SUBPD	%XMM14,%XMM9

(164) 0x422da5 MOVAPD	%XMM9,%XMM4

(164) 0x422daa MULPD	%XMM8,%XMM4

(164) 0x422daf PXOR	%XMM0,%XMM0

(164) 0x422db3 CMPPD	$0x1,%XMM4,%XMM0

(164) 0x422db8 MOVMSKPD	%XMM0,%EAX

(164) 0x422dbc TEST	%EAX,%EAX

(164) 0x422dbe JE	422dc8

(164) 0x422dc0 MOV	-0x50(%RBP),%RDX

(164) 0x422dc4 MOV	0x8(%RDX),%RDX

(164) 0x422dc8 MOVDQA	-0xb0(%RBP),%XMM4

(164) 0x422dd0 PMULUDQ	%XMM11,%XMM4

(164) 0x422dd5 MOVDQA	-0x100(%RBP),%XMM5

(164) 0x422ddd PMULUDQ	%XMM5,%XMM3

(164) 0x422de1 PADDQ	%XMM4,%XMM3

(164) 0x422de5 PSLLQ	$0x20,%XMM3

(164) 0x422dea PMULUDQ	%XMM5,%XMM11

(164) 0x422def PADDQ	%XMM15,%XMM11

(164) 0x422df4 PADDQ	%XMM3,%XMM11

(164) 0x422df9 PSLLQ	$0x3,%XMM11

(164) 0x422dff MOVQ	%R10,%XMM3

(164) 0x422e04 PSHUFD	$0x44,%XMM3,%XMM3

(164) 0x422e09 PADDQ	%XMM11,%XMM3

(164) 0x422e0e MOVQ	%XMM3,%R9

(164) 0x422e13 PSHUFD	$-0x12,%XMM3,%XMM3

(164) 0x422e18 MOVQ	%XMM3,%RSI

(164) 0x422e1d MOVSD	(%R9),%XMM6

(164) 0x422e22 MOVHPD	(%RSI),%XMM6

(164) 0x422e26 MOVDQA	%XMM12,%XMM3

(164) 0x422e2b PSLLQ	$0x3,%XMM3

(164) 0x422e30 MOVQ	%RDX,%XMM4

(164) 0x422e35 PSHUFD	$0x44,%XMM4,%XMM4

(164) 0x422e3a PADDQ	%XMM4,%XMM3

(164) 0x422e3e TEST	$0x1,%AL

(164) 0x422e40 MOVAPD	0x77ca8(%RIP),%XMM2

(164) 0x422e48 JE	422e54

(164) 0x422e4a MOVQ	%XMM3,%RDX

(164) 0x422e4f MOVSD	(%RDX),%XMM11

(164) 0x422e54 TEST	$0x2,%AL

(164) 0x422e56 JE	422e67

(164) 0x422e58 PSHUFD	$-0x12,%XMM3,%XMM3

(164) 0x422e5d MOVQ	%XMM3,%RDX

(164) 0x422e62 MOVHPD	(%RDX),%XMM11

(164) 0x422e67 MOV	%R12,%R9

(164) 0x422e6a SHUFPS	$-0x18,%XMM1,%XMM1

(164) 0x422e6e PAND	%XMM1,%XMM13

(164) 0x422e73 PANDN	%XMM10,%XMM1

(164) 0x422e78 POR	%XMM13,%XMM1

(164) 0x422e7d MOVAPD	-0x70(%RBP),%XMM3

(164) 0x422e82 ANDPD	%XMM2,%XMM3

(164) 0x422e86 DIVPD	%XMM6,%XMM3

(164) 0x422e8a MOVAPD	%XMM11,%XMM10

(164) 0x422e8f MULPD	0x78768(%RIP),%XMM10

(164) 0x422e98 MOVAPD	%XMM3,%XMM13

(164) 0x422e9d ADDPD	0x7873a(%RIP),%XMM13

(164) 0x422ea6 PXOR	%XMM5,%XMM5

(164) 0x422eaa PCMPGTD	%XMM1,%XMM5

(164) 0x422eae PUNPCKLDQ	%XMM5,%XMM1

(164) 0x422eb2 PSLLQ	$0x3,%XMM1

(164) 0x422eb7 PADDQ	%XMM1,%XMM4

(164) 0x422ebb TEST	$0x1,%AL

(164) 0x422ebd JE	422ec8

(164) 0x422ebf MOVQ	%XMM4,%RDX

(164) 0x422ec4 MOVSD	(%RDX),%XMM1

(164) 0x422ec8 ANDPD	%XMM2,%XMM8

(164) 0x422ecd MULPD	%XMM8,%XMM13

(164) 0x422ed2 TEST	$0x2,%AL

(164) 0x422ed4 PXOR	%XMM5,%XMM5

(164) 0x422ed8 JE	4229e0

(164) 0x422ede PSHUFD	$-0x12,%XMM4,%XMM4

(164) 0x422ee3 MOVQ	%XMM4,%RAX

(164) 0x422ee8 MOVHPD	(%RAX),%XMM1

(164) 0x422eec JMP	4229e0

0x422ef1 ADD	$0x118,%RSP

0x422ef8 POP	%RBX

0x422ef9 POP	%R12

0x422efb POP	%R13

0x422efd POP	%R14

0x422eff POP	%R15

0x422f01 POP	%RBP

0x422f02 RET

0x422f03 CMP	%R13,-0x78(%RBP)

0x422f07 JNE	422f27

0x422f09 MOV	$0x4b77b0,%EDI

0x422f0e MOV	-0x2c(%RBP),%ESI

0x422f11 ADD	$0x118,%RSP

0x422f18 POP	%RBX

0x422f19 POP	%R12

0x422f1b POP	%R13

0x422f1d POP	%R14

0x422f1f POP	%R15

0x422f21 POP	%RBP

0x422f22 JMP	403050

0x422f27 ADD	%R13,%RCX

0x422f2a PXOR	%XMM0,%XMM0

0x422f2e MOVAPD	0x77bba(%RIP),%XMM1

0x422f36 MOVSD	0x786e2(%RIP),%XMM2

0x422f3e MOVSD	0x77b52(%RIP),%XMM3

0x422f46 MOVSD	0x786da(%RIP),%XMM4

0x422f4e MOVAPD	0x786ba(%RIP),%XMM5

0x422f56 JMP	422f9a

0x422f58 NOPL	(%RAX,%RAX,1)

(163) 0x422f60 MOVAPD	%XMM3,%XMM9

(163) 0x422f65 SUBSD	%XMM7,%XMM9

(163) 0x422f6a MULSD	%XMM11,%XMM9

(163) 0x422f6f ADDSD	%XMM8,%XMM9

(163) 0x422f74 MULSD	%XMM6,%XMM9

(163) 0x422f79 IMUL	-0x88(%RBP),%RDI

(163) 0x422f81 ADD	%RDX,%RDI

(163) 0x422f84 MOVSD	%XMM9,(%R14,%RDI,8)

(163) 0x422f8a INC	%RCX

(163) 0x422f8d CMP	%RCX,-0x98(%RBP)

(163) 0x422f94 JE	422f09

(163) 0x422f9a MOV	%RCX,%RAX

(163) 0x422f9d SHR	$0x20,%RAX

(163) 0x422fa1 JE	422fb0

(163) 0x422fa3 MOV	%RCX,%RAX

(163) 0x422fa6 XOR	%EDX,%EDX

(163) 0x422fa8 DIV	%R9

(163) 0x422fab JMP	422fb7

0x422fad NOPL	(%RAX)

(163) 0x422fb0 MOV	%ECX,%EAX

(163) 0x422fb2 XOR	%EDX,%EDX

(163) 0x422fb4 DIV	%R9D

(163) 0x422fb7 MOV	-0x40(%RBP),%R13

(163) 0x422fbb MOV	-0x48(%RBP),%R12

(163) 0x422fbf LEA	(%RAX,%R12,1),%R8D

(163) 0x422fc3 ADD	%EBX,%EDX

(163) 0x422fc5 MOVSXD	%EDX,%RDX

(163) 0x422fc8 MOVSXD	%R8D,%RDI

(163) 0x422fcb MOV	-0x90(%RBP),%RSI

(163) 0x422fd2 IMUL	%RDI,%RSI

(163) 0x422fd6 ADD	%RDX,%RSI

(163) 0x422fd9 MOVSD	(%R13,%RSI,8),%XMM6

(163) 0x422fe0 UCOMISD	%XMM6,%XMM0

(163) 0x422fe4 LEA	0x1(%RAX,%R12,1),%EAX

(163) 0x422fe9 MOVSXD	%EAX,%R13

(163) 0x422fec JBE	423000

(163) 0x422fee ADD	$0x2,%R8D

(163) 0x422ff2 MOV	%RDI,%R12

(163) 0x422ff5 JMP	42300c

0x422ff7 NOPW	(%RAX,%RAX,1)

(163) 0x423000 DEC	%R8D

(163) 0x423003 MOV	%R13,%R12

(163) 0x423006 MOV	%RDI,%R13

(163) 0x423009 MOV	%R8D,%EAX

(163) 0x42300c MOV	-0x38(%RBP),%RSI

(163) 0x423010 MOVAPD	%XMM6,%XMM7

(163) 0x423014 ANDPD	%XMM1,%XMM7

(163) 0x423018 IMUL	%R13,%RSI

(163) 0x42301c ADD	%RDX,%RSI

(163) 0x42301f DIVSD	(%R10,%RSI,8),%XMM7

(163) 0x423025 IMUL	%R11,%R13

(163) 0x423029 ADD	%RDX,%R13

(163) 0x42302c MOVSD	(%R15,%R13,8),%XMM8

(163) 0x423032 MOVSXD	%R8D,%RSI

(163) 0x423035 IMUL	%R11,%RSI

(163) 0x423039 ADD	%RDX,%RSI

(163) 0x42303c IMUL	%R11,%R12

(163) 0x423040 ADD	%RDX,%R12

(163) 0x423043 MOVAPD	%XMM8,%XMM10

(163) 0x423048 MOVHPD	(%R15,%R12,8),%XMM10

(163) 0x42304e MOVSD	(%R15,%RSI,8),%XMM9

(163) 0x423054 UNPCKLPD	%XMM8,%XMM9

(163) 0x423059 SUBPD	%XMM9,%XMM10

(163) 0x42305e MOVAPD	%XMM10,%XMM9

(163) 0x423063 UNPCKHPD	%XMM10,%XMM9

(163) 0x423068 MOVAPD	%XMM9,%XMM12

(163) 0x42306d MULSD	%XMM10,%XMM12

(163) 0x423072 XORPD	%XMM11,%XMM11

(163) 0x423077 UCOMISD	%XMM11,%XMM12

(163) 0x42307c JBE	422f60

(163) 0x423082 MOV	-0x50(%RBP),%RSI

(163) 0x423086 MOV	0x8(%RSI),%RSI

(163) 0x42308a MOVSD	(%RSI,%RDI,8),%XMM11

(163) 0x423090 ANDPD	%XMM1,%XMM10

(163) 0x423095 MOVAPD	%XMM2,%XMM12

(163) 0x42309a SUBSD	%XMM7,%XMM12

(163) 0x42309f MOVAPD	%XMM7,%XMM13

(163) 0x4230a4 ADDSD	%XMM3,%XMM13

(163) 0x4230a9 UNPCKLPD	%XMM12,%XMM13

(163) 0x4230ae CLTQ

(163) 0x4230b0 MULPD	%XMM10,%XMM13

(163) 0x4230b5 MOVSD	(%RSI,%RAX,8),%XMM12

(163) 0x4230bb UNPCKLPD	%XMM11,%XMM12

(163) 0x4230c0 DIVPD	%XMM12,%XMM13

(163) 0x4230c5 MOVAPD	%XMM13,%XMM12

(163) 0x4230ca UNPCKHPD	%XMM13,%XMM12

(163) 0x4230cf ADDSD	%XMM13,%XMM12

(163) 0x4230d4 MULSD	%XMM4,%XMM11

(163) 0x4230d9 MULSD	%XMM12,%XMM11

(163) 0x4230de MOVAPD	%XMM10,%XMM12

(163) 0x4230e3 MINSD	%XMM11,%XMM12

(163) 0x4230e8 CMPSD	$0x3,%XMM11,%XMM11

(163) 0x4230ee MOVAPD	%XMM11,%XMM13

(163) 0x4230f3 ANDNPD	%XMM12,%XMM13

(163) 0x4230f8 ANDPD	%XMM10,%XMM11

(163) 0x4230fd ORPD	%XMM13,%XMM11

(163) 0x423102 PSHUFD	$-0x12,%XMM10,%XMM10

(163) 0x423108 MOVDQA	%XMM10,%XMM12

(163) 0x42310d MINSD	%XMM11,%XMM12

(163) 0x423112 CMPSD	$0x3,%XMM11,%XMM11

(163) 0x423118 MOVAPD	%XMM11,%XMM13

(163) 0x42311d ANDNPD	%XMM12,%XMM13

(163) 0x423122 ANDPD	%XMM10,%XMM11

(163) 0x423127 ORPD	%XMM13,%XMM11

(163) 0x42312c CMPSD	$0x6,%XMM0,%XMM9

(163) 0x423132 MOVAPD	%XMM9,%XMM10

(163) 0x423137 ANDPD	%XMM11,%XMM10

(163) 0x42313c XORPD	%XMM5,%XMM11

(163) 0x423141 ANDNPD	%XMM11,%XMM9

(163) 0x423146 ORPD	%XMM10,%XMM9

(163) 0x42314b MOVAPD	%XMM9,%XMM11

(163) 0x423150 JMP	422f60

0x423155 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180-211
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.00 to 9.00 cycles (2.56x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 23.00 to 2.53 cycles (9.10x speedup).

Details

35% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

17% of SSE/AVX loads are used in vector version.
40% of SSE/AVX stores are used in vector version.
14% of SSE/AVX addition or subtraction instructions are used in vector version.
46% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 216 bytes. The binary function is storing 272 bytes.

General properties

nb instructions	137
nb uops	138
loop length	630
used x86 registers	16
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	30

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.00 cycles
front end	23.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.80	9.00	13.00	13.00	17.50	9.00	7.60	17.50	17.50	17.50	7.60	13.00
cycles	7.80	9.00	13.00	13.00	17.50	9.00	7.60	17.50	17.50	17.50	7.60	13.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.00
Dispatch	17.50
Overall L1	23.00

Vectorization ratios

INT

all	33%
load	8%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
other	44%

all	50%
load	40%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	35%
load	17%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	46%

Vector efficiency ratios

INT

all	15%
load	11%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
other	17%

all	18%
load	17%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	15%
load	13%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.00 cycles. At this rate:

4% of peak load performance is reached (9.39 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (11.83 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 23.00 to 17.50 cycles (1.31x speedup).

ASM code

In the binary file, the address of the function is: 4227f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x118,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RCX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 422ef1 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x701>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xa0(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x60(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x58(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b7790,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x58(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 422f09 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x719>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R14,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EBX,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%R13),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R13),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R12),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R12),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R15),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R15),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $-0x2,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %RAX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RSI,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 422f2a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x73a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %R9D,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVD -0x48(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RBX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RDX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RDI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R11,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R8,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RCX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x78abb(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOVQ %XMM1,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM1,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,%RDI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XORPD %XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVDQA %XMM2,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSRLQ $0x20,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM2,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RSI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM3,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSRLQ $0x20,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM3,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
JMP 422b09 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x319>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x118,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
CMP %R13,-0x78(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 422f27 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x737>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b77b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x2c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x118,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD %R13,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PXOR %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD 0x77bba(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVSD 0x786e2(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSD 0x77b52(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSD 0x786da(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVAPD 0x786ba(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
JMP 422f9a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x7aa>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180-211
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.00 to 9.00 cycles (2.56x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

35% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

17% of SSE/AVX loads are used in vector version.
40% of SSE/AVX stores are used in vector version.
14% of SSE/AVX addition or subtraction instructions are used in vector version.
46% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 216 bytes. The binary function is storing 272 bytes.

General properties

nb instructions	137
nb uops	138
loop length	630
used x86 registers	16
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	30

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.00 cycles
front end	23.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.80	9.00	13.00	13.00	17.50	9.00	7.60	17.50	17.50	17.50	7.60	13.00
cycles	7.80	9.00	13.00	13.00	17.50	9.00	7.60	17.50	17.50	17.50	7.60	13.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.00
Dispatch	17.50
Overall L1	23.00

Vectorization ratios

INT

all	33%
load	8%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
other	44%

all	50%
load	40%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	35%
load	17%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	46%

Vector efficiency ratios

INT

all	15%
load	11%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
other	17%

all	18%
load	17%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	15%
load	13%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.00 cycles. At this rate:

4% of peak load performance is reached (9.39 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (11.83 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4227f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x118,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RCX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 422ef1 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x701>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xa0(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x60(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x58(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b7790,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x58(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 422f09 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x719>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R14,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EBX,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%R13),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R13),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R12),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R12),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R15),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R15),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $-0x2,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %RAX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RSI,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 422f2a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x73a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %R9D,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVD -0x48(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RBX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RDX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RDI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R11,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R8,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RCX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x78abb(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOVQ %XMM1,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM1,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,%RDI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
XORPD %XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVDQA %XMM2,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSRLQ $0x20,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM2,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RSI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM3,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSRLQ $0x20,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM3,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
JMP 422b09 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x319>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x118,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
CMP %R13,-0x78(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 422f27 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x737>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b77b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x2c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x118,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD %R13,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PXOR %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD 0x77bba(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVSD 0x786e2(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSD 0x77b52(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSD 0x786da(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVAPD 0x786ba(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
JMP 422f9a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x7aa>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	7.06	2.79
○Loop 164 - advec_mom.cpp:181-211 - exec	7.06	2.78
○Loop 163 - advec_mom.cpp:181-211 - exec	0.00	0.00

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Code clean check

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Vectorization

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Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code