OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .extracted.32]

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:54-59 [...]	Coverage (incl. loops): 0.94% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 54 - 59

--------------------------------------------------------------------------------

54: #pragma omp parallel for simd collapse(2)

55:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

56:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

57:           pre_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

58:           post_vol(i, j) = volume(i, j);

59:         }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x421070 PUSH	%RBP

0x421071 MOV	%RSP,%RBP

0x421074 PUSH	%R15

0x421076 PUSH	%R14

0x421078 PUSH	%R13

0x42107a PUSH	%R12

0x42107c PUSH	%RBX

0x42107d SUB	$0xa8,%RSP

0x421084 MOV	%RDX,%R13

0x421087 MOV	0x30(%RBP),%RAX

0x42108b MOV	0x20(%RBP),%RBX

0x42108f MOV	0x18(%RBP),%RDX

0x421093 MOV	0x10(%RBP),%R10

0x421097 MOVL	$0,-0x30(%RBP)

0x42109e TEST	%RAX,%RAX

0x4210a1 JS	4214ba

0x4210a7 MOV	%R9,%R14

0x4210aa MOV	%R8,%R15

0x4210ad MOV	%RCX,%R12

0x4210b0 MOV	(%RDI),%ESI

0x4210b2 MOVQ	$0,-0x58(%RBP)

0x4210ba MOV	%RAX,-0x50(%RBP)

0x4210be MOVQ	$0x1,-0x90(%RBP)

0x4210c9 SUB	$0x8,%RSP

0x4210cd LEA	-0x90(%RBP),%RAX

0x4210d4 LEA	-0x30(%RBP),%RCX

0x4210d8 LEA	-0x58(%RBP),%R8

0x4210dc MOV	%RDX,-0x40(%RBP)

0x4210e0 LEA	-0x50(%RBP),%R9

0x4210e4 MOV	$0x4b7670,%EDI

0x4210e9 MOV	%ESI,-0x2c(%RBP)

0x4210ec MOV	$0x22,%EDX

0x4210f1 PUSH	$0x1

0x4210f3 PUSH	$0x1

0x4210f5 PUSH	%RAX

0x4210f6 MOV	%R10,-0x38(%RBP)

0x4210fa CALL	4031f0 <__kmpc_for_static_init_8@plt>

0x4210ff MOV	-0x38(%RBP),%R11

0x421103 MOV	-0x40(%RBP),%R9

0x421107 ADD	$0x20,%RSP

0x42110b MOV	-0x58(%RBP),%RCX

0x42110f MOV	-0x50(%RBP),%RDX

0x421113 CMP	%RDX,%RCX

0x421116 JA	42149c

0x42111c MOV	%RDX,%RAX

0x42111f SUB	%R9D,%EBX

0x421122 MOV	(%R13),%RDX

0x421126 MOV	0x10(%R13),%R8

0x42112a MOV	(%R12),%RSI

0x42112e MOV	0x10(%R12),%R10

0x421133 MOV	(%R15),%RDI

0x421136 MOV	0x10(%R15),%R15

0x42113a MOV	(%R14),%R12

0x42113d MOV	0x10(%R14),%R14

0x421141 INC	%RAX

0x421144 MOV	%RAX,-0x88(%RBP)

0x42114b SUB	%RCX,%RAX

0x42114e MOV	$-0x2,%R13D

0x421154 AND	%RAX,%R13

0x421157 MOV	%RSI,-0x48(%RBP)

0x42115b MOV	%RDI,-0x80(%RBP)

0x42115f MOV	%R12,-0x78(%RBP)

0x421163 JE	4214cc

0x421169 MOV	%RAX,-0x60(%RBP)

0x42116d MOV	%RBX,-0x70(%RBP)

0x421171 MOVD	%EBX,%XMM0

0x421175 PSHUFD	$0x44,%XMM0,%XMM1

0x42117a MOVQ	%R11,%XMM0

0x42117f PSHUFD	$0x44,%XMM0,%XMM0

0x421184 MOVDQA	%XMM0,-0xc0(%RBP)

0x42118c MOVD	%R9D,%XMM0

0x421191 PSHUFD	$0x50,%XMM0,%XMM0

0x421196 MOVDQA	%XMM0,-0xb0(%RBP)

0x42119e MOV	%RDX,-0x68(%RBP)

0x4211a2 MOVQ	%RDX,%XMM0

0x4211a7 PSHUFD	$0x44,%XMM0,%XMM8

0x4211ad MOVQ	%RSI,%XMM0

0x4211b2 PSHUFD	$0x44,%XMM0,%XMM11

0x4211b8 MOVQ	%RDI,%XMM0

0x4211bd PSHUFD	$0x44,%XMM0,%XMM5

0x4211c2 MOVQ	%R12,%XMM0

0x4211c7 PSHUFD	$0x44,%XMM0,%XMM6

0x4211cc MOVQ	%RCX,%XMM0

0x4211d1 PSHUFD	$0x44,%XMM0,%XMM7

0x4211d6 PADDQ	0x7a252(%RIP),%XMM7

0x4211de XOR	%EDI,%EDI

0x4211e0 MOVQ	%XMM1,%R9

0x4211e5 MOVDQA	%XMM1,-0xd0(%RBP)

0x4211ed PSHUFD	$-0x12,%XMM1,%XMM0

0x4211f2 MOVQ	%XMM0,%R12

0x4211f7 MOVDQA	%XMM8,%XMM9

0x4211fc PSRLQ	$0x20,%XMM9

0x421202 MOVQ	%R8,%XMM1

0x421207 PSHUFD	$0x44,%XMM1,%XMM0

0x42120c MOVDQA	%XMM0,-0xa0(%RBP)

0x421214 MOVDQA	%XMM11,%XMM2

0x421219 PSRLQ	$0x20,%XMM2

0x42121e MOVQ	%R10,%XMM1

0x421223 PSHUFD	$0x44,%XMM1,%XMM12

0x421229 MOVDQA	%XMM5,%XMM13

0x42122e PSRLQ	$0x20,%XMM13

0x421234 NOPW	%CS:(%RAX,%RAX,1)

(158) 0x421240 MOVQ	%XMM7,%RAX

(158) 0x421245 XOR	%EDX,%EDX

(158) 0x421247 DIV	%R9

(158) 0x42124a MOVQ	%RAX,%XMM1

(158) 0x42124f PSHUFD	$-0x12,%XMM7,%XMM3

(158) 0x421254 MOVQ	%XMM3,%RAX

(158) 0x421259 XOR	%EDX,%EDX

(158) 0x42125b DIV	%R12

(158) 0x42125e MOVQ	%RAX,%XMM3

(158) 0x421263 PUNPCKLQDQ	%XMM3,%XMM1

(158) 0x421267 MOVDQA	%XMM1,%XMM15

(158) 0x42126c PADDQ	-0xc0(%RBP),%XMM15

(158) 0x421275 PMULUDQ	-0xd0(%RBP),%XMM1

(158) 0x42127d MOVDQA	%XMM7,%XMM3

(158) 0x421281 PSUBQ	%XMM1,%XMM3

(158) 0x421285 PSHUFD	$-0x18,%XMM3,%XMM14

(158) 0x42128b PADDD	-0xb0(%RBP),%XMM14

(158) 0x421294 PXOR	%XMM4,%XMM4

(158) 0x421298 PSHUFD	$-0x18,%XMM15,%XMM10

(158) 0x42129e PSLLQ	$0x20,%XMM15

(158) 0x4212a4 PCMPGTD	%XMM14,%XMM4

(158) 0x4212a9 PSRAD	$0x1f,%XMM15

(158) 0x4212af PSHUFD	$-0x13,%XMM15,%XMM1

(158) 0x4212b5 PUNPCKLDQ	%XMM1,%XMM10

(158) 0x4212ba MOVDQA	%XMM14,%XMM1

(158) 0x4212bf MOVDQA	%XMM8,%XMM3

(158) 0x4212c4 PMULUDQ	%XMM10,%XMM3

(158) 0x4212c9 MOVDQA	%XMM9,%XMM0

(158) 0x4212ce PUNPCKLDQ	%XMM4,%XMM1

(158) 0x4212d2 PSRLQ	$0x20,%XMM15

(158) 0x4212d8 MOVDQA	%XMM8,%XMM4

(158) 0x4212dd PMULUDQ	%XMM15,%XMM4

(158) 0x4212e2 PMULUDQ	%XMM10,%XMM0

(158) 0x4212e7 PADDQ	%XMM0,%XMM4

(158) 0x4212eb PADDQ	%XMM1,%XMM3

(158) 0x4212ef PSUBD	0x7a2c8(%RIP),%XMM14

(158) 0x4212f8 PSLLQ	$0x20,%XMM4

(158) 0x4212fd PXOR	%XMM0,%XMM0

(158) 0x421301 PCMPGTD	%XMM14,%XMM0

(158) 0x421306 PUNPCKLDQ	%XMM0,%XMM14

(158) 0x42130b PADDQ	%XMM4,%XMM3

(158) 0x42130f MOVDQA	%XMM2,%XMM0

(158) 0x421313 MOVDQA	%XMM11,%XMM4

(158) 0x421318 PMULUDQ	%XMM15,%XMM4

(158) 0x42131d PMULUDQ	%XMM10,%XMM0

(158) 0x421322 PADDQ	%XMM0,%XMM4

(158) 0x421326 MOVDQA	%XMM11,%XMM0

(158) 0x42132b PMULUDQ	%XMM10,%XMM0

(158) 0x421330 PSLLQ	$0x20,%XMM4

(158) 0x421335 PADDQ	%XMM0,%XMM4

(158) 0x421339 PSLLQ	$0x3,%XMM3

(158) 0x42133e PADDQ	-0xa0(%RBP),%XMM3

(158) 0x421346 MOVQ	%XMM3,%RAX

(158) 0x42134b PSHUFD	$-0x12,%XMM3,%XMM0

(158) 0x421350 PADDQ	%XMM4,%XMM14

(158) 0x421355 PSLLQ	$0x3,%XMM14

(158) 0x42135b MOVQ	%XMM0,%RDX

(158) 0x421360 PADDQ	%XMM12,%XMM14

(158) 0x421365 MOVQ	%XMM14,%RBX

(158) 0x42136a PSHUFD	$-0x12,%XMM14,%XMM0

(158) 0x421370 MOVQ	%XMM0,%R11

(158) 0x421375 PADDQ	%XMM1,%XMM4

(158) 0x421379 PSLLQ	$0x3,%XMM4

(158) 0x42137e MOVDQA	%XMM13,%XMM0

(158) 0x421383 PMULUDQ	%XMM10,%XMM0

(158) 0x421388 MOVDQA	%XMM5,%XMM14

(158) 0x42138d PMULUDQ	%XMM15,%XMM14

(158) 0x421392 PADDQ	%XMM0,%XMM14

(158) 0x421397 MOVSD	(%RBX),%XMM3

(158) 0x42139b PADDQ	%XMM12,%XMM4

(158) 0x4213a0 MOVQ	%XMM4,%RBX

(158) 0x4213a5 PSHUFD	$-0x12,%XMM4,%XMM0

(158) 0x4213aa MOVQ	%XMM0,%RSI

(158) 0x4213af MOVDQA	%XMM5,%XMM0

(158) 0x4213b3 PMULUDQ	%XMM10,%XMM0

(158) 0x4213b8 PADDQ	%XMM1,%XMM0

(158) 0x4213bc PSLLQ	$0x20,%XMM14

(158) 0x4213c2 PADDQ	%XMM14,%XMM0

(158) 0x4213c7 MOVSD	(%RAX),%XMM4

(158) 0x4213cb MOVHPD	(%R11),%XMM3

(158) 0x4213d0 MOVHPD	(%RDX),%XMM4

(158) 0x4213d4 PSLLQ	$0x3,%XMM0

(158) 0x4213d9 ADDPD	%XMM4,%XMM3

(158) 0x4213dd MOVQ	%R15,%XMM4

(158) 0x4213e2 PSHUFD	$0x44,%XMM4,%XMM4

(158) 0x4213e7 PADDQ	%XMM0,%XMM4

(158) 0x4213eb MOVSD	(%RBX),%XMM0

(158) 0x4213ef MOVHPD	(%RSI),%XMM0

(158) 0x4213f3 MOVQ	%XMM4,%RSI

(158) 0x4213f8 PSHUFD	$-0x12,%XMM4,%XMM4

(158) 0x4213fd MOVQ	%XMM4,%R11

(158) 0x421402 MOVDQA	%XMM6,%XMM4

(158) 0x421406 PMULUDQ	%XMM10,%XMM4

(158) 0x42140b SUBPD	%XMM0,%XMM3

(158) 0x42140f MOVDQA	%XMM6,%XMM0

(158) 0x421413 PSRLQ	$0x20,%XMM0

(158) 0x421418 PMULUDQ	%XMM10,%XMM0

(158) 0x42141d PMULUDQ	%XMM6,%XMM15

(158) 0x421422 PADDQ	%XMM0,%XMM15

(158) 0x421427 PADDQ	%XMM1,%XMM4

(158) 0x42142b MOVLPD	%XMM3,(%RSI)

(158) 0x42142f MOVHPD	%XMM3,(%R11)

(158) 0x421434 PSLLQ	$0x20,%XMM15

(158) 0x42143a PADDQ	%XMM15,%XMM4

(158) 0x42143f MOVQ	%R14,%XMM0

(158) 0x421444 PSLLQ	$0x3,%XMM4

(158) 0x421449 PSHUFD	$0x44,%XMM0,%XMM0

(158) 0x42144e PADDQ	%XMM4,%XMM0

(158) 0x421452 MOVQ	(%RAX),%XMM1

(158) 0x421456 MOVQ	%XMM0,%RAX

(158) 0x42145b PSHUFD	$-0x12,%XMM0,%XMM0

(158) 0x421460 MOVQ	%XMM0,%RSI

(158) 0x421465 MOVQ	(%RDX),%XMM0

(158) 0x421469 MOVQ	%XMM1,(%RAX)

(158) 0x42146d MOVQ	%XMM0,(%RSI)

(158) 0x421471 PADDQ	0x79fd7(%RIP),%XMM7

(158) 0x421479 ADD	$0x2,%RDI

(158) 0x42147d CMP	%R13,%RDI

(158) 0x421480 JB	421240

0x421486 CMP	%R13,-0x60(%RBP)

0x42148a MOV	-0x70(%RBP),%RBX

0x42148e MOV	-0x40(%RBP),%R9

0x421492 MOV	-0x38(%RBP),%R11

0x421496 MOV	-0x68(%RBP),%R12

0x42149a JNE	4214d1

0x42149c MOV	$0x4b7690,%EDI

0x4214a1 MOV	-0x2c(%RBP),%ESI

0x4214a4 ADD	$0xa8,%RSP

0x4214ab POP	%RBX

0x4214ac POP	%R12

0x4214ae POP	%R13

0x4214b0 POP	%R14

0x4214b2 POP	%R15

0x4214b4 POP	%RBP

0x4214b5 JMP	403050

0x4214ba ADD	$0xa8,%RSP

0x4214c1 POP	%RBX

0x4214c2 POP	%R12

0x4214c4 POP	%R13

0x4214c6 POP	%R14

0x4214c8 POP	%R15

0x4214ca POP	%RBP

0x4214cb RET

0x4214cc MOV	%RDX,%R12

0x4214cf JMP	421550

0x4214d1 ADD	%R13,%RCX

0x4214d4 JMP	421550

0x4214d6 NOPW	%CS:(%RAX,%RAX,1)

(157) 0x4214e0 MOV	%RCX,%RAX

(157) 0x4214e3 XOR	%EDX,%EDX

(157) 0x4214e5 DIV	%RBX

(157) 0x4214e8 MOV	-0x48(%RBP),%RDI

(157) 0x4214ec ADD	%R11D,%EAX

(157) 0x4214ef ADD	%R9D,%EDX

(157) 0x4214f2 MOVSXD	%EDX,%RDX

(157) 0x4214f5 CLTQ

(157) 0x4214f7 MOV	%R12,%RSI

(157) 0x4214fa IMUL	%RAX,%RSI

(157) 0x4214fe ADD	%RDX,%RSI

(157) 0x421501 IMUL	%RAX,%RDI

(157) 0x421505 ADD	%RDX,%RDI

(157) 0x421508 MOVSD	0x8(%R10,%RDI,8),%XMM0

(157) 0x42150f ADDSD	(%R8,%RSI,8),%XMM0

(157) 0x421515 SUBSD	(%R10,%RDI,8),%XMM0

(157) 0x42151b MOV	-0x80(%RBP),%RDI

(157) 0x42151f IMUL	%RAX,%RDI

(157) 0x421523 ADD	%RDX,%RDI

(157) 0x421526 MOVSD	%XMM0,(%R15,%RDI,8)

(157) 0x42152c MOVQ	(%R8,%RSI,8),%XMM0

(157) 0x421532 IMUL	-0x78(%RBP),%RAX

(157) 0x421537 ADD	%RDX,%RAX

(157) 0x42153a MOVQ	%XMM0,(%R14,%RAX,8)

(157) 0x421540 INC	%RCX

(157) 0x421543 CMP	%RCX,-0x88(%RBP)

(157) 0x42154a JE	42149c

(157) 0x421550 MOV	%RCX,%RAX

(157) 0x421553 SHR	$0x20,%RAX

(157) 0x421557 JNE	4214e0

(157) 0x421559 MOV	%ECX,%EAX

(157) 0x42155b XOR	%EDX,%EDX

(157) 0x42155d DIV	%EBX

(157) 0x42155f JMP	4214e8

0x421561 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_cell.cpp:54-59
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:54-59
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.17 to 10.50 cycles (2.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 22.17 to 2.31 cycles (9.60x speedup).

Details

30% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
22% of SSE/AVX stores are used in vector version.
14% of SSE/AVX addition or subtraction instructions are used in vector version.
51% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:54

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 192 bytes. The binary function is storing 168 bytes.

General properties

nb instructions	132
nb uops	133
loop length	569
used x86 registers	16
used mmx registers	0
used xmm registers	11
used ymm registers	0
used zmm registers	0
nb stack references	22

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.17 cycles
front end	22.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.30	10.50	12.33	12.33	14.00	10.50	8.30	14.00	14.00	14.00	8.40	12.33
cycles	8.30	10.50	12.33	12.33	14.00	10.50	8.30	14.00	14.00	14.00	8.40	12.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	22.17
Dispatch	14.00
Overall L1	22.17

Vectorization ratios

all	30%
load	5%
store	22%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	51%

Vector efficiency ratios

all	15%
load	12%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.17 cycles. At this rate:

4% of peak load performance is reached (8.66 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.58 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 22.17 to 14.00 cycles (1.58x speedup).

ASM code

In the binary file, the address of the function is: 421070

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xa8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 4214ba <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.32+0x44a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x90(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x58(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x50(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b7670,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %R10,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x58(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 42149c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.32+0x42c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R9D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%R13),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R13),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R12),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R12),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R15),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R15),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $-0x2,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %RAX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 4214cc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.32+0x45c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %EBX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R11,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVD %R9D,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %RDX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %RDX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RSI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RDI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R12,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RCX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x7a252(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ %XMM1,%R9	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM1,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,%R12	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R8,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM11,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R10,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM5,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R13,-0x60(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x70(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x68(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 4214d1 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.32+0x461>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b7690,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x2c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0xa8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0xa8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 421550 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.32+0x4e0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
ADD %R13,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 421550 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.32+0x4e0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_cell.cpp:54-59
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:54-59
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

30% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
22% of SSE/AVX stores are used in vector version.
14% of SSE/AVX addition or subtraction instructions are used in vector version.
51% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:54

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 192 bytes. The binary function is storing 168 bytes.

General properties

nb instructions	132
nb uops	133
loop length	569
used x86 registers	16
used mmx registers	0
used xmm registers	11
used ymm registers	0
used zmm registers	0
nb stack references	22

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.17 cycles
front end	22.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.30	10.50	12.33	12.33	14.00	10.50	8.30	14.00	14.00	14.00	8.40	12.33
cycles	8.30	10.50	12.33	12.33	14.00	10.50	8.30	14.00	14.00	14.00	8.40	12.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	22.17
Dispatch	14.00
Overall L1	22.17

Vectorization ratios

all	30%
load	5%
store	22%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	51%

Vector efficiency ratios

all	15%
load	12%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.17 cycles. At this rate:

4% of peak load performance is reached (8.66 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.58 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 421070

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xa8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 4214ba <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.32+0x44a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x90(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x58(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x50(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b7670,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %R10,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x58(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 42149c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.32+0x42c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R9D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%R13),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R13),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R12),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R12),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R15),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R15),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $-0x2,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %RAX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 4214cc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.32+0x45c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %EBX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R11,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVD %R9D,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %RDX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %RDX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RSI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RDI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R12,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RCX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x7a252(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ %XMM1,%R9	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM1,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,%R12	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOVDQA %XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R8,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM11,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R10,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM5,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R13,-0x60(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x70(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x68(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 4214d1 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.32+0x461>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b7690,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x2c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0xa8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0xa8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 421550 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.32+0x4e0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
ADD %R13,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 421550 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.32+0x4e0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	0.94	0.37
○Loop 158 - advec_cell.cpp:55-59 - exec	0.94	0.37
○Loop 157 - advec_cell.cpp:55-59 - exec	0.00	0.00

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

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Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code