OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .extracted.22]

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:117-126 [...]	Coverage (incl. loops): 2.66% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 117 - 126

--------------------------------------------------------------------------------

117: #pragma omp parallel for simd collapse(2)

118:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

119:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

120:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

121:         double post_mass_s = pre_mass_s + mass_flux_x(i, j) - mass_flux_x(i + 1, j + 0);

122:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 1, j + 0)) / post_mass_s;

123:         double advec_vol_s = pre_vol(i, j) + vol_flux_x(i, j) - vol_flux_x(i + 1, j + 0);

124:         density1(i, j) = post_mass_s / advec_vol_s;

125:         energy1(i, j) = post_ener_s;

126:       }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41fbb0 PUSH	%RBP

0x41fbb1 MOV	%RSP,%RBP

0x41fbb4 PUSH	%R15

0x41fbb6 PUSH	%R14

0x41fbb8 PUSH	%R13

0x41fbba PUSH	%R12

0x41fbbc PUSH	%RBX

0x41fbbd SUB	$0x138,%RSP

0x41fbc4 MOV	0x40(%RBP),%RAX

0x41fbc8 MOV	0x30(%RBP),%R10

0x41fbcc MOV	0x28(%RBP),%R11

0x41fbd0 MOV	0x20(%RBP),%R15

0x41fbd4 MOV	0x18(%RBP),%RBX

0x41fbd8 MOV	0x10(%RBP),%R14

0x41fbdc MOVL	$0,-0x58(%RBP)

0x41fbe3 TEST	%RAX,%RAX

0x41fbe6 JS	420204

0x41fbec MOV	%R8,%R12

0x41fbef MOV	%RDX,%R13

0x41fbf2 MOV	%RCX,-0x38(%RBP)

0x41fbf6 MOV	%R9,-0x30(%RBP)

0x41fbfa MOV	(%RDI),%ESI

0x41fbfc MOVQ	$0,-0x80(%RBP)

0x41fc04 MOV	%RAX,-0x78(%RBP)

0x41fc08 MOVQ	$0x1,-0xe8(%RBP)

0x41fc13 SUB	$0x8,%RSP

0x41fc17 LEA	-0xe8(%RBP),%RAX

0x41fc1e LEA	-0x58(%RBP),%RCX

0x41fc22 LEA	-0x80(%RBP),%R8

0x41fc26 LEA	-0x78(%RBP),%R9

0x41fc2a MOV	$0x4b75b0,%EDI

0x41fc2f MOV	%ESI,-0x54(%RBP)

0x41fc32 MOV	$0x22,%EDX

0x41fc37 PUSH	$0x1

0x41fc39 PUSH	$0x1

0x41fc3b PUSH	%RAX

0x41fc3c MOV	%R15,-0x68(%RBP)

0x41fc40 MOV	%R10,%R15

0x41fc43 MOV	%R11,-0x48(%RBP)

0x41fc47 CALL	4031f0 <__kmpc_for_static_init_8@plt>

0x41fc4c ADD	$0x20,%RSP

0x41fc50 MOV	-0x80(%RBP),%RCX

0x41fc54 MOV	-0x78(%RBP),%RDX

0x41fc58 CMP	%RDX,%RCX

0x41fc5b JA	4201e6

0x41fc61 MOV	%R15,%R10

0x41fc64 MOV	%RDX,%RAX

0x41fc67 MOV	-0x48(%RBP),%RDI

0x41fc6b SUB	%EDI,%R10D

0x41fc6e MOV	(%R13),%RDX

0x41fc72 MOV	0x10(%R13),%R13

0x41fc76 MOV	(%R14),%RSI

0x41fc79 MOV	0x10(%R14),%R8

0x41fc7d MOV	%R8,-0x40(%RBP)

0x41fc81 MOV	(%R12),%R8

0x41fc85 MOV	0x10(%R12),%R9

0x41fc8a MOV	%R9,-0x50(%RBP)

0x41fc8e MOV	-0x38(%RBP),%R11

0x41fc92 MOV	(%R11),%R9

0x41fc95 MOV	0x10(%R11),%R14

0x41fc99 MOV	(%RBX),%R15

0x41fc9c MOV	0x10(%RBX),%RBX

0x41fca0 MOV	-0x30(%RBP),%R12

0x41fca4 MOV	(%R12),%R11

0x41fca8 MOV	0x10(%R12),%R12

0x41fcad MOV	%R12,-0x30(%RBP)

0x41fcb1 INC	%RAX

0x41fcb4 MOV	%RAX,-0xe0(%RBP)

0x41fcbb MOV	%RAX,%R12

0x41fcbe SUB	%RCX,%R12

0x41fcc1 MOV	$-0x2,%EAX

0x41fcc6 AND	%R12,%RAX

0x41fcc9 MOV	%R8,-0x60(%RBP)

0x41fccd MOV	%R14,-0x38(%RBP)

0x41fcd1 MOV	%RBX,-0x70(%RBP)

0x41fcd5 MOV	%R9,-0xd8(%RBP)

0x41fcdc MOV	%R15,-0xd0(%RBP)

0x41fce3 MOV	%R11,-0xc8(%RBP)

0x41fcea JE	420216

0x41fcf0 MOV	%R12,-0x88(%RBP)

0x41fcf7 MOV	%R10,-0xa8(%RBP)

0x41fcfe MOVD	%R10D,%XMM0

0x41fd03 PSHUFD	$0x44,%XMM0,%XMM1

0x41fd08 MOVQ	-0x68(%RBP),%XMM0

0x41fd0d PSHUFD	$0x44,%XMM0,%XMM0

0x41fd12 MOVDQA	%XMM0,-0x150(%RBP)

0x41fd1a MOVD	%EDI,%XMM0

0x41fd1e PSHUFD	$0x50,%XMM0,%XMM0

0x41fd23 MOVDQA	%XMM0,-0x140(%RBP)

0x41fd2b MOV	%RDX,-0xa0(%RBP)

0x41fd32 MOVQ	%RDX,%XMM0

0x41fd37 PSHUFD	$0x44,%XMM0,%XMM2

0x41fd3c MOV	%RSI,-0x90(%RBP)

0x41fd43 MOVQ	%RSI,%XMM0

0x41fd48 PSHUFD	$0x44,%XMM0,%XMM3

0x41fd4d MOVQ	%R8,%XMM0

0x41fd52 PSHUFD	$0x44,%XMM0,%XMM13

0x41fd58 MOVQ	%R9,%XMM0

0x41fd5d PSHUFD	$0x44,%XMM0,%XMM6

0x41fd62 MOVQ	%R15,%XMM0

0x41fd67 PSHUFD	$0x44,%XMM0,%XMM10

0x41fd6d MOVQ	%R11,%XMM0

0x41fd72 PSHUFD	$0x44,%XMM0,%XMM8

0x41fd78 MOVQ	%RCX,%XMM0

0x41fd7d PSHUFD	$0x44,%XMM0,%XMM9

0x41fd83 PADDQ	0x7b6a4(%RIP),%XMM9

0x41fd8c XOR	%R9D,%R9D

0x41fd8f MOVQ	%XMM1,-0xb8(%RBP)

0x41fd97 MOVDQA	%XMM1,-0x160(%RBP)

0x41fd9f PSHUFD	$-0x12,%XMM1,%XMM0

0x41fda4 MOVQ	%XMM0,-0xb0(%RBP)

0x41fdac MOVDQA	%XMM2,-0x130(%RBP)

0x41fdb4 PSRLQ	$0x20,%XMM2

0x41fdb9 MOVDQA	%XMM2,-0x120(%RBP)

0x41fdc1 MOV	%R13,-0x98(%RBP)

0x41fdc8 MOVQ	%R13,%XMM0

0x41fdcd PSHUFD	$0x44,%XMM0,%XMM0

0x41fdd2 MOVDQA	%XMM0,-0x110(%RBP)

0x41fdda MOVDQA	%XMM3,%XMM0

0x41fdde PSRLQ	$0x20,%XMM0

0x41fde3 MOVQ	-0x40(%RBP),%XMM1

0x41fde8 PSHUFD	$0x44,%XMM1,%XMM1

0x41fded MOVDQA	%XMM1,-0x100(%RBP)

0x41fdf5 MOV	%RAX,-0xc0(%RBP)

0x41fdfc NOPL	(%RAX)

(154) 0x41fe00 MOVQ	%XMM9,%RAX

(154) 0x41fe05 XOR	%EDX,%EDX

(154) 0x41fe07 DIVQ	-0xb8(%RBP)

(154) 0x41fe0e PSHUFD	$-0x12,%XMM9,%XMM1

(154) 0x41fe14 MOVQ	%XMM1,%RDX

(154) 0x41fe19 MOVQ	%RAX,%XMM1

(154) 0x41fe1e MOV	%RDX,%RAX

(154) 0x41fe21 XOR	%EDX,%EDX

(154) 0x41fe23 DIVQ	-0xb0(%RBP)

(154) 0x41fe2a MOVQ	%RAX,%XMM2

(154) 0x41fe2f PUNPCKLQDQ	%XMM2,%XMM1

(154) 0x41fe33 MOVDQA	%XMM1,%XMM14

(154) 0x41fe38 PADDQ	-0x150(%RBP),%XMM14

(154) 0x41fe41 PMULUDQ	-0x160(%RBP),%XMM1

(154) 0x41fe49 MOVDQA	%XMM9,%XMM2

(154) 0x41fe4e PSUBQ	%XMM1,%XMM2

(154) 0x41fe52 PSHUFD	$-0x18,%XMM2,%XMM1

(154) 0x41fe57 PXOR	%XMM4,%XMM4

(154) 0x41fe5b PSHUFD	$-0x18,%XMM14,%XMM2

(154) 0x41fe61 PSLLQ	$0x20,%XMM14

(154) 0x41fe67 PADDD	-0x140(%RBP),%XMM1

(154) 0x41fe6f PSRAD	$0x1f,%XMM14

(154) 0x41fe75 PSHUFD	$-0x13,%XMM14,%XMM5

(154) 0x41fe7b PUNPCKLDQ	%XMM5,%XMM2

(154) 0x41fe7f PCMPGTD	%XMM1,%XMM4

(154) 0x41fe83 MOVDQA	-0x130(%RBP),%XMM7

(154) 0x41fe8b MOVDQA	%XMM7,%XMM11

(154) 0x41fe90 PMULUDQ	%XMM2,%XMM11

(154) 0x41fe95 MOVDQA	-0x120(%RBP),%XMM5

(154) 0x41fe9d MOVDQA	%XMM1,%XMM15

(154) 0x41fea2 PMULUDQ	%XMM2,%XMM5

(154) 0x41fea6 PSRLQ	$0x20,%XMM14

(154) 0x41feac PUNPCKLDQ	%XMM4,%XMM15

(154) 0x41feb1 PMULUDQ	%XMM14,%XMM7

(154) 0x41feb6 PADDQ	%XMM5,%XMM7

(154) 0x41feba MOVDQA	%XMM3,%XMM4

(154) 0x41febe PADDQ	%XMM15,%XMM11

(154) 0x41fec3 PMULUDQ	%XMM2,%XMM4

(154) 0x41fec7 MOVDQA	%XMM0,%XMM5

(154) 0x41fecb PMULUDQ	%XMM2,%XMM5

(154) 0x41fecf PSLLQ	$0x20,%XMM7

(154) 0x41fed4 MOVDQA	%XMM3,%XMM12

(154) 0x41fed9 PMULUDQ	%XMM14,%XMM12

(154) 0x41fede PADDQ	%XMM5,%XMM12

(154) 0x41fee3 PADDQ	%XMM7,%XMM11

(154) 0x41fee8 PSLLQ	$0x20,%XMM12

(154) 0x41feee PADDQ	%XMM15,%XMM4

(154) 0x41fef3 PADDQ	%XMM12,%XMM4

(154) 0x41fef8 PSLLQ	$0x3,%XMM11

(154) 0x41fefe MOVDQA	%XMM13,%XMM7

(154) 0x41ff03 PMULUDQ	%XMM2,%XMM7

(154) 0x41ff07 MOVDQA	%XMM13,%XMM12

(154) 0x41ff0c PSLLQ	$0x3,%XMM4

(154) 0x41ff11 PSRLQ	$0x20,%XMM12

(154) 0x41ff17 PMULUDQ	%XMM2,%XMM12

(154) 0x41ff1c MOVDQA	%XMM13,%XMM5

(154) 0x41ff21 PADDQ	-0x110(%RBP),%XMM11

(154) 0x41ff2a PMULUDQ	%XMM14,%XMM5

(154) 0x41ff2f PADDQ	%XMM12,%XMM5

(154) 0x41ff34 PSLLQ	$0x20,%XMM5

(154) 0x41ff39 MOVQ	%XMM11,%RAX

(154) 0x41ff3e PADDQ	%XMM7,%XMM5

(154) 0x41ff42 PSUBD	0x7b676(%RIP),%XMM1

(154) 0x41ff4a PXOR	%XMM7,%XMM7

(154) 0x41ff4e PSHUFD	$-0x12,%XMM11,%XMM11

(154) 0x41ff54 PCMPGTD	%XMM1,%XMM7

(154) 0x41ff58 PUNPCKLDQ	%XMM7,%XMM1

(154) 0x41ff5c MOVDQA	%XMM6,%XMM7

(154) 0x41ff60 MOVQ	%XMM11,%RDX

(154) 0x41ff65 PSRLQ	$0x20,%XMM7

(154) 0x41ff6a PMULUDQ	%XMM2,%XMM7

(154) 0x41ff6e MOVDQA	%XMM6,%XMM12

(154) 0x41ff73 MOVDQA	%XMM5,%XMM11

(154) 0x41ff78 PMULUDQ	%XMM14,%XMM12

(154) 0x41ff7d PADDQ	%XMM7,%XMM12

(154) 0x41ff82 MOVDQA	%XMM6,%XMM7

(154) 0x41ff86 PADDQ	-0x100(%RBP),%XMM4

(154) 0x41ff8e PMULUDQ	%XMM2,%XMM7

(154) 0x41ff92 PSLLQ	$0x20,%XMM12

(154) 0x41ff98 PADDQ	%XMM15,%XMM7

(154) 0x41ff9d PADDQ	%XMM15,%XMM11

(154) 0x41ffa2 PADDQ	%XMM12,%XMM7

(154) 0x41ffa7 PSLLQ	$0x3,%XMM7

(154) 0x41ffac MOVQ	-0x38(%RBP),%XMM12

(154) 0x41ffb2 MOVQ	%XMM4,%R10

(154) 0x41ffb7 PSHUFD	$0x44,%XMM12,%XMM12

(154) 0x41ffbd PADDQ	%XMM7,%XMM12

(154) 0x41ffc2 MOVQ	-0x50(%RBP),%XMM7

(154) 0x41ffc7 PSHUFD	$-0x12,%XMM4,%XMM4

(154) 0x41ffcc PSHUFD	$0x44,%XMM7,%XMM7

(154) 0x41ffd1 PADDQ	%XMM1,%XMM5

(154) 0x41ffd5 PSLLQ	$0x3,%XMM5

(154) 0x41ffda PSLLQ	$0x3,%XMM11

(154) 0x41ffe0 PADDQ	%XMM7,%XMM5

(154) 0x41ffe4 MOVQ	%XMM12,%RBX

(154) 0x41ffe9 PSHUFD	$-0x12,%XMM12,%XMM12

(154) 0x41ffef MOVQ	%XMM4,%R11

(154) 0x41fff4 MOVDQA	%XMM10,%XMM4

(154) 0x41fff9 PSRLQ	$0x20,%XMM4

(154) 0x41fffe PMULUDQ	%XMM2,%XMM4

(154) 0x420002 PADDQ	%XMM7,%XMM11

(154) 0x420007 MOVDQA	%XMM10,%XMM7

(154) 0x42000c PMULUDQ	%XMM14,%XMM7

(154) 0x420011 PADDQ	%XMM4,%XMM7

(154) 0x420015 MOVQ	%XMM5,%R13

(154) 0x42001a MOVDQA	%XMM10,%XMM4

(154) 0x42001f PMULUDQ	%XMM2,%XMM4

(154) 0x420023 PSLLQ	$0x20,%XMM7

(154) 0x420028 PSHUFD	$-0x12,%XMM5,%XMM5

(154) 0x42002d PADDQ	%XMM4,%XMM7

(154) 0x420031 MOVDQA	%XMM7,%XMM4

(154) 0x420035 PADDQ	%XMM15,%XMM4

(154) 0x42003a MOVQ	%XMM12,%RSI

(154) 0x42003f PSLLQ	$0x3,%XMM4

(154) 0x420044 MOVQ	-0x70(%RBP),%XMM12

(154) 0x42004a PSHUFD	$0x44,%XMM12,%XMM12

(154) 0x420050 PADDQ	%XMM12,%XMM4

(154) 0x420055 PADDQ	%XMM1,%XMM7

(154) 0x420059 PSLLQ	$0x3,%XMM7

(154) 0x42005e PADDQ	%XMM12,%XMM7

(154) 0x420063 MOVQ	%XMM5,%R8

(154) 0x420068 MOVDQA	%XMM8,%XMM5

(154) 0x42006d MOVDQA	%XMM8,%XMM12

(154) 0x420072 PSRLQ	$0x20,%XMM12

(154) 0x420078 PMULUDQ	%XMM2,%XMM5

(154) 0x42007c PMULUDQ	%XMM2,%XMM12

(154) 0x420081 PMULUDQ	%XMM8,%XMM14

(154) 0x420086 PADDQ	%XMM12,%XMM14

(154) 0x42008b PSLLQ	$0x20,%XMM14

(154) 0x420091 PADDQ	%XMM5,%XMM14

(154) 0x420096 MOVQ	%XMM7,%R12

(154) 0x42009b PSHUFD	$-0x12,%XMM7,%XMM2

(154) 0x4200a0 MOVQ	%XMM2,%R15

(154) 0x4200a5 MOVSD	(%R10),%XMM5

(154) 0x4200aa MOVHPD	(%R11),%XMM5

(154) 0x4200af MOVQ	%XMM11,%R10

(154) 0x4200b4 PSHUFD	$-0x12,%XMM11,%XMM2

(154) 0x4200ba PADDQ	%XMM14,%XMM15

(154) 0x4200bf PSLLQ	$0x3,%XMM15

(154) 0x4200c5 MOVQ	%XMM2,%R11

(154) 0x4200ca MOVQ	-0x30(%RBP),%XMM2

(154) 0x4200cf PSHUFD	$0x44,%XMM2,%XMM7

(154) 0x4200d4 PADDQ	%XMM7,%XMM15

(154) 0x4200d9 MOVQ	%XMM15,%RDI

(154) 0x4200de PSHUFD	$-0x12,%XMM15,%XMM2

(154) 0x4200e4 MOVQ	%XMM2,%R14

(154) 0x4200e9 MOVSD	(%RDI),%XMM2

(154) 0x4200ed MOVQ	%XMM4,%RDI

(154) 0x4200f2 PSHUFD	$-0x12,%XMM4,%XMM4

(154) 0x4200f7 MOVHPD	(%R14),%XMM2

(154) 0x4200fc MOVQ	%XMM4,%R14

(154) 0x420101 MOVSD	(%RAX),%XMM11

(154) 0x420106 MOVHPD	(%RDX),%XMM11

(154) 0x42010b MULPD	%XMM5,%XMM11

(154) 0x420110 ADDPD	%XMM5,%XMM2

(154) 0x420114 MOVSD	(%R10),%XMM4

(154) 0x420119 MOVHPD	(%R11),%XMM4

(154) 0x42011e PADDQ	%XMM1,%XMM14

(154) 0x420123 PSLLQ	$0x3,%XMM14

(154) 0x420129 PADDQ	%XMM7,%XMM14

(154) 0x42012e ADDPD	%XMM11,%XMM4

(154) 0x420133 MOVSD	(%RBX),%XMM1

(154) 0x420137 MOVHPD	(%RSI),%XMM1

(154) 0x42013b MULPD	%XMM11,%XMM1

(154) 0x420140 MOVSD	(%R13),%XMM5

(154) 0x420146 MOVHPD	(%R8),%XMM5

(154) 0x42014b SUBPD	%XMM5,%XMM4

(154) 0x42014f MOVSD	(%RDI),%XMM5

(154) 0x420153 MOVHPD	(%R14),%XMM5

(154) 0x420158 ADDPD	%XMM1,%XMM5

(154) 0x42015c MOVSD	(%R12),%XMM1

(154) 0x420162 MOVHPD	(%R15),%XMM1

(154) 0x420167 SUBPD	%XMM1,%XMM5

(154) 0x42016b MOVQ	%XMM14,%RDI

(154) 0x420170 PSHUFD	$-0x12,%XMM14,%XMM1

(154) 0x420176 MOVQ	%XMM1,%R8

(154) 0x42017b MOVSD	(%RDI),%XMM1

(154) 0x42017f MOVHPD	(%R8),%XMM1

(154) 0x420184 SUBPD	%XMM1,%XMM2

(154) 0x420188 DIVPD	%XMM4,%XMM5

(154) 0x42018c DIVPD	%XMM2,%XMM4

(154) 0x420190 MOVLPD	%XMM4,(%RAX)

(154) 0x420194 MOV	-0xc0(%RBP),%RAX

(154) 0x42019b MOVHPD	%XMM4,(%RDX)

(154) 0x42019f MOVLPD	%XMM5,(%RBX)

(154) 0x4201a3 MOVHPD	%XMM5,(%RSI)

(154) 0x4201a7 PADDQ	0x7b2a0(%RIP),%XMM9

(154) 0x4201b0 ADD	$0x2,%R9

(154) 0x4201b4 CMP	%RAX,%R9

(154) 0x4201b7 JB	41fe00

0x4201bd CMP	%RAX,-0x88(%RBP)

0x4201c4 MOV	-0xa8(%RBP),%R10

0x4201cb MOV	-0xa0(%RBP),%RBX

0x4201d2 MOV	-0x98(%RBP),%R13

0x4201d9 MOV	-0x90(%RBP),%R14

0x4201e0 MOV	-0x40(%RBP),%R12

0x4201e4 JNE	420225

0x4201e6 MOV	$0x4b75d0,%EDI

0x4201eb MOV	-0x54(%RBP),%ESI

0x4201ee ADD	$0x138,%RSP

0x4201f5 POP	%RBX

0x4201f6 POP	%R12

0x4201f8 POP	%R13

0x4201fa POP	%R14

0x4201fc POP	%R15

0x4201fe POP	%RBP

0x4201ff JMP	403050

0x420204 ADD	$0x138,%RSP

0x42020b POP	%RBX

0x42020c POP	%R12

0x42020e POP	%R13

0x420210 POP	%R14

0x420212 POP	%R15

0x420214 POP	%RBP

0x420215 RET

0x420216 MOV	%RDX,%RBX

0x420219 MOV	%RSI,%R14

0x42021c MOV	-0x40(%RBP),%R12

0x420220 JMP	420319

0x420225 ADD	%RAX,%RCX

0x420228 JMP	420319

0x42022d NOPL	(%RAX)

(153) 0x420230 MOV	%RCX,%RAX

(153) 0x420233 XOR	%EDX,%EDX

(153) 0x420235 DIV	%R10

(153) 0x420238 MOV	-0x60(%RBP),%R8

(153) 0x42023c MOV	-0x50(%RBP),%R9

(153) 0x420240 MOV	-0x48(%RBP),%RSI

(153) 0x420244 ADD	-0x68(%RBP),%EAX

(153) 0x420247 ADD	%ESI,%EDX

(153) 0x420249 MOVSXD	%EDX,%RDX

(153) 0x42024c MOVSXD	%EAX,%RSI

(153) 0x42024f MOV	%RBX,%RAX

(153) 0x420252 IMUL	%RSI,%RAX

(153) 0x420256 ADD	%RDX,%RAX

(153) 0x420259 MOV	%R14,%RDI

(153) 0x42025c IMUL	%RSI,%RDI

(153) 0x420260 ADD	%RDX,%RDI

(153) 0x420263 MOVSD	(%R12,%RDI,8),%XMM1

(153) 0x420269 MOVSD	(%R13,%RAX,8),%XMM0

(153) 0x420270 MULSD	%XMM1,%XMM0

(153) 0x420274 MOV	%R8,%RDI

(153) 0x420277 IMUL	%RSI,%RDI

(153) 0x42027b LEA	(%RDI,%RDX,1),%R8

(153) 0x42027f MOVSD	(%R9,%R8,8),%XMM2

(153) 0x420285 ADDSD	%XMM0,%XMM2

(153) 0x420289 ADD	%RDX,%RDI

(153) 0x42028c INC	%RDI

(153) 0x42028f SUBSD	(%R9,%RDI,8),%XMM2

(153) 0x420295 MOV	-0xd8(%RBP),%RDI

(153) 0x42029c IMUL	%RSI,%RDI

(153) 0x4202a0 ADD	%RDX,%RDI

(153) 0x4202a3 MOV	-0x38(%RBP),%R15

(153) 0x4202a7 MULSD	(%R15,%RDI,8),%XMM0

(153) 0x4202ad MOV	-0xd0(%RBP),%R8

(153) 0x4202b4 IMUL	%RSI,%R8

(153) 0x4202b8 LEA	(%R8,%RDX,1),%R9

(153) 0x4202bc MOV	-0x70(%RBP),%R11

(153) 0x4202c0 ADDSD	(%R11,%R9,8),%XMM0

(153) 0x4202c6 ADD	%RDX,%R8

(153) 0x4202c9 INC	%R8

(153) 0x4202cc SUBSD	(%R11,%R8,8),%XMM0

(153) 0x4202d2 IMUL	-0xc8(%RBP),%RSI

(153) 0x4202da LEA	(%RSI,%RDX,1),%R8

(153) 0x4202de MOV	-0x30(%RBP),%R9

(153) 0x4202e2 ADDSD	(%R9,%R8,8),%XMM1

(153) 0x4202e8 ADD	%RSI,%RDX

(153) 0x4202eb INC	%RDX

(153) 0x4202ee SUBSD	(%R9,%RDX,8),%XMM1

(153) 0x4202f4 DIVSD	%XMM2,%XMM0

(153) 0x4202f8 DIVSD	%XMM1,%XMM2

(153) 0x4202fc MOVSD	%XMM2,(%R13,%RAX,8)

(153) 0x420303 MOVSD	%XMM0,(%R15,%RDI,8)

(153) 0x420309 INC	%RCX

(153) 0x42030c CMP	%RCX,-0xe0(%RBP)

(153) 0x420313 JE	4201e6

(153) 0x420319 MOV	%RCX,%RAX

(153) 0x42031c SHR	$0x20,%RAX

(153) 0x420320 JNE	420230

(153) 0x420326 MOV	%ECX,%EAX

(153) 0x420328 XOR	%EDX,%EDX

(153) 0x42032a DIV	%R10D

(153) 0x42032d JMP	420238

0x420332 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►99.99+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_cell.cpp:117-126
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117-126
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 26.50 to 11.50 cycles (2.30x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 26.50 to 2.84 cycles (9.33x speedup).

Details

26% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
20% of SSE/AVX stores are used in vector version.
14% of SSE/AVX addition or subtraction instructions are used in vector version.
48% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 280 bytes. The binary function is storing 320 bytes.

General properties

nb instructions	158
nb uops	159
loop length	721
used x86 registers	16
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	38

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	26.50 cycles
front end	26.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.30	11.50	16.00	16.00	22.00	11.50	7.30	22.00	22.00	22.00	7.40	16.00
cycles	7.30	11.50	16.00	16.00	22.00	11.50	7.30	22.00	22.00	22.00	7.40	16.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	26.50
Dispatch	22.00
Overall L1	26.50

Vectorization ratios

all	26%
load	5%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	48%

Vector efficiency ratios

all	15%
load	12%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 26.50 cycles. At this rate:

5% of peak load performance is reached (10.57 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (12.08 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 26.50 to 22.00 cycles (1.20x speedup).

ASM code

In the binary file, the address of the function is: 41fbb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x138,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x28(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVL $0,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 420204 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x654>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xe8(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x58(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x80(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x78(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b75b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x54(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %R15,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R11,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x80(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x78(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 4201e6 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x636>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x48(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EDI,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%R13),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R13),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R8,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%R12),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R11),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R11),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R12),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R12),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R12,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RCX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $-0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %R12,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R8,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 420216 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x666>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R12,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %R10D,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ -0x68(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x150(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVD %EDI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %RDX,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %RDX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOV %RSI,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %RSI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R8,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R9,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R15,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R11,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RCX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x7b6a4(%RIP),%XMM9	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOVQ %XMM1,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM1,-0x160(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM2,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSRLQ $0x20,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM2,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %R13,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %R13,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ -0x40(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM1,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %RAX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RAX,-0x88(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0xa8(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xa0(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x98(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x90(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x40(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 420225 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x675>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b75d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x54(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x138,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0x138,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x40(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 420319 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x769>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 420319 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x769>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_cell.cpp:117-126
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117-126
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

26% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
20% of SSE/AVX stores are used in vector version.
14% of SSE/AVX addition or subtraction instructions are used in vector version.
48% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 280 bytes. The binary function is storing 320 bytes.

General properties

nb instructions	158
nb uops	159
loop length	721
used x86 registers	16
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	38

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	26.50 cycles
front end	26.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.30	11.50	16.00	16.00	22.00	11.50	7.30	22.00	22.00	22.00	7.40	16.00
cycles	7.30	11.50	16.00	16.00	22.00	11.50	7.30	22.00	22.00	22.00	7.40	16.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	26.50
Dispatch	22.00
Overall L1	26.50

Vectorization ratios

all	26%
load	5%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	48%

Vector efficiency ratios

all	15%
load	12%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 26.50 cycles. At this rate:

5% of peak load performance is reached (10.57 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (12.08 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 41fbb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x138,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x28(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVL $0,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 420204 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x654>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xe8(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x58(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x80(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x78(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b75b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x54(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %R15,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R11,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x80(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x78(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 4201e6 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x636>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x48(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EDI,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%R13),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R13),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R8,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%R12),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R11),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R11),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R12),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R12),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R12,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RCX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $-0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %R12,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R8,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 420216 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x666>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R12,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %R10D,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ -0x68(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x150(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVD %EDI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %RDX,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %RDX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOV %RSI,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %RSI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R8,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R9,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R15,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R11,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RCX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x7b6a4(%RIP),%XMM9	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOVQ %XMM1,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM1,-0x160(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM2,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSRLQ $0x20,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM2,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %R13,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %R13,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ -0x40(%RBP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM1,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %RAX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RAX,-0x88(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0xa8(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xa0(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x98(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x90(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x40(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 420225 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x675>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b75d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x54(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x138,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0x138,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x40(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 420319 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x769>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 420319 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.22+0x769>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	2.66	1.05
○Loop 154 - advec_cell.cpp:118-126 - exec	2.66	1.05
○Loop 153 - advec_cell.cpp:118-126 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code