OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .extracted.17]

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:136-141 [...]	Coverage (incl. loops): 1.19% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 136 - 141

--------------------------------------------------------------------------------

136: #pragma omp parallel for simd collapse(2)

137:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

138:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

139:           pre_vol(i, j) = volume(i, j) + (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j));

140:           post_vol(i, j) = pre_vol(i, j) - (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j));

141:         }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41f510 PUSH	%RBP

0x41f511 MOV	%RSP,%RBP

0x41f514 PUSH	%R15

0x41f516 PUSH	%R14

0x41f518 PUSH	%R13

0x41f51a PUSH	%R12

0x41f51c PUSH	%RBX

0x41f51d SUB	$0x118,%RSP

0x41f524 MOV	%RCX,%R15

0x41f527 MOV	%RDX,%R13

0x41f52a MOV	0x38(%RBP),%RAX

0x41f52e MOV	0x28(%RBP),%RCX

0x41f532 MOV	0x20(%RBP),%RDX

0x41f536 MOV	0x10(%RBP),%R12

0x41f53a MOV	0x18(%RBP),%EBX

0x41f53d MOVL	$0,-0x40(%RBP)

0x41f544 TEST	%RAX,%RAX

0x41f547 JS	41faac

0x41f54d MOV	%R8,%R14

0x41f550 MOV	%R9,-0x38(%RBP)

0x41f554 MOV	%RDX,-0x48(%RBP)

0x41f558 MOV	%RCX,-0x30(%RBP)

0x41f55c MOV	(%RDI),%ESI

0x41f55e MOVQ	$0,-0x60(%RBP)

0x41f566 MOV	%RAX,-0x58(%RBP)

0x41f56a MOVQ	$0x1,-0xb0(%RBP)

0x41f575 SUB	$0x8,%RSP

0x41f579 LEA	-0xb0(%RBP),%RAX

0x41f580 LEA	-0x40(%RBP),%RCX

0x41f584 LEA	-0x60(%RBP),%R8

0x41f588 LEA	-0x58(%RBP),%R9

0x41f58c MOV	$0x4b7550,%EDI

0x41f591 MOV	%ESI,-0x3c(%RBP)

0x41f594 MOV	$0x22,%EDX

0x41f599 PUSH	$0x1

0x41f59b PUSH	$0x1

0x41f59d PUSH	%RAX

0x41f59e CALL	4031f0 <__kmpc_for_static_init_8@plt>

0x41f5a3 ADD	$0x20,%RSP

0x41f5a7 MOV	-0x60(%RBP),%RCX

0x41f5ab MOV	-0x58(%RBP),%RAX

0x41f5af CMP	%RAX,%RCX

0x41f5b2 JA	41fa8e

0x41f5b8 MOV	%RAX,%RSI

0x41f5bb MOV	-0x30(%RBP),%RAX

0x41f5bf MOV	-0x48(%RBP),%RDX

0x41f5c3 SUB	%EDX,%EAX

0x41f5c5 MOV	(%R13),%RDI

0x41f5c9 MOV	0x10(%R13),%R13

0x41f5cd MOV	(%R14),%R10

0x41f5d0 MOV	0x10(%R14),%R11

0x41f5d4 MOV	(%R15),%R9

0x41f5d7 MOV	0x10(%R15),%R15

0x41f5db MOV	-0x38(%RBP),%R8

0x41f5df MOV	(%R8),%R14

0x41f5e2 MOV	0x10(%R8),%R8

0x41f5e6 MOV	%R8,-0x38(%RBP)

0x41f5ea MOV	(%R12),%R8

0x41f5ee MOV	0x10(%R12),%R12

0x41f5f3 MOV	%R12,-0x50(%RBP)

0x41f5f7 INC	%RSI

0x41f5fa MOV	%RSI,-0xa8(%RBP)

0x41f601 MOV	%RSI,%R12

0x41f604 SUB	%RCX,%R12

0x41f607 MOV	$-0x2,%ESI

0x41f60c AND	%R12,%RSI

0x41f60f MOV	%R8,-0x98(%RBP)

0x41f616 MOV	%RAX,-0x30(%RBP)

0x41f61a MOV	%R14,-0xa0(%RBP)

0x41f621 JE	41fabe

0x41f627 MOV	%R12,-0x68(%RBP)

0x41f62b MOVD	%EAX,%XMM0

0x41f62f PSHUFD	$0x44,%XMM0,%XMM2

0x41f634 MOVD	%EBX,%XMM0

0x41f638 PSHUFD	$0x50,%XMM0,%XMM0

0x41f63d MOVDQA	%XMM0,-0x130(%RBP)

0x41f645 MOVD	%EDX,%XMM0

0x41f649 PSHUFD	$0x50,%XMM0,%XMM0

0x41f64e MOVDQA	%XMM0,-0x120(%RBP)

0x41f656 MOV	%RDI,-0x80(%RBP)

0x41f65a MOVQ	%RDI,%XMM0

0x41f65f PSHUFD	$0x44,%XMM0,%XMM3

0x41f664 MOVQ	%R10,%XMM0

0x41f669 PSHUFD	$0x44,%XMM0,%XMM13

0x41f66f MOV	%R9,-0x70(%RBP)

0x41f673 MOVQ	%R9,%XMM0

0x41f678 PSHUFD	$0x44,%XMM0,%XMM0

0x41f67d MOVDQA	%XMM0,-0xd0(%RBP)

0x41f685 MOVQ	%R14,%XMM0

0x41f68a PSHUFD	$0x44,%XMM0,%XMM6

0x41f68f MOVQ	%R8,%XMM0

0x41f694 MOVQ	%RCX,%XMM1

0x41f699 PSHUFD	$0x44,%XMM1,%XMM7

0x41f69e PADDQ	0x7bd8a(%RIP),%XMM7

0x41f6a6 PSHUFD	$0x44,%XMM0,%XMM8

0x41f6ac XOR	%R12D,%R12D

0x41f6af MOVQ	%XMM2,-0x90(%RBP)

0x41f6b7 MOVDQA	%XMM2,-0x140(%RBP)

0x41f6bf PSHUFD	$-0x12,%XMM2,%XMM0

0x41f6c4 MOVQ	%XMM0,-0x88(%RBP)

0x41f6cc MOVDQA	%XMM3,-0x110(%RBP)

0x41f6d4 PSRLQ	$0x20,%XMM3

0x41f6d9 MOVDQA	%XMM3,-0x100(%RBP)

0x41f6e1 MOV	%R13,-0x78(%RBP)

0x41f6e5 MOVQ	%R13,%XMM0

0x41f6ea PSHUFD	$0x44,%XMM0,%XMM0

0x41f6ef MOVDQA	%XMM0,-0xf0(%RBP)

0x41f6f7 MOVDQA	%XMM13,%XMM0

0x41f6fc PSRLQ	$0x20,%XMM0

0x41f701 MOVDQA	%XMM0,-0xe0(%RBP)

0x41f709 MOVQ	%R11,%XMM1

0x41f70e PSHUFD	$0x44,%XMM1,%XMM0

0x41f713 MOVDQA	%XMM0,-0xc0(%RBP)

0x41f71b NOPL	(%RAX,%RAX,1)

(152) 0x41f720 MOVQ	%XMM7,%RAX

(152) 0x41f725 XOR	%EDX,%EDX

(152) 0x41f727 DIVQ	-0x90(%RBP)

(152) 0x41f72e MOV	%RSI,%R8

(152) 0x41f731 MOV	%RAX,%RSI

(152) 0x41f734 PSHUFD	$-0x12,%XMM7,%XMM1

(152) 0x41f739 MOVQ	%XMM1,%RAX

(152) 0x41f73e XOR	%EDX,%EDX

(152) 0x41f740 DIVQ	-0x88(%RBP)

(152) 0x41f747 MOVQ	%RSI,%XMM1

(152) 0x41f74c MOVQ	%RAX,%XMM2

(152) 0x41f751 PUNPCKLQDQ	%XMM2,%XMM1

(152) 0x41f755 PSHUFD	$-0x18,%XMM1,%XMM15

(152) 0x41f75b PADDD	-0x130(%RBP),%XMM15

(152) 0x41f764 PMULUDQ	-0x140(%RBP),%XMM1

(152) 0x41f76c MOVDQA	%XMM7,%XMM2

(152) 0x41f770 PSUBQ	%XMM1,%XMM2

(152) 0x41f774 PSHUFD	$-0x18,%XMM2,%XMM1

(152) 0x41f779 PXOR	%XMM4,%XMM4

(152) 0x41f77d PXOR	%XMM9,%XMM9

(152) 0x41f782 PADDD	-0x120(%RBP),%XMM1

(152) 0x41f78a PCMPGTD	%XMM15,%XMM9

(152) 0x41f78f MOVDQA	%XMM15,%XMM12

(152) 0x41f794 PUNPCKLDQ	%XMM9,%XMM12

(152) 0x41f799 PCMPGTD	%XMM1,%XMM4

(152) 0x41f79d MOVDQA	-0x100(%RBP),%XMM10

(152) 0x41f7a6 PMULUDQ	%XMM12,%XMM10

(152) 0x41f7ab PUNPCKLDQ	0x7afec(%RIP),%XMM9

(152) 0x41f7b4 MOVDQA	%XMM1,%XMM2

(152) 0x41f7b8 MOVDQA	-0x110(%RBP),%XMM14

(152) 0x41f7c1 MOVDQA	%XMM14,%XMM3

(152) 0x41f7c6 PCMPEQD	%XMM0,%XMM0

(152) 0x41f7ca PSUBD	%XMM0,%XMM15

(152) 0x41f7cf PXOR	%XMM11,%XMM11

(152) 0x41f7d4 PUNPCKLDQ	%XMM4,%XMM2

(152) 0x41f7d8 PCMPGTD	%XMM15,%XMM11

(152) 0x41f7dd PUNPCKLDQ	%XMM11,%XMM15

(152) 0x41f7e2 MOVDQA	%XMM13,%XMM4

(152) 0x41f7e7 PMULUDQ	%XMM9,%XMM3

(152) 0x41f7ec PMULUDQ	%XMM15,%XMM4

(152) 0x41f7f1 MOVDQA	-0xe0(%RBP),%XMM5

(152) 0x41f7f9 PMULUDQ	%XMM5,%XMM15

(152) 0x41f7fe PSHUFD	$-0x2c,%XMM11,%XMM11

(152) 0x41f804 PADDQ	%XMM10,%XMM3

(152) 0x41f809 PMULUDQ	%XMM13,%XMM11

(152) 0x41f80e PMULUDQ	%XMM12,%XMM5

(152) 0x41f813 PADDQ	%XMM15,%XMM11

(152) 0x41f818 MOVDQA	%XMM13,%XMM15

(152) 0x41f81d PMULUDQ	%XMM9,%XMM15

(152) 0x41f822 PADDQ	%XMM5,%XMM15

(152) 0x41f827 PMULUDQ	%XMM12,%XMM14

(152) 0x41f82c PSLLQ	$0x20,%XMM3

(152) 0x41f831 PADDQ	%XMM2,%XMM14

(152) 0x41f836 PADDQ	%XMM3,%XMM14

(152) 0x41f83b PSLLQ	$0x3,%XMM14

(152) 0x41f841 PSLLQ	$0x20,%XMM11

(152) 0x41f847 PADDQ	%XMM2,%XMM4

(152) 0x41f84b PADDQ	%XMM11,%XMM4

(152) 0x41f850 MOVDQA	%XMM13,%XMM3

(152) 0x41f855 PMULUDQ	%XMM12,%XMM3

(152) 0x41f85a PSLLQ	$0x20,%XMM15

(152) 0x41f860 PADDQ	-0xf0(%RBP),%XMM14

(152) 0x41f869 PADDQ	%XMM2,%XMM3

(152) 0x41f86d PADDQ	%XMM15,%XMM3

(152) 0x41f872 PSUBD	%XMM0,%XMM1

(152) 0x41f876 MOVQ	%XMM14,%RDI

(152) 0x41f87b PXOR	%XMM11,%XMM11

(152) 0x41f880 PCMPGTD	%XMM1,%XMM11

(152) 0x41f885 PUNPCKLDQ	%XMM11,%XMM1

(152) 0x41f88a PSHUFD	$-0x12,%XMM14,%XMM10

(152) 0x41f890 MOVDQA	-0xd0(%RBP),%XMM0

(152) 0x41f898 MOVDQA	%XMM0,%XMM11

(152) 0x41f89d PSRLQ	$0x20,%XMM11

(152) 0x41f8a3 PMULUDQ	%XMM12,%XMM11

(152) 0x41f8a8 MOVQ	%XMM10,%R9

(152) 0x41f8ad MOVDQA	%XMM0,%XMM15

(152) 0x41f8b2 PMULUDQ	%XMM9,%XMM15

(152) 0x41f8b7 PADDQ	%XMM11,%XMM15

(152) 0x41f8bc MOVDQA	%XMM0,%XMM10

(152) 0x41f8c1 PMULUDQ	%XMM12,%XMM10

(152) 0x41f8c6 PSLLQ	$0x20,%XMM15

(152) 0x41f8cc PADDQ	%XMM10,%XMM15

(152) 0x41f8d1 PSLLQ	$0x3,%XMM4

(152) 0x41f8d6 MOVDQA	-0xc0(%RBP),%XMM0

(152) 0x41f8de PADDQ	%XMM0,%XMM4

(152) 0x41f8e2 MOVQ	%XMM4,%RAX

(152) 0x41f8e7 PSHUFD	$-0x12,%XMM4,%XMM4

(152) 0x41f8ec PSLLQ	$0x3,%XMM3

(152) 0x41f8f1 PADDQ	%XMM0,%XMM3

(152) 0x41f8f5 MOVQ	%XMM3,%RDX

(152) 0x41f8fa PSHUFD	$-0x12,%XMM3,%XMM3

(152) 0x41f8ff MOVQ	%XMM3,%RSI

(152) 0x41f904 PADDQ	%XMM15,%XMM1

(152) 0x41f909 PSLLQ	$0x3,%XMM1

(152) 0x41f90e MOVQ	%R15,%XMM3

(152) 0x41f913 MOVQ	%XMM4,%R13

(152) 0x41f918 PSHUFD	$0x44,%XMM3,%XMM4

(152) 0x41f91d PADDQ	%XMM4,%XMM1

(152) 0x41f921 MOVQ	%XMM1,%R14

(152) 0x41f926 MOVSD	(%RDI),%XMM10

(152) 0x41f92b PSHUFD	$-0x12,%XMM1,%XMM1

(152) 0x41f930 MOVQ	%XMM1,%RDI

(152) 0x41f935 MOVHPD	(%R9),%XMM10

(152) 0x41f93a MOVSD	(%RAX),%XMM3

(152) 0x41f93e PADDQ	%XMM2,%XMM15

(152) 0x41f943 MOVHPD	(%R13),%XMM3

(152) 0x41f949 PSLLQ	$0x3,%XMM15

(152) 0x41f94f PADDQ	%XMM4,%XMM15

(152) 0x41f954 MOVQ	%XMM15,%R9

(152) 0x41f959 MOVSD	(%R14),%XMM1

(152) 0x41f95e PSHUFD	$-0x12,%XMM15,%XMM4

(152) 0x41f964 MOVQ	%XMM4,%R14

(152) 0x41f969 MOVHPD	(%RDI),%XMM1

(152) 0x41f96d MOVSD	(%RDX),%XMM4

(152) 0x41f971 MOVHPD	(%RSI),%XMM4

(152) 0x41f975 ADDPD	%XMM10,%XMM3

(152) 0x41f97a MOVSD	(%R9),%XMM10

(152) 0x41f97f MOVHPD	(%R14),%XMM10

(152) 0x41f984 ADDPD	%XMM4,%XMM10

(152) 0x41f989 MOVDQA	%XMM6,%XMM4

(152) 0x41f98d PSRLQ	$0x20,%XMM4

(152) 0x41f992 PMULUDQ	%XMM12,%XMM4

(152) 0x41f997 ADDPD	%XMM3,%XMM1

(152) 0x41f99b MOVDQA	%XMM6,%XMM3

(152) 0x41f99f PMULUDQ	%XMM9,%XMM3

(152) 0x41f9a4 PADDQ	%XMM4,%XMM3

(152) 0x41f9a8 SUBPD	%XMM10,%XMM1

(152) 0x41f9ad MOVDQA	%XMM6,%XMM4

(152) 0x41f9b1 PMULUDQ	%XMM12,%XMM4

(152) 0x41f9b6 PSLLQ	$0x20,%XMM3

(152) 0x41f9bb PADDQ	%XMM2,%XMM4

(152) 0x41f9bf PADDQ	%XMM3,%XMM4

(152) 0x41f9c3 MOVQ	-0x38(%RBP),%XMM3

(152) 0x41f9c8 PSHUFD	$0x44,%XMM3,%XMM3

(152) 0x41f9cd PSLLQ	$0x3,%XMM4

(152) 0x41f9d2 PADDQ	%XMM4,%XMM3

(152) 0x41f9d6 MOVQ	%XMM3,%RDI

(152) 0x41f9db PSHUFD	$-0x12,%XMM3,%XMM3

(152) 0x41f9e0 MOVQ	%XMM3,%R9

(152) 0x41f9e5 MOVDQA	%XMM8,%XMM3

(152) 0x41f9ea MOVDQA	%XMM8,%XMM4

(152) 0x41f9ef PSRLQ	$0x20,%XMM4

(152) 0x41f9f4 PMULUDQ	%XMM12,%XMM3

(152) 0x41f9f9 PMULUDQ	%XMM12,%XMM4

(152) 0x41f9fe PMULUDQ	%XMM8,%XMM9

(152) 0x41fa03 PADDQ	%XMM4,%XMM9

(152) 0x41fa08 PADDQ	%XMM2,%XMM3

(152) 0x41fa0c MOVLPD	%XMM1,(%RDI)

(152) 0x41fa10 MOVHPD	%XMM1,(%R9)

(152) 0x41fa15 PSLLQ	$0x20,%XMM9

(152) 0x41fa1b PADDQ	%XMM9,%XMM3

(152) 0x41fa20 PSLLQ	$0x3,%XMM3

(152) 0x41fa25 MOVQ	-0x50(%RBP),%XMM2

(152) 0x41fa2a PSHUFD	$0x44,%XMM2,%XMM2

(152) 0x41fa2f PADDQ	%XMM3,%XMM2

(152) 0x41fa33 MOVSD	(%RAX),%XMM3

(152) 0x41fa37 MOVHPD	(%R13),%XMM3

(152) 0x41fa3d SUBPD	%XMM3,%XMM1

(152) 0x41fa41 MOVSD	(%RDX),%XMM3

(152) 0x41fa45 MOVHPD	(%RSI),%XMM3

(152) 0x41fa49 MOV	%R8,%RSI

(152) 0x41fa4c ADDPD	%XMM3,%XMM1

(152) 0x41fa50 MOVQ	%XMM2,%RAX

(152) 0x41fa55 PSHUFD	$-0x12,%XMM2,%XMM2

(152) 0x41fa5a MOVQ	%XMM2,%RDX

(152) 0x41fa5f MOVLPD	%XMM1,(%RAX)

(152) 0x41fa63 MOVHPD	%XMM1,(%RDX)

(152) 0x41fa67 PADDQ	0x7b9e1(%RIP),%XMM7

(152) 0x41fa6f ADD	$0x2,%R12

(152) 0x41fa73 CMP	%R8,%R12

(152) 0x41fa76 JB	41f720

0x41fa7c CMP	%RSI,-0x68(%RBP)

0x41fa80 MOV	-0x80(%RBP),%R14

0x41fa84 MOV	-0x78(%RBP),%R13

0x41fa88 MOV	-0x70(%RBP),%R12

0x41fa8c JNE	41fac9

0x41fa8e MOV	$0x4b7570,%EDI

0x41fa93 MOV	-0x3c(%RBP),%ESI

0x41fa96 ADD	$0x118,%RSP

0x41fa9d POP	%RBX

0x41fa9e POP	%R12

0x41faa0 POP	%R13

0x41faa2 POP	%R14

0x41faa4 POP	%R15

0x41faa6 POP	%RBP

0x41faa7 JMP	403050

0x41faac ADD	$0x118,%RSP

0x41fab3 POP	%RBX

0x41fab4 POP	%R12

0x41fab6 POP	%R13

0x41fab8 POP	%R14

0x41faba POP	%R15

0x41fabc POP	%RBP

0x41fabd RET

0x41fabe MOV	%RDI,%R14

0x41fac1 MOV	%R9,%R12

0x41fac4 JMP	41fb8c

0x41fac9 ADD	%RSI,%RCX

0x41facc JMP	41fb8c

0x41fad1 NOPW	%CS:(%RAX,%RAX,1)

(151) 0x41fae0 MOV	%RCX,%RAX

(151) 0x41fae3 XOR	%EDX,%EDX

(151) 0x41fae5 DIVQ	-0x30(%RBP)

(151) 0x41fae9 LEA	(%RAX,%RBX,1),%ESI

(151) 0x41faec ADD	-0x48(%RBP),%EDX

(151) 0x41faef MOVSXD	%EDX,%RDX

(151) 0x41faf2 MOVSXD	%ESI,%RSI

(151) 0x41faf5 MOV	%R14,%R9

(151) 0x41faf8 IMUL	%RSI,%R9

(151) 0x41fafc ADD	%RDX,%R9

(151) 0x41faff ADD	%EBX,%EAX

(151) 0x41fb01 INC	%EAX

(151) 0x41fb03 CLTQ

(151) 0x41fb05 IMUL	%R10,%RAX

(151) 0x41fb09 ADD	%RDX,%RAX

(151) 0x41fb0c MOVSD	(%R11,%RAX,8),%XMM0

(151) 0x41fb12 MOV	%R10,%RDI

(151) 0x41fb15 IMUL	%RSI,%RDI

(151) 0x41fb19 ADD	%RDX,%RDI

(151) 0x41fb1c ADDSD	(%R13,%R9,8),%XMM0

(151) 0x41fb23 MOVSD	(%R11,%RDI,8),%XMM1

(151) 0x41fb29 MOV	%R12,%R9

(151) 0x41fb2c IMUL	%RSI,%R9

(151) 0x41fb30 ADD	%RDX,%R9

(151) 0x41fb33 ADDSD	0x8(%R15,%R9,8),%XMM0

(151) 0x41fb3a ADDSD	(%R15,%R9,8),%XMM1

(151) 0x41fb40 SUBSD	%XMM1,%XMM0

(151) 0x41fb44 MOV	-0xa0(%RBP),%R9

(151) 0x41fb4b IMUL	%RSI,%R9

(151) 0x41fb4f ADD	%RDX,%R9

(151) 0x41fb52 MOV	-0x38(%RBP),%R8

(151) 0x41fb56 MOVSD	%XMM0,(%R8,%R9,8)

(151) 0x41fb5c SUBSD	(%R11,%RAX,8),%XMM0

(151) 0x41fb62 ADDSD	(%R11,%RDI,8),%XMM0

(151) 0x41fb68 IMUL	-0x98(%RBP),%RSI

(151) 0x41fb70 ADD	%RDX,%RSI

(151) 0x41fb73 MOV	-0x50(%RBP),%RAX

(151) 0x41fb77 MOVSD	%XMM0,(%RAX,%RSI,8)

(151) 0x41fb7c INC	%RCX

(151) 0x41fb7f CMP	%RCX,-0xa8(%RBP)

(151) 0x41fb86 JE	41fa8e

(151) 0x41fb8c MOV	%RCX,%RAX

(151) 0x41fb8f SHR	$0x20,%RAX

(151) 0x41fb93 JNE	41fae0

(151) 0x41fb99 MOV	%ECX,%EAX

(151) 0x41fb9b XOR	%EDX,%EDX

(151) 0x41fb9d DIVL	-0x30(%RBP)

(151) 0x41fba0 JMP	41fae9

0x41fba5 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_cell.cpp:136-141
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:136-141
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.17 to 11.50 cycles (2.10x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 24.17 to 2.57 cycles (9.40x speedup).

Details

35% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

12% of SSE/AVX loads are used in vector version.
31% of SSE/AVX stores are used in vector version.
16% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:136

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 212 bytes. The binary function is storing 296 bytes.

General properties

nb instructions	144
nb uops	145
loop length	639
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	32

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	24.17 cycles
front end	24.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.30	11.50	13.33	13.33	19.50	11.50	7.30	19.50	19.50	19.50	7.40	13.33
cycles	7.30	11.50	13.33	13.33	19.50	11.50	7.30	19.50	19.50	19.50	7.40	13.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	24.17
Dispatch	19.50
Overall L1	24.17

Vectorization ratios

all	35%
load	12%
store	31%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

all	16%
load	13%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.17 cycles. At this rate:

4% of peak load performance is reached (8.77 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (12.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 24.17 to 19.50 cycles (1.24x speedup).

ASM code

In the binary file, the address of the function is: 41f510

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x118,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 41faac <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.17+0x59c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xb0(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x60(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x58(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b7550,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 41fa8e <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.17+0x57e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
SUB %EDX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV (%R13),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R13),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R15),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R15),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%R12),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R12),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R12,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RCX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $-0x2,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %R12,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R8,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 41fabe <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.17+0x5ae>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R12,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %EAX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVD %EBX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVD %EDX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %RDI,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %RDI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R10,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOV %R9,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %R9,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R14,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R8,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
MOVQ %RCX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x7bd8a(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PSHUFD $0x44,%XMM0,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ %XMM2,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM2,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM2,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM3,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSRLQ $0x20,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM3,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %R13,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %R13,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM0,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R11,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,-0x68(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x80(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x78(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 41fac9 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.17+0x5b9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b7570,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x118,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0x118,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 41fb8c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.17+0x67c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD %RSI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 41fb8c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.17+0x67c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_cell.cpp:136-141
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:136-141
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

35% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

12% of SSE/AVX loads are used in vector version.
31% of SSE/AVX stores are used in vector version.
16% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:136

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 212 bytes. The binary function is storing 296 bytes.

General properties

nb instructions	144
nb uops	145
loop length	639
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	32

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	24.17 cycles
front end	24.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.30	11.50	13.33	13.33	19.50	11.50	7.30	19.50	19.50	19.50	7.40	13.33
cycles	7.30	11.50	13.33	13.33	19.50	11.50	7.30	19.50	19.50	19.50	7.40	13.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	24.17
Dispatch	19.50
Overall L1	24.17

Vectorization ratios

all	35%
load	12%
store	31%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

all	16%
load	13%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.17 cycles. At this rate:

4% of peak load performance is reached (8.77 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (12.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 41f510

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x118,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 41faac <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.17+0x59c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xb0(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x60(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x58(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b7550,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 41fa8e <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.17+0x57e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
SUB %EDX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV (%R13),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R13),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R15),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R15),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%R12),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R12),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R12,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RCX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $-0x2,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %R12,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R8,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 41fabe <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.17+0x5ae>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R12,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %EAX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVD %EBX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVD %EDX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %RDI,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %RDI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R10,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOV %R9,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %R9,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R14,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R8,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
MOVQ %RCX,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x7bd8a(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
PSHUFD $0x44,%XMM0,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ %XMM2,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM2,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM2,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM3,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSRLQ $0x20,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM3,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %R13,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %R13,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM0,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R11,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,-0x68(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x80(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x78(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 41fac9 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.17+0x5b9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b7570,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x118,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0x118,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 41fb8c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.17+0x67c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD %RSI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 41fb8c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.17+0x67c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	1.19	0.47
○Loop 152 - advec_cell.cpp:137-141 - exec	1.19	0.47
○Loop 151 - advec_cell.cpp:137-141 - exec	0.00	0.00

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Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

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Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code