OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .extracted.12]

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:146-151 [...]	Coverage (incl. loops): 0.97% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 146 - 151

--------------------------------------------------------------------------------

146: #pragma omp parallel for simd collapse(2)

147:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

148:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

149:           pre_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

150:           post_vol(i, j) = volume(i, j);

151:         }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41eff0 PUSH	%RBP

0x41eff1 MOV	%RSP,%RBP

0x41eff4 PUSH	%R15

0x41eff6 PUSH	%R14

0x41eff8 PUSH	%R13

0x41effa PUSH	%R12

0x41effc PUSH	%RBX

0x41effd SUB	$0xa8,%RSP

0x41f004 MOV	%RCX,%R12

0x41f007 MOV	0x30(%RBP),%RAX

0x41f00b MOV	0x20(%RBP),%R14

0x41f00f MOV	0x18(%RBP),%RCX

0x41f013 MOV	0x10(%RBP),%EBX

0x41f016 MOVL	$0,-0x38(%RBP)

0x41f01d TEST	%RAX,%RAX

0x41f020 JS	41f44a

0x41f026 MOV	%R8,%R15

0x41f029 MOV	%RDX,%R13

0x41f02c MOV	%R9,-0x30(%RBP)

0x41f030 MOV	%RCX,-0x40(%RBP)

0x41f034 MOV	(%RDI),%ESI

0x41f036 MOVQ	$0,-0x50(%RBP)

0x41f03e MOV	%RAX,-0x48(%RBP)

0x41f042 MOVQ	$0x1,-0x90(%RBP)

0x41f04d SUB	$0x8,%RSP

0x41f051 LEA	-0x90(%RBP),%RAX

0x41f058 LEA	-0x38(%RBP),%RCX

0x41f05c LEA	-0x50(%RBP),%R8

0x41f060 LEA	-0x48(%RBP),%R9

0x41f064 MOV	$0x4b74f0,%EDI

0x41f069 MOV	%ESI,-0x34(%RBP)

0x41f06c MOV	$0x22,%EDX

0x41f071 PUSH	$0x1

0x41f073 PUSH	$0x1

0x41f075 PUSH	%RAX

0x41f076 CALL	4031f0 <__kmpc_for_static_init_8@plt>

0x41f07b ADD	$0x20,%RSP

0x41f07f MOV	-0x50(%RBP),%RCX

0x41f083 MOV	-0x48(%RBP),%RAX

0x41f087 CMP	%RAX,%RCX

0x41f08a JA	41f42c

0x41f090 MOV	%R14,%R11

0x41f093 MOV	%RAX,%RDX

0x41f096 MOV	-0x40(%RBP),%RAX

0x41f09a SUB	%EAX,%R11D

0x41f09d MOV	(%R13),%RSI

0x41f0a1 MOV	0x10(%R13),%R8

0x41f0a5 MOV	(%R12),%R9

0x41f0a9 MOV	0x10(%R12),%R10

0x41f0ae MOV	(%R15),%RDI

0x41f0b1 MOV	0x10(%R15),%R15

0x41f0b5 MOV	-0x30(%RBP),%R14

0x41f0b9 MOV	(%R14),%R12

0x41f0bc MOV	0x10(%R14),%R14

0x41f0c0 INC	%RDX

0x41f0c3 MOV	%RDX,-0x30(%RBP)

0x41f0c7 SUB	%RCX,%RDX

0x41f0ca MOV	$-0x2,%R13D

0x41f0d0 AND	%RDX,%R13

0x41f0d3 MOV	%RDI,-0x88(%RBP)

0x41f0da MOV	%R12,-0x80(%RBP)

0x41f0de JE	41f45c

0x41f0e4 MOV	%RDX,-0x58(%RBP)

0x41f0e8 MOV	%R11,-0x68(%RBP)

0x41f0ec MOVD	%R11D,%XMM0

0x41f0f1 PSHUFD	$0x44,%XMM0,%XMM1

0x41f0f6 MOVD	%EBX,%XMM0

0x41f0fa PSHUFD	$0x50,%XMM0,%XMM0

0x41f0ff MOVDQA	%XMM0,-0xc0(%RBP)

0x41f107 MOVQ	%RAX,%XMM0

0x41f10c PSHUFD	$0x44,%XMM0,%XMM0

0x41f111 MOVDQA	%XMM0,-0xb0(%RBP)

0x41f119 MOV	%RSI,-0x60(%RBP)

0x41f11d MOVQ	%RSI,%XMM0

0x41f122 PSHUFD	$0x44,%XMM0,%XMM9

0x41f128 MOVQ	%R9,%XMM0

0x41f12d PSHUFD	$0x44,%XMM0,%XMM12

0x41f133 MOVQ	%RDI,%XMM0

0x41f138 PSHUFD	$0x44,%XMM0,%XMM5

0x41f13d MOVQ	%R12,%XMM0

0x41f142 PSHUFD	$0x44,%XMM0,%XMM6

0x41f147 MOVQ	%RCX,%XMM0

0x41f14c PSHUFD	$0x44,%XMM0,%XMM7

0x41f151 PADDQ	0x7c2d7(%RIP),%XMM7

0x41f159 XOR	%EDI,%EDI

0x41f15b MOVQ	%XMM1,-0x78(%RBP)

0x41f160 MOVDQA	%XMM1,-0xd0(%RBP)

0x41f168 PSHUFD	$-0x12,%XMM1,%XMM0

0x41f16d MOVQ	%XMM0,-0x70(%RBP)

0x41f172 MOVDQA	%XMM9,%XMM10

0x41f177 PSRLQ	$0x20,%XMM10

0x41f17d MOVQ	%R8,%XMM0

0x41f182 PSHUFD	$0x44,%XMM0,%XMM0

0x41f187 MOVDQA	%XMM0,-0xa0(%RBP)

0x41f18f MOVDQA	%XMM12,%XMM0

0x41f194 PSRLQ	$0x20,%XMM0

0x41f199 MOVQ	%R10,%XMM1

0x41f19e PSHUFD	$0x44,%XMM1,%XMM13

0x41f1a4 MOVDQA	%XMM5,%XMM14

0x41f1a9 PSRLQ	$0x20,%XMM14

0x41f1af NOP

(150) 0x41f1b0 MOVQ	%XMM7,%RAX

(150) 0x41f1b5 XOR	%EDX,%EDX

(150) 0x41f1b7 DIVQ	-0x78(%RBP)

(150) 0x41f1bb PSHUFD	$-0x12,%XMM7,%XMM1

(150) 0x41f1c0 MOVQ	%XMM1,%RDX

(150) 0x41f1c5 MOVQ	%RAX,%XMM1

(150) 0x41f1ca MOV	%RDX,%RAX

(150) 0x41f1cd XOR	%EDX,%EDX

(150) 0x41f1cf DIVQ	-0x70(%RBP)

(150) 0x41f1d3 MOVQ	%RAX,%XMM3

(150) 0x41f1d8 PUNPCKLQDQ	%XMM3,%XMM1

(150) 0x41f1dc PSHUFD	$-0x18,%XMM1,%XMM15

(150) 0x41f1e2 PADDD	-0xc0(%RBP),%XMM15

(150) 0x41f1eb PMULUDQ	-0xd0(%RBP),%XMM1

(150) 0x41f1f3 MOVDQA	%XMM7,%XMM3

(150) 0x41f1f7 PSUBQ	%XMM1,%XMM3

(150) 0x41f1fb PADDQ	-0xb0(%RBP),%XMM3

(150) 0x41f203 PSLLQ	$0x20,%XMM3

(150) 0x41f208 PSHUFD	$-0x13,%XMM3,%XMM11

(150) 0x41f20e PXOR	%XMM8,%XMM8

(150) 0x41f213 MOVDQA	%XMM11,%XMM3

(150) 0x41f218 PCMPGTD	%XMM15,%XMM8

(150) 0x41f21d MOVDQA	%XMM15,%XMM1

(150) 0x41f222 PUNPCKLDQ	%XMM8,%XMM1

(150) 0x41f227 PSRAD	$0x1f,%XMM3

(150) 0x41f22c MOVDQA	%XMM9,%XMM4

(150) 0x41f231 PMULUDQ	%XMM1,%XMM4

(150) 0x41f235 MOVDQA	%XMM10,%XMM2

(150) 0x41f23a PUNPCKLDQ	%XMM3,%XMM11

(150) 0x41f23f PMULUDQ	%XMM1,%XMM2

(150) 0x41f243 PUNPCKLDQ	0x7b554(%RIP),%XMM8

(150) 0x41f24c MOVDQA	%XMM9,%XMM3

(150) 0x41f251 PMULUDQ	%XMM8,%XMM3

(150) 0x41f256 PADDQ	%XMM2,%XMM3

(150) 0x41f25a PSLLQ	$0x20,%XMM3

(150) 0x41f25f PADDQ	%XMM4,%XMM3

(150) 0x41f263 PADDQ	%XMM11,%XMM3

(150) 0x41f268 PSUBD	0x7c34f(%RIP),%XMM15

(150) 0x41f271 PXOR	%XMM2,%XMM2

(150) 0x41f275 PCMPGTD	%XMM15,%XMM2

(150) 0x41f27a PSLLQ	$0x3,%XMM3

(150) 0x41f27f PUNPCKLDQ	%XMM2,%XMM15

(150) 0x41f284 MOVDQA	%XMM12,%XMM4

(150) 0x41f289 PMULUDQ	%XMM15,%XMM4

(150) 0x41f28e PADDQ	-0xa0(%RBP),%XMM3

(150) 0x41f296 PMULUDQ	%XMM0,%XMM15

(150) 0x41f29b PSHUFD	$-0x2c,%XMM2,%XMM2

(150) 0x41f2a0 PMULUDQ	%XMM12,%XMM2

(150) 0x41f2a5 MOVQ	%XMM3,%RAX

(150) 0x41f2aa PADDQ	%XMM15,%XMM2

(150) 0x41f2af PSLLQ	$0x20,%XMM2

(150) 0x41f2b4 PADDQ	%XMM11,%XMM4

(150) 0x41f2b9 PSHUFD	$-0x12,%XMM3,%XMM3

(150) 0x41f2be PADDQ	%XMM2,%XMM4

(150) 0x41f2c2 PSLLQ	$0x3,%XMM4

(150) 0x41f2c7 PADDQ	%XMM13,%XMM4

(150) 0x41f2cc MOVQ	%XMM3,%RDX

(150) 0x41f2d1 MOVQ	%XMM4,%RSI

(150) 0x41f2d6 MOVDQA	%XMM0,%XMM2

(150) 0x41f2da PMULUDQ	%XMM1,%XMM2

(150) 0x41f2de PSHUFD	$-0x12,%XMM4,%XMM3

(150) 0x41f2e3 MOVDQA	%XMM12,%XMM4

(150) 0x41f2e8 PMULUDQ	%XMM8,%XMM4

(150) 0x41f2ed PADDQ	%XMM2,%XMM4

(150) 0x41f2f1 MOVSD	(%RAX),%XMM2

(150) 0x41f2f5 MOVDQA	%XMM12,%XMM15

(150) 0x41f2fa PMULUDQ	%XMM1,%XMM15

(150) 0x41f2ff PSLLQ	$0x20,%XMM4

(150) 0x41f304 MOVQ	%XMM3,%R12

(150) 0x41f309 PADDQ	%XMM15,%XMM4

(150) 0x41f30e PADDQ	%XMM11,%XMM4

(150) 0x41f313 MOVHPD	(%RDX),%XMM2

(150) 0x41f317 PSLLQ	$0x3,%XMM4

(150) 0x41f31c PADDQ	%XMM13,%XMM4

(150) 0x41f321 MOVQ	%XMM4,%R11

(150) 0x41f326 MOVSD	(%RSI),%XMM3

(150) 0x41f32a PSHUFD	$-0x12,%XMM4,%XMM4

(150) 0x41f32f MOVQ	%XMM4,%RSI

(150) 0x41f334 MOVHPD	(%R12),%XMM3

(150) 0x41f33a MOVSD	(%R11),%XMM4

(150) 0x41f33f MOVDQA	%XMM14,%XMM15

(150) 0x41f344 PMULUDQ	%XMM1,%XMM15

(150) 0x41f349 ADDPD	%XMM2,%XMM3

(150) 0x41f34d MOVDQA	%XMM5,%XMM2

(150) 0x41f351 PMULUDQ	%XMM8,%XMM2

(150) 0x41f356 MOVHPD	(%RSI),%XMM4

(150) 0x41f35a PADDQ	%XMM15,%XMM2

(150) 0x41f35f MOVDQA	%XMM5,%XMM15

(150) 0x41f364 PMULUDQ	%XMM1,%XMM15

(150) 0x41f369 PSLLQ	$0x20,%XMM2

(150) 0x41f36e PADDQ	%XMM15,%XMM2

(150) 0x41f373 PADDQ	%XMM11,%XMM2

(150) 0x41f378 PSLLQ	$0x3,%XMM2

(150) 0x41f37d SUBPD	%XMM4,%XMM3

(150) 0x41f381 MOVQ	%R15,%XMM4

(150) 0x41f386 PSHUFD	$0x44,%XMM4,%XMM4

(150) 0x41f38b PADDQ	%XMM2,%XMM4

(150) 0x41f38f MOVQ	%XMM4,%RSI

(150) 0x41f394 MOVLPD	%XMM3,(%RSI)

(150) 0x41f398 PSHUFD	$-0x12,%XMM4,%XMM2

(150) 0x41f39d MOVQ	%XMM2,%RSI

(150) 0x41f3a2 MOVHPD	%XMM3,(%RSI)

(150) 0x41f3a6 MOVDQA	%XMM6,%XMM2

(150) 0x41f3aa MOVDQA	%XMM6,%XMM3

(150) 0x41f3ae PSRLQ	$0x20,%XMM3

(150) 0x41f3b3 PMULUDQ	%XMM1,%XMM2

(150) 0x41f3b7 PMULUDQ	%XMM1,%XMM3

(150) 0x41f3bb PMULUDQ	%XMM6,%XMM8

(150) 0x41f3c0 PADDQ	%XMM3,%XMM8

(150) 0x41f3c5 PSLLQ	$0x20,%XMM8

(150) 0x41f3cb PADDQ	%XMM2,%XMM8

(150) 0x41f3d0 PADDQ	%XMM11,%XMM8

(150) 0x41f3d5 MOVQ	%R14,%XMM1

(150) 0x41f3da PSLLQ	$0x3,%XMM8

(150) 0x41f3e0 PSHUFD	$0x44,%XMM1,%XMM1

(150) 0x41f3e5 PADDQ	%XMM8,%XMM1

(150) 0x41f3ea MOVSD	(%RAX),%XMM2

(150) 0x41f3ee MOVQ	%XMM1,%RAX

(150) 0x41f3f3 PSHUFD	$-0x12,%XMM1,%XMM1

(150) 0x41f3f8 MOVQ	%XMM1,%RSI

(150) 0x41f3fd MOVQ	(%RDX),%XMM1

(150) 0x41f401 MOVSD	%XMM2,(%RAX)

(150) 0x41f405 MOVQ	%XMM1,(%RSI)

(150) 0x41f409 PADDQ	0x7c03f(%RIP),%XMM7

(150) 0x41f411 ADD	$0x2,%RDI

(150) 0x41f415 CMP	%R13,%RDI

(150) 0x41f418 JB	41f1b0

0x41f41e CMP	%R13,-0x58(%RBP)

0x41f422 MOV	-0x68(%RBP),%R11

0x41f426 MOV	-0x60(%RBP),%R12

0x41f42a JNE	41f464

0x41f42c MOV	$0x4b7510,%EDI

0x41f431 MOV	-0x34(%RBP),%ESI

0x41f434 ADD	$0xa8,%RSP

0x41f43b POP	%RBX

0x41f43c POP	%R12

0x41f43e POP	%R13

0x41f440 POP	%R14

0x41f442 POP	%R15

0x41f444 POP	%RBP

0x41f445 JMP	403050

0x41f44a ADD	$0xa8,%RSP

0x41f451 POP	%RBX

0x41f452 POP	%R12

0x41f454 POP	%R13

0x41f456 POP	%R14

0x41f458 POP	%R15

0x41f45a POP	%RBP

0x41f45b RET

0x41f45c MOV	%RSI,%R12

0x41f45f JMP	41f4ec

0x41f464 ADD	%R13,%RCX

0x41f467 JMP	41f4ec

0x41f46c NOPL	(%RAX)

(149) 0x41f470 MOV	%RCX,%RAX

(149) 0x41f473 XOR	%EDX,%EDX

(149) 0x41f475 DIV	%R11

(149) 0x41f478 LEA	(%RAX,%RBX,1),%ESI

(149) 0x41f47b ADD	-0x40(%RBP),%EDX

(149) 0x41f47e MOVSXD	%EDX,%RDX

(149) 0x41f481 MOVSXD	%ESI,%RSI

(149) 0x41f484 MOV	%R12,%RDI

(149) 0x41f487 IMUL	%RSI,%RDI

(149) 0x41f48b ADD	%RDX,%RDI

(149) 0x41f48e ADD	%EBX,%EAX

(149) 0x41f490 INC	%EAX

(149) 0x41f492 CLTQ

(149) 0x41f494 IMUL	%R9,%RAX

(149) 0x41f498 ADD	%RDX,%RAX

(149) 0x41f49b MOVSD	(%R10,%RAX,8),%XMM0

(149) 0x41f4a1 ADDSD	(%R8,%RDI,8),%XMM0

(149) 0x41f4a7 MOV	%R9,%RAX

(149) 0x41f4aa IMUL	%RSI,%RAX

(149) 0x41f4ae ADD	%RDX,%RAX

(149) 0x41f4b1 SUBSD	(%R10,%RAX,8),%XMM0

(149) 0x41f4b7 MOV	-0x88(%RBP),%RAX

(149) 0x41f4be IMUL	%RSI,%RAX

(149) 0x41f4c2 ADD	%RDX,%RAX

(149) 0x41f4c5 MOVSD	%XMM0,(%R15,%RAX,8)

(149) 0x41f4cb MOVQ	(%R8,%RDI,8),%XMM0

(149) 0x41f4d1 IMUL	-0x80(%RBP),%RSI

(149) 0x41f4d6 ADD	%RDX,%RSI

(149) 0x41f4d9 MOVQ	%XMM0,(%R14,%RSI,8)

(149) 0x41f4df INC	%RCX

(149) 0x41f4e2 CMP	%RCX,-0x30(%RBP)

(149) 0x41f4e6 JE	41f42c

(149) 0x41f4ec MOV	%RCX,%RAX

(149) 0x41f4ef SHR	$0x20,%RAX

(149) 0x41f4f3 JNE	41f470

(149) 0x41f4f9 MOV	%ECX,%EAX

(149) 0x41f4fb XOR	%EDX,%EDX

(149) 0x41f4fd DIV	%R11D

(149) 0x41f500 JMP	41f478

0x41f505 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_cell.cpp:146-151
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:146-151
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.67 to 10.50 cycles (2.06x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 21.67 to 2.23 cycles (9.74x speedup).

Details

31% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

10% of SSE/AVX loads are used in vector version.
21% of SSE/AVX stores are used in vector version.
11% of SSE/AVX addition or subtraction instructions are used in vector version.
51% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:146

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 172 bytes. The binary function is storing 176 bytes.

General properties

nb instructions	129
nb uops	130
loop length	541
used x86 registers	16
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	22

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.67 cycles
front end	21.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.70	10.50	11.67	11.67	14.50	10.50	7.70	14.50	14.50	14.50	7.60	11.67
cycles	7.70	10.50	11.67	11.67	14.50	10.50	7.70	14.50	14.50	14.50	7.60	11.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.67
Dispatch	14.50
Overall L1	21.67

Vectorization ratios

all	31%
load	10%
store	21%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	51%

Vector efficiency ratios

all	15%
load	11%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.67 cycles. At this rate:

4% of peak load performance is reached (7.94 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 21.67 to 14.50 cycles (1.49x speedup).

ASM code

In the binary file, the address of the function is: 41eff0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xa8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 41f44a <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.12+0x45a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x90(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x50(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x48(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b74f0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x50(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 41f42c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.12+0x43c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EAX,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%R13),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R13),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R12),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R15),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R15),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV $-0x2,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %RDX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDI,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 41f45c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.12+0x46c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %R11D,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVD %EBX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RAX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %RSI,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %RSI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R9,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RDI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R12,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RCX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x7c2d7(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ %XMM1,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM1,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R8,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM12,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R10,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM5,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R13,-0x58(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x68(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x60(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 41f464 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.12+0x474>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b7510,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0xa8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0xa8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 41f4ec <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.12+0x4fc>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD %R13,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 41f4ec <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.12+0x4fc>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_cell.cpp:146-151
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:146-151
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

31% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

10% of SSE/AVX loads are used in vector version.
21% of SSE/AVX stores are used in vector version.
11% of SSE/AVX addition or subtraction instructions are used in vector version.
51% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:146

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 172 bytes. The binary function is storing 176 bytes.

General properties

nb instructions	129
nb uops	130
loop length	541
used x86 registers	16
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	22

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.67 cycles
front end	21.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.70	10.50	11.67	11.67	14.50	10.50	7.70	14.50	14.50	14.50	7.60	11.67
cycles	7.70	10.50	11.67	11.67	14.50	10.50	7.70	14.50	14.50	14.50	7.60	11.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.67
Dispatch	14.50
Overall L1	21.67

Vectorization ratios

all	31%
load	10%
store	21%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	51%

Vector efficiency ratios

all	15%
load	11%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.67 cycles. At this rate:

4% of peak load performance is reached (7.94 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 41eff0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xa8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 41f44a <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.12+0x45a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x90(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x50(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x48(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b74f0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x50(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 41f42c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.12+0x43c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %EAX,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%R13),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R13),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R12),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R15),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R15),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R14),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV $-0x2,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %RDX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDI,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 41f45c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.12+0x46c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %R11D,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVD %EBX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RAX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %RSI,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ %RSI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R9,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RDI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %R12,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %RCX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x7c2d7(%RIP),%XMM7	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ %XMM1,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM1,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R8,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVDQA %XMM12,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVQ %R10,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM13	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM5,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
PSRLQ $0x20,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R13,-0x58(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x68(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x60(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 41f464 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.12+0x474>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b7510,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0xa8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD $0xa8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 41f4ec <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.12+0x4fc>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD %R13,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 41f4ec <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.12+0x4fc>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	0.97	0.38
○Loop 150 - advec_cell.cpp:147-151 - exec	0.97	0.38
○Loop 149 - advec_cell.cpp:147-151 - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

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Vector efficiency ratios

Cycles and memory resources usage

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ASM code