OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .extracted.7]

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:157-202 [...]	Coverage (incl. loops): 4.57% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 157 - 202

--------------------------------------------------------------------------------

157: #pragma omp parallel for simd collapse(2)

158:     for (int j = (y_min + 1); j < (y_max + 2 + 2); j++) {

159:       for (int i = (x_min + 1); i < (x_max + 2); i++)

160:         ({

161:           int upwind, donor, downwind, dif;

162:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

163:           if (vol_flux_y(i, j) > 0.0) {

164:             upwind = j - 2;

165:             donor = j - 1;

166:             downwind = j;

167:             dif = donor;

168:           } else {

169:             upwind = std::min(j + 1, y_max + 2);

170:             donor = j;

171:             downwind = j - 1;

172:             dif = upwind;

173:           }

174:           sigmat = std::fabs(vol_flux_y(i, j)) / pre_vol(i, donor);

175:           sigma3 = (1.0 + sigmat) * (vertexdy[j] / vertexdy[dif]);

176:           sigma4 = 2.0 - sigmat;

177:           sigmav = sigmat;

178:           diffuw = density1(i, donor) - density1(i, upwind);

179:           diffdw = density1(i, downwind) - density1(i, donor);

180:           wind = 1.0;

181:           if (diffdw <= 0.0) wind = -1.0;

182:           if (diffuw * diffdw > 0.0) {

183:             limiter = (1.0 - sigmav) * wind *

184:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

185:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

186:           } else {

187:             limiter = 0.0;

188:           }

189:           mass_flux_y(i, j) = vol_flux_y(i, j) * (density1(i, donor) + limiter);

190:           sigmam = std::fabs(mass_flux_y(i, j)) / (density1(i, donor) * pre_vol(i, donor));

191:           diffuw = energy1(i, donor) - energy1(i, upwind);

192:           diffdw = energy1(i, downwind) - energy1(i, donor);

193:           wind = 1.0;

194:           if (diffdw <= 0.0) wind = -1.0;

195:           if (diffuw * diffdw > 0.0) {

196:             limiter = (1.0 - sigmam) * wind *

197:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

198:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

199:           } else {

200:             limiter = 0.0;

201:           }

202:           ener_flux(i, j) = mass_flux_y(i, j) * (energy1(i, donor) + limiter);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41e1d0 PUSH	%RBP

0x41e1d1 MOV	%RSP,%RBP

0x41e1d4 PUSH	%R15

0x41e1d6 PUSH	%R14

0x41e1d8 PUSH	%R13

0x41e1da PUSH	%R12

0x41e1dc PUSH	%RBX

0x41e1dd SUB	$0x1f8,%RSP

0x41e1e4 MOV	%RCX,%RSI

0x41e1e7 MOV	0x50(%RBP),%RAX

0x41e1eb MOV	0x40(%RBP),%R12

0x41e1ef MOV	0x38(%RBP),%R11

0x41e1f3 MOV	0x28(%RBP),%RBX

0x41e1f7 MOV	0x20(%RBP),%R13

0x41e1fb MOV	0x18(%RBP),%R15

0x41e1ff MOV	0x10(%RBP),%R14

0x41e203 MOV	0x30(%RBP),%ECX

0x41e206 MOV	%RCX,-0x70(%RBP)

0x41e20a MOVL	$0,-0x50(%RBP)

0x41e211 TEST	%RAX,%RAX

0x41e214 JS	41ec54

0x41e21a MOV	%RSI,-0x30(%RBP)

0x41e21e MOV	%R8,-0x38(%RBP)

0x41e222 MOV	%R9,-0xb0(%RBP)

0x41e229 MOV	%RDX,-0x40(%RBP)

0x41e22d MOV	(%RDI),%ESI

0x41e22f MOVQ	$0,-0xa0(%RBP)

0x41e23a MOV	%RAX,-0x98(%RBP)

0x41e241 MOVQ	$0x1,-0xe8(%RBP)

0x41e24c SUB	$0x8,%RSP

0x41e250 LEA	-0xe8(%RBP),%RAX

0x41e257 LEA	-0x50(%RBP),%RCX

0x41e25b LEA	-0xa0(%RBP),%R8

0x41e262 MOV	%R11,-0x68(%RBP)

0x41e266 LEA	-0x98(%RBP),%R9

0x41e26d MOV	$0x4b7490,%EDI

0x41e272 MOV	%ESI,-0x4c(%RBP)

0x41e275 MOV	$0x22,%EDX

0x41e27a PUSH	$0x1

0x41e27c PUSH	$0x1

0x41e27e PUSH	%RAX

0x41e27f CALL	4031f0 <__kmpc_for_static_init_8@plt>

0x41e284 MOV	-0x68(%RBP),%R9

0x41e288 ADD	$0x20,%RSP

0x41e28c MOV	-0xa0(%RBP),%RCX

0x41e293 MOV	-0x98(%RBP),%RAX

0x41e29a CMP	%RAX,%RCX

0x41e29d JA	41ec6f

0x41e2a3 MOV	%R12,%R11

0x41e2a6 MOV	%RAX,%RDX

0x41e2a9 SUB	%R9D,%R11D

0x41e2ac MOV	(%R15),%RDI

0x41e2af MOV	0x10(%R15),%R10

0x41e2b3 MOV	(%R13),%RSI

0x41e2b7 MOV	0x10(%R13),%RAX

0x41e2bb MOV	%RAX,-0x48(%RBP)

0x41e2bf MOV	-0x30(%RBP),%RAX

0x41e2c3 MOV	0x8(%RAX),%RAX

0x41e2c7 MOV	%RAX,-0x90(%RBP)

0x41e2ce MOV	-0x38(%RBP),%RAX

0x41e2d2 MOV	(%RAX),%R8

0x41e2d5 MOV	0x10(%RAX),%R12

0x41e2d9 MOV	(%R14),%R13

0x41e2dc MOV	0x10(%R14),%RAX

0x41e2e0 MOV	%RAX,-0x88(%RBP)

0x41e2e7 MOV	-0xb0(%RBP),%RAX

0x41e2ee MOV	(%RAX),%R14

0x41e2f1 MOV	0x10(%RAX),%RAX

0x41e2f5 MOV	%RAX,-0x80(%RBP)

0x41e2f9 MOV	(%RBX),%RAX

0x41e2fc MOV	%RAX,-0x60(%RBP)

0x41e300 MOV	0x10(%RBX),%RAX

0x41e304 MOV	%RAX,-0x78(%RBP)

0x41e308 MOV	-0x40(%RBP),%RAX

0x41e30c ADD	$0x2,%EAX

0x41e30f INC	%RDX

0x41e312 MOV	%RDX,-0xe0(%RBP)

0x41e319 SUB	%RCX,%RDX

0x41e31c MOV	$-0x2,%R15D

0x41e322 AND	%RDX,%R15

0x41e325 MOV	%RAX,-0x40(%RBP)

0x41e329 MOV	%RDI,-0x38(%RBP)

0x41e32d MOV	%R10,-0x30(%RBP)

0x41e331 MOV	%RSI,-0x58(%RBP)

0x41e335 MOV	%R13,-0xd8(%RBP)

0x41e33c MOV	%R14,-0xd0(%RBP)

0x41e343 JE	41ec8d

0x41e349 MOV	%RDX,-0xb8(%RBP)

0x41e350 MOVD	%R11D,%XMM0

0x41e355 PSHUFD	$0x44,%XMM0,%XMM1

0x41e35a MOVD	-0x70(%RBP),%XMM0

0x41e35f PSHUFD	$0x50,%XMM0,%XMM0

0x41e364 MOVDQA	%XMM0,-0x1a0(%RBP)

0x41e36c MOVQ	%R9,%XMM0

0x41e371 PSHUFD	$0x44,%XMM0,%XMM0

0x41e376 MOVDQA	%XMM0,-0x190(%RBP)

0x41e37e MOVQ	%RDI,%XMM0

0x41e383 PSHUFD	$0x44,%XMM0,%XMM2

0x41e388 MOVD	%EAX,%XMM0

0x41e38c PSHUFD	$0x50,%XMM0,%XMM0

0x41e391 MOVDQA	%XMM0,-0x170(%RBP)

0x41e399 MOVQ	%RSI,%XMM0

0x41e39e PSHUFD	$0x44,%XMM0,%XMM0

0x41e3a3 MOVDQA	%XMM0,-0x160(%RBP)

0x41e3ab MOVQ	%R8,%XMM0

0x41e3b0 PSHUFD	$0x44,%XMM0,%XMM0

0x41e3b5 MOVDQA	%XMM0,-0x150(%RBP)

0x41e3bd MOVQ	%R13,%XMM0

0x41e3c2 PSHUFD	$0x44,%XMM0,%XMM0

0x41e3c7 MOVDQA	%XMM0,-0x140(%RBP)

0x41e3cf MOVQ	%R14,%XMM0

0x41e3d4 PSHUFD	$0x44,%XMM0,%XMM0

0x41e3d9 MOVDQA	%XMM0,-0x130(%RBP)

0x41e3e1 MOV	-0x60(%RBP),%RAX

0x41e3e5 MOVQ	%RAX,%XMM0

0x41e3ea PSHUFD	$0x44,%XMM0,%XMM0

0x41e3ef MOVDQA	%XMM0,-0x120(%RBP)

0x41e3f7 MOVQ	%RCX,%XMM0

0x41e3fc PSHUFD	$0x44,%XMM0,%XMM3

0x41e401 PADDQ	0x7d027(%RIP),%XMM3

0x41e409 XOR	%ESI,%ESI

0x41e40b MOVQ	%XMM1,-0xc8(%RBP)

0x41e413 MOVDQA	%XMM1,-0x1b0(%RBP)

0x41e41b PSHUFD	$-0x12,%XMM1,%XMM0

0x41e420 MOVQ	%XMM0,-0xc0(%RBP)

0x41e428 PXOR	%XMM10,%XMM10

0x41e42d MOVDQA	%XMM2,-0x180(%RBP)

0x41e435 PSRLQ	$0x20,%XMM2

0x41e43a MOVDQA	%XMM2,-0x110(%RBP)

0x41e442 MOVQ	%R10,%XMM0

0x41e447 PSHUFD	$0x44,%XMM0,%XMM0

0x41e44c MOVDQA	%XMM0,-0x100(%RBP)

0x41e454 MOVAPD	0x7c693(%RIP),%XMM12

0x41e45d JMP	41e5a6

0x41e462 NOPW	%CS:(%RAX,%RAX,1)

(148) 0x41e470 MOV	-0x38(%RBP),%RDI

(148) 0x41e474 MOV	-0x30(%RBP),%RBX

(148) 0x41e478 MULPD	%XMM7,%XMM6

(148) 0x41e47c DIVPD	%XMM6,%XMM0

(148) 0x41e480 MOVAPD	%XMM5,%XMM6

(148) 0x41e484 CMPPD	$0x6,%XMM10,%XMM6

(148) 0x41e48a MOVAPD	0x7d14e(%RIP),%XMM7

(148) 0x41e492 MOVAPD	%XMM7,%XMM3

(148) 0x41e496 SUBPD	%XMM0,%XMM3

(148) 0x41e49a SUBPD	%XMM7,%XMM0

(148) 0x41e49e ANDPD	%XMM6,%XMM3

(148) 0x41e4a2 ANDNPD	%XMM0,%XMM6

(148) 0x41e4a6 ORPD	%XMM3,%XMM6

(148) 0x41e4aa ANDPD	%XMM12,%XMM4

(148) 0x41e4af ANDPD	%XMM12,%XMM5

(148) 0x41e4b4 MOVAPD	%XMM5,%XMM0

(148) 0x41e4b8 MINPD	%XMM4,%XMM0

(148) 0x41e4bc MOVAPD	%XMM4,%XMM3

(148) 0x41e4c0 CMPPD	$0x3,%XMM4,%XMM3

(148) 0x41e4c5 MOVAPD	%XMM5,%XMM7

(148) 0x41e4c9 ANDPD	%XMM3,%XMM7

(148) 0x41e4cd ANDNPD	%XMM0,%XMM3

(148) 0x41e4d1 ORPD	%XMM7,%XMM3

(148) 0x41e4d5 MULPD	-0x200(%RBP),%XMM5

(148) 0x41e4dd MULPD	-0x210(%RBP),%XMM4

(148) 0x41e4e5 ADDPD	%XMM5,%XMM4

(148) 0x41e4e9 MOVAPD	0x7d10f(%RIP),%XMM5

(148) 0x41e4f1 MULPD	%XMM5,%XMM4

(148) 0x41e4f5 MOVAPD	%XMM4,%XMM0

(148) 0x41e4f9 MINPD	%XMM3,%XMM0

(148) 0x41e4fd CMPPD	$0x3,%XMM3,%XMM3

(148) 0x41e502 ANDPD	%XMM3,%XMM4

(148) 0x41e506 ANDNPD	%XMM0,%XMM3

(148) 0x41e50a ORPD	%XMM4,%XMM3

(148) 0x41e50e MULPD	%XMM6,%XMM3

(148) 0x41e512 ANDPD	%XMM3,%XMM2

(148) 0x41e516 ADDPD	%XMM1,%XMM2

(148) 0x41e51a MULPD	%XMM9,%XMM2

(148) 0x41e51f MOVDQA	-0x120(%RBP),%XMM3

(148) 0x41e527 MOVDQA	%XMM3,%XMM0

(148) 0x41e52b PSRLQ	$0x20,%XMM0

(148) 0x41e530 MOVDQA	-0xb0(%RBP),%XMM4

(148) 0x41e538 PMULUDQ	%XMM4,%XMM0

(148) 0x41e53c MOVDQA	%XMM3,%XMM1

(148) 0x41e540 PMULUDQ	%XMM4,%XMM1

(148) 0x41e544 PSRLQ	$0x20,%XMM4

(148) 0x41e549 PMULUDQ	%XMM3,%XMM4

(148) 0x41e54d PADDQ	%XMM0,%XMM4

(148) 0x41e551 PADDQ	%XMM8,%XMM1

(148) 0x41e556 PSLLQ	$0x20,%XMM4

(148) 0x41e55b PADDQ	%XMM4,%XMM1

(148) 0x41e55f PSLLQ	$0x3,%XMM1

(148) 0x41e564 MOVQ	-0x78(%RBP),%XMM0

(148) 0x41e569 PSHUFD	$0x44,%XMM0,%XMM0

(148) 0x41e56e PADDQ	%XMM1,%XMM0

(148) 0x41e572 MOVQ	%XMM0,%RAX

(148) 0x41e577 PSHUFD	$-0x12,%XMM0,%XMM0

(148) 0x41e57c MOVQ	%XMM0,%RDX

(148) 0x41e581 MOVLPD	%XMM2,(%RAX)

(148) 0x41e585 MOVHPD	%XMM2,(%RDX)

(148) 0x41e589 MOVDQA	-0x220(%RBP),%XMM3

(148) 0x41e591 PADDQ	0x7ceb7(%RIP),%XMM3

(148) 0x41e599 ADD	$0x2,%RSI

(148) 0x41e59d CMP	%R15,%RSI

(148) 0x41e5a0 JAE	41ec66

(148) 0x41e5a6 MOV	%R11,%R9

(148) 0x41e5a9 MOVQ	%XMM3,%RAX

(148) 0x41e5ae XOR	%EDX,%EDX

(148) 0x41e5b0 DIVQ	-0xc8(%RBP)

(148) 0x41e5b7 MOVQ	%RAX,%XMM0

(148) 0x41e5bc PSHUFD	$-0x12,%XMM3,%XMM1

(148) 0x41e5c1 MOVQ	%XMM1,%RAX

(148) 0x41e5c6 XOR	%EDX,%EDX

(148) 0x41e5c8 DIVQ	-0xc0(%RBP)

(148) 0x41e5cf MOVQ	%RAX,%XMM1

(148) 0x41e5d4 PUNPCKLQDQ	%XMM1,%XMM0

(148) 0x41e5d8 PSHUFD	$-0x18,%XMM0,%XMM2

(148) 0x41e5dd PADDD	-0x1a0(%RBP),%XMM2

(148) 0x41e5e5 PMULUDQ	-0x1b0(%RBP),%XMM0

(148) 0x41e5ed MOVDQA	%XMM3,-0x220(%RBP)

(148) 0x41e5f5 MOVDQA	%XMM3,%XMM1

(148) 0x41e5f9 PSUBQ	%XMM0,%XMM1

(148) 0x41e5fd PADDQ	-0x190(%RBP),%XMM1

(148) 0x41e605 PSLLQ	$0x20,%XMM1

(148) 0x41e60a PSHUFD	$-0x13,%XMM1,%XMM14

(148) 0x41e610 MOVDQA	%XMM14,%XMM0

(148) 0x41e615 PSRAD	$0x1f,%XMM0

(148) 0x41e61a PUNPCKLDQ	%XMM0,%XMM14

(148) 0x41e61f PXOR	%XMM11,%XMM11

(148) 0x41e624 PCMPGTD	%XMM2,%XMM11

(148) 0x41e629 MOVDQA	%XMM2,%XMM4

(148) 0x41e62d PUNPCKLDQ	%XMM11,%XMM4

(148) 0x41e632 MOVDQA	-0x180(%RBP),%XMM3

(148) 0x41e63a MOVDQA	%XMM3,%XMM0

(148) 0x41e63e PMULUDQ	%XMM4,%XMM0

(148) 0x41e642 MOVDQA	-0x110(%RBP),%XMM1

(148) 0x41e64a PMULUDQ	%XMM4,%XMM1

(148) 0x41e64e MOVDQA	%XMM4,%XMM6

(148) 0x41e652 PUNPCKLDQ	%XMM10,%XMM11

(148) 0x41e657 PMULUDQ	%XMM11,%XMM3

(148) 0x41e65c PADDQ	%XMM1,%XMM3

(148) 0x41e660 PSLLQ	$0x20,%XMM3

(148) 0x41e665 PADDQ	%XMM0,%XMM3

(148) 0x41e669 PADDQ	%XMM14,%XMM3

(148) 0x41e66e PSLLQ	$0x3,%XMM3

(148) 0x41e673 PADDQ	-0x100(%RBP),%XMM3

(148) 0x41e67b MOVQ	%XMM3,%RAX

(148) 0x41e680 PSHUFD	$-0x12,%XMM3,%XMM0

(148) 0x41e685 MOVQ	%XMM0,%RDX

(148) 0x41e68a MOVSD	(%RAX),%XMM0

(148) 0x41e68e MOVHPD	(%RDX),%XMM0

(148) 0x41e692 PXOR	%XMM4,%XMM4

(148) 0x41e696 CMPPD	$0x1,%XMM0,%XMM4

(148) 0x41e69b MOVAPD	%XMM0,%XMM7

(148) 0x41e69f MOVAPD	%XMM0,-0x1f0(%RBP)

(148) 0x41e6a7 MOVDQA	%XMM2,%XMM0

(148) 0x41e6ab PCMPEQD	%XMM3,%XMM3

(148) 0x41e6af PADDD	%XMM3,%XMM0

(148) 0x41e6b3 MOVDQA	%XMM2,%XMM1

(148) 0x41e6b7 PSUBD	%XMM3,%XMM1

(148) 0x41e6bb MOVDQA	%XMM1,%XMM5

(148) 0x41e6bf MOVDQA	-0x170(%RBP),%XMM3

(148) 0x41e6c7 PCMPGTD	%XMM3,%XMM5

(148) 0x41e6cb PAND	%XMM5,%XMM3

(148) 0x41e6cf PANDN	%XMM1,%XMM5

(148) 0x41e6d3 POR	%XMM3,%XMM5

(148) 0x41e6d7 PXOR	%XMM1,%XMM1

(148) 0x41e6db PCMPGTD	%XMM0,%XMM1

(148) 0x41e6df PUNPCKLDQ	%XMM1,%XMM0

(148) 0x41e6e3 PXOR	%XMM1,%XMM1

(148) 0x41e6e7 PCMPGTD	%XMM5,%XMM1

(148) 0x41e6eb PUNPCKLDQ	%XMM1,%XMM5

(148) 0x41e6ef PADDD	0x7ced9(%RIP),%XMM2

(148) 0x41e6f7 PXOR	%XMM1,%XMM1

(148) 0x41e6fb PCMPGTD	%XMM2,%XMM1

(148) 0x41e6ff PUNPCKLDQ	%XMM1,%XMM2

(148) 0x41e703 MOVAPD	%XMM4,%XMM3

(148) 0x41e707 ANDNPD	%XMM5,%XMM3

(148) 0x41e70b PAND	%XMM4,%XMM2

(148) 0x41e70f POR	%XMM3,%XMM2

(148) 0x41e713 MOVDQA	%XMM4,%XMM1

(148) 0x41e717 PANDN	%XMM0,%XMM1

(148) 0x41e71b PAND	%XMM4,%XMM0

(148) 0x41e71f POR	%XMM0,%XMM3

(148) 0x41e723 MOVDQA	%XMM6,%XMM13

(148) 0x41e728 PAND	%XMM4,%XMM13

(148) 0x41e72d POR	%XMM1,%XMM13

(148) 0x41e732 PANDN	%XMM6,%XMM4

(148) 0x41e736 MOVDQA	%XMM6,%XMM9

(148) 0x41e73b MOVDQA	%XMM6,-0xb0(%RBP)

(148) 0x41e743 POR	%XMM0,%XMM4

(148) 0x41e747 MOVAPD	%XMM7,%XMM5

(148) 0x41e74b ANDPD	%XMM12,%XMM5

(148) 0x41e750 MOVDQA	-0x160(%RBP),%XMM7

(148) 0x41e758 MOVDQA	%XMM7,%XMM0

(148) 0x41e75c PSRLQ	$0x20,%XMM0

(148) 0x41e761 PMULUDQ	%XMM4,%XMM0

(148) 0x41e765 MOVDQA	%XMM4,%XMM1

(148) 0x41e769 PSRLQ	$0x20,%XMM1

(148) 0x41e76e MOVDQA	%XMM7,%XMM6

(148) 0x41e772 PMULUDQ	%XMM1,%XMM6

(148) 0x41e776 MOVDQA	%XMM1,%XMM8

(148) 0x41e77b MOVDQA	%XMM1,-0x1e0(%RBP)

(148) 0x41e783 PADDQ	%XMM0,%XMM6

(148) 0x41e787 PSLLQ	$0x20,%XMM6

(148) 0x41e78c MOVDQA	%XMM7,%XMM0

(148) 0x41e790 PMULUDQ	%XMM4,%XMM0

(148) 0x41e794 PADDQ	%XMM14,%XMM0

(148) 0x41e799 PADDQ	%XMM6,%XMM0

(148) 0x41e79d PSLLQ	$0x3,%XMM0

(148) 0x41e7a2 MOVQ	-0x48(%RBP),%XMM6

(148) 0x41e7a7 PSHUFD	$0x44,%XMM6,%XMM6

(148) 0x41e7ac PADDQ	%XMM0,%XMM6

(148) 0x41e7b0 MOVQ	%XMM6,%RDX

(148) 0x41e7b5 PSHUFD	$-0x12,%XMM6,%XMM0

(148) 0x41e7ba MOVQ	%XMM0,%RAX

(148) 0x41e7bf MOVSD	(%RDX),%XMM0

(148) 0x41e7c3 MOVHPD	(%RAX),%XMM0

(148) 0x41e7c7 DIVPD	%XMM0,%XMM5

(148) 0x41e7cb MOVAPD	%XMM5,%XMM0

(148) 0x41e7cf MOVDQA	%XMM9,%XMM6

(148) 0x41e7d4 PSLLQ	$0x3,%XMM6

(148) 0x41e7d9 MOVQ	-0x90(%RBP),%XMM7

(148) 0x41e7e1 PSHUFD	$0x44,%XMM7,%XMM7

(148) 0x41e7e6 PADDQ	%XMM7,%XMM6

(148) 0x41e7ea MOVQ	%XMM6,%RDI

(148) 0x41e7ef PSHUFD	$-0x12,%XMM6,%XMM6

(148) 0x41e7f4 MOVQ	%XMM6,%RBX

(148) 0x41e7f9 MOVSD	(%RDI),%XMM1

(148) 0x41e7fd MOVHPD	(%RBX),%XMM1

(148) 0x41e801 MOVAPD	0x7cdd6(%RIP),%XMM12

(148) 0x41e80a ADDPD	%XMM12,%XMM0

(148) 0x41e80f MULPD	%XMM0,%XMM1

(148) 0x41e813 PSLLQ	$0x3,%XMM3

(148) 0x41e818 PADDQ	%XMM7,%XMM3

(148) 0x41e81c MOVQ	%XMM3,%RDI

(148) 0x41e821 PSHUFD	$-0x12,%XMM3,%XMM0

(148) 0x41e826 MOVQ	%XMM0,%RBX

(148) 0x41e82b MOVSD	(%RDI),%XMM6

(148) 0x41e82f MOVHPD	(%RBX),%XMM6

(148) 0x41e833 MOVDQA	-0x150(%RBP),%XMM9

(148) 0x41e83c MOVDQA	%XMM9,%XMM3

(148) 0x41e841 PSRLQ	$0x20,%XMM3

(148) 0x41e846 MOVDQA	%XMM3,%XMM0

(148) 0x41e84a PMULUDQ	%XMM4,%XMM0

(148) 0x41e84e MOVDQA	%XMM9,%XMM7

(148) 0x41e853 PMULUDQ	%XMM8,%XMM7

(148) 0x41e858 PADDQ	%XMM0,%XMM7

(148) 0x41e85c PSLLQ	$0x20,%XMM7

(148) 0x41e861 MOVDQA	%XMM9,%XMM0

(148) 0x41e866 PMULUDQ	%XMM4,%XMM0

(148) 0x41e86a PADDQ	%XMM14,%XMM0

(148) 0x41e86f PADDQ	%XMM7,%XMM0

(148) 0x41e873 PSLLQ	$0x3,%XMM0

(148) 0x41e878 MOVQ	%R12,%XMM7

(148) 0x41e87d PSHUFD	$0x44,%XMM7,%XMM7

(148) 0x41e882 PADDQ	%XMM7,%XMM0

(148) 0x41e886 MOVQ	%XMM0,%RDI

(148) 0x41e88b PSHUFD	$-0x12,%XMM0,%XMM0

(148) 0x41e890 MOVQ	%XMM0,%RBX

(148) 0x41e895 MOVDQA	%XMM3,%XMM0

(148) 0x41e899 PMULUDQ	%XMM2,%XMM0

(148) 0x41e89d MOVDQA	%XMM2,%XMM15

(148) 0x41e8a2 PSRLQ	$0x20,%XMM15

(148) 0x41e8a8 MOVDQA	%XMM9,%XMM8

(148) 0x41e8ad PMULUDQ	%XMM15,%XMM8

(148) 0x41e8b2 PADDQ	%XMM0,%XMM8

(148) 0x41e8b7 PSLLQ	$0x20,%XMM8

(148) 0x41e8bd MOVDQA	%XMM9,%XMM10

(148) 0x41e8c2 PMULUDQ	%XMM2,%XMM10

(148) 0x41e8c7 MOVDQA	%XMM14,-0x1d0(%RBP)

(148) 0x41e8d0 PADDQ	%XMM14,%XMM10

(148) 0x41e8d5 PADDQ	%XMM8,%XMM10

(148) 0x41e8da MOVSD	(%RDI),%XMM0

(148) 0x41e8de MOVHPD	(%RBX),%XMM0

(148) 0x41e8e2 PSLLQ	$0x3,%XMM10

(148) 0x41e8e8 PADDQ	%XMM7,%XMM10

(148) 0x41e8ed MOVQ	%XMM10,%R14

(148) 0x41e8f2 PSHUFD	$-0x12,%XMM10,%XMM8

(148) 0x41e8f8 MOVQ	%XMM8,%R13

(148) 0x41e8fd MOVSD	(%R14),%XMM8

(148) 0x41e902 MOVHPD	(%R13),%XMM8

(148) 0x41e908 DIVPD	%XMM6,%XMM1

(148) 0x41e90c MOVAPD	%XMM0,%XMM10

(148) 0x41e911 MOVAPD	%XMM0,-0x1c0(%RBP)

(148) 0x41e919 SUBPD	%XMM8,%XMM10

(148) 0x41e91e PMULUDQ	%XMM13,%XMM3

(148) 0x41e923 MOVDQA	%XMM13,%XMM6

(148) 0x41e928 PSRLQ	$0x20,%XMM6

(148) 0x41e92d MOVDQA	%XMM9,%XMM8

(148) 0x41e932 PMULUDQ	%XMM6,%XMM8

(148) 0x41e937 PADDQ	%XMM3,%XMM8

(148) 0x41e93c PSLLQ	$0x20,%XMM8

(148) 0x41e942 MOVDQA	%XMM9,%XMM3

(148) 0x41e947 PMULUDQ	%XMM13,%XMM3

(148) 0x41e94c PADDQ	%XMM14,%XMM3

(148) 0x41e951 PADDQ	%XMM8,%XMM3

(148) 0x41e956 PSLLQ	$0x3,%XMM3

(148) 0x41e95b PADDQ	%XMM7,%XMM3

(148) 0x41e95f MOVQ	%XMM3,%R14

(148) 0x41e964 PSHUFD	$-0x12,%XMM3,%XMM3

(148) 0x41e969 MOVQ	%XMM3,%R13

(148) 0x41e96e MOVSD	(%R14),%XMM9

(148) 0x41e973 MOVHPD	(%R13),%XMM9

(148) 0x41e979 SUBPD	%XMM0,%XMM9

(148) 0x41e97e MOVAPD	%XMM9,%XMM8

(148) 0x41e983 MULPD	%XMM10,%XMM8

(148) 0x41e988 PXOR	%XMM7,%XMM7

(148) 0x41e98c CMPPD	$0x1,%XMM8,%XMM7

(148) 0x41e992 MOVAPD	0x7c156(%RIP),%XMM0

(148) 0x41e99a ANDPD	%XMM0,%XMM10

(148) 0x41e99f MOVAPD	%XMM9,%XMM3

(148) 0x41e9a4 ANDPD	%XMM0,%XMM3

(148) 0x41e9a8 MOVAPD	%XMM12,%XMM0

(148) 0x41e9ad MOVAPD	%XMM3,%XMM14

(148) 0x41e9b2 MINPD	%XMM10,%XMM14

(148) 0x41e9b7 MOVAPD	%XMM10,%XMM8

(148) 0x41e9bc CMPPD	$0x3,%XMM10,%XMM8

(148) 0x41e9c2 MOVAPD	%XMM3,%XMM12

(148) 0x41e9c7 ANDPD	%XMM8,%XMM12

(148) 0x41e9cc ANDNPD	%XMM14,%XMM8

(148) 0x41e9d1 MOVAPD	%XMM0,%XMM14

(148) 0x41e9d6 ORPD	%XMM12,%XMM8

(148) 0x41e9db MOVAPD	0x7cc0d(%RIP),%XMM0

(148) 0x41e9e3 SUBPD	%XMM5,%XMM0

(148) 0x41e9e7 MOVAPD	%XMM0,-0x200(%RBP)

(148) 0x41e9ef MULPD	%XMM0,%XMM3

(148) 0x41e9f3 MOVAPD	%XMM1,-0x210(%RBP)

(148) 0x41e9fb MULPD	%XMM1,%XMM10

(148) 0x41ea00 ADDPD	%XMM3,%XMM10

(148) 0x41ea05 MULPD	0x7cbf2(%RIP),%XMM10

(148) 0x41ea0e MOVAPD	%XMM10,%XMM3

(148) 0x41ea13 MINPD	%XMM8,%XMM3

(148) 0x41ea18 CMPPD	$0x3,%XMM8,%XMM8

(148) 0x41ea1e ANDPD	%XMM8,%XMM10

(148) 0x41ea23 ANDNPD	%XMM3,%XMM8

(148) 0x41ea28 ORPD	%XMM10,%XMM8

(148) 0x41ea2d XORPD	%XMM10,%XMM10

(148) 0x41ea32 CMPPD	$0x6,%XMM10,%XMM9

(148) 0x41ea38 MOVAPD	%XMM14,%XMM3

(148) 0x41ea3d SUBPD	%XMM5,%XMM3

(148) 0x41ea41 SUBPD	%XMM14,%XMM5

(148) 0x41ea46 ANDPD	%XMM9,%XMM3

(148) 0x41ea4b ANDNPD	%XMM5,%XMM9

(148) 0x41ea50 ORPD	%XMM3,%XMM9

(148) 0x41ea55 MULPD	%XMM8,%XMM9

(148) 0x41ea5a ANDPD	%XMM7,%XMM9

(148) 0x41ea5f ADDPD	-0x1c0(%RBP),%XMM9

(148) 0x41ea68 MULPD	-0x1f0(%RBP),%XMM9

(148) 0x41ea71 MOVDQA	-0x140(%RBP),%XMM1

(148) 0x41ea79 MOVDQA	%XMM1,%XMM0

(148) 0x41ea7d PSRLQ	$0x20,%XMM0

(148) 0x41ea82 MOVDQA	-0xb0(%RBP),%XMM3

(148) 0x41ea8a PMULUDQ	%XMM3,%XMM0

(148) 0x41ea8e PMULUDQ	%XMM1,%XMM11

(148) 0x41ea93 PADDQ	%XMM0,%XMM11

(148) 0x41ea98 MOVDQA	%XMM1,%XMM0

(148) 0x41ea9c PMULUDQ	%XMM3,%XMM0

(148) 0x41eaa0 PSLLQ	$0x20,%XMM11

(148) 0x41eaa6 PADDQ	%XMM0,%XMM11

(148) 0x41eaab MOVDQA	-0x1d0(%RBP),%XMM7

(148) 0x41eab3 PADDQ	%XMM7,%XMM11

(148) 0x41eab8 PSLLQ	$0x3,%XMM11

(148) 0x41eabe MOVQ	-0x88(%RBP),%XMM0

(148) 0x41eac6 PSHUFD	$0x44,%XMM0,%XMM0

(148) 0x41eacb PADDQ	%XMM11,%XMM0

(148) 0x41ead0 MOVQ	%XMM0,%R14

(148) 0x41ead5 PSHUFD	$-0x12,%XMM0,%XMM0

(148) 0x41eada MOVQ	%XMM0,%R13

(148) 0x41eadf MOVDQA	-0x130(%RBP),%XMM3

(148) 0x41eae7 MOVDQA	%XMM3,%XMM8

(148) 0x41eaec PSRLQ	$0x20,%XMM8

(148) 0x41eaf2 MOVDQA	%XMM8,%XMM0

(148) 0x41eaf7 PMULUDQ	%XMM4,%XMM0

(148) 0x41eafb MOVDQA	-0x1e0(%RBP),%XMM1

(148) 0x41eb03 PMULUDQ	%XMM3,%XMM1

(148) 0x41eb07 PADDQ	%XMM0,%XMM1

(148) 0x41eb0b PSLLQ	$0x20,%XMM1

(148) 0x41eb10 PMULUDQ	%XMM3,%XMM4

(148) 0x41eb14 PADDQ	%XMM7,%XMM4

(148) 0x41eb18 PADDQ	%XMM1,%XMM4

(148) 0x41eb1c PSLLQ	$0x3,%XMM4

(148) 0x41eb21 MOVQ	-0x80(%RBP),%XMM0

(148) 0x41eb26 PSHUFD	$0x44,%XMM0,%XMM5

(148) 0x41eb2b PADDQ	%XMM5,%XMM4

(148) 0x41eb2f MOVQ	%XMM4,%R10

(148) 0x41eb34 PSHUFD	$-0x12,%XMM4,%XMM0

(148) 0x41eb39 MOVQ	%XMM0,%R11

(148) 0x41eb3e MOVDQA	%XMM8,%XMM0

(148) 0x41eb43 PMULUDQ	%XMM2,%XMM0

(148) 0x41eb47 PMULUDQ	%XMM3,%XMM15

(148) 0x41eb4c PADDQ	%XMM0,%XMM15

(148) 0x41eb51 MOVLPD	%XMM9,(%R14)

(148) 0x41eb56 MOVHPD	%XMM9,(%R13)

(148) 0x41eb5c PSLLQ	$0x20,%XMM15

(148) 0x41eb62 PMULUDQ	%XMM3,%XMM2

(148) 0x41eb66 PADDQ	%XMM7,%XMM2

(148) 0x41eb6a PADDQ	%XMM15,%XMM2

(148) 0x41eb6f MOVSD	(%R10),%XMM1

(148) 0x41eb74 MOVHPD	(%R11),%XMM1

(148) 0x41eb79 PSLLQ	$0x3,%XMM2

(148) 0x41eb7e PADDQ	%XMM5,%XMM2

(148) 0x41eb82 MOVQ	%XMM2,%R10

(148) 0x41eb87 PSHUFD	$-0x12,%XMM2,%XMM0

(148) 0x41eb8c MOVQ	%XMM0,%R11

(148) 0x41eb91 PMULUDQ	%XMM13,%XMM8

(148) 0x41eb96 PMULUDQ	%XMM3,%XMM6

(148) 0x41eb9a PADDQ	%XMM8,%XMM6

(148) 0x41eb9f MOVDQA	%XMM7,%XMM8

(148) 0x41eba4 MOVSD	(%R10),%XMM0

(148) 0x41eba9 MOVHPD	(%R11),%XMM0

(148) 0x41ebae PSLLQ	$0x20,%XMM6

(148) 0x41ebb3 PMULUDQ	%XMM3,%XMM13

(148) 0x41ebb8 PADDQ	%XMM7,%XMM13

(148) 0x41ebbd PADDQ	%XMM6,%XMM13

(148) 0x41ebc2 MOVAPD	%XMM1,%XMM4

(148) 0x41ebc6 PSLLQ	$0x3,%XMM13

(148) 0x41ebcc PADDQ	%XMM5,%XMM13

(148) 0x41ebd1 MOVQ	%XMM13,%R10

(148) 0x41ebd6 PSHUFD	$-0x12,%XMM13,%XMM2

(148) 0x41ebdc MOVQ	%XMM2,%R11

(148) 0x41ebe1 MOVSD	(%R10),%XMM5

(148) 0x41ebe6 MOVHPD	(%R11),%XMM5

(148) 0x41ebeb SUBPD	%XMM0,%XMM4

(148) 0x41ebef SUBPD	%XMM1,%XMM5

(148) 0x41ebf3 MOVAPD	%XMM5,%XMM0

(148) 0x41ebf7 MULPD	%XMM4,%XMM0

(148) 0x41ebfb PXOR	%XMM2,%XMM2

(148) 0x41ebff CMPPD	$0x1,%XMM0,%XMM2

(148) 0x41ec04 MOVMSKPD	%XMM2,%R14D

(148) 0x41ec09 TEST	$0x1,%R14B

(148) 0x41ec0d JE	41ec13

(148) 0x41ec0f MOVSD	(%RDX),%XMM6

(148) 0x41ec13 TEST	$0x2,%R14B

(148) 0x41ec17 JE	41ec1d

(148) 0x41ec19 MOVHPD	(%RAX),%XMM6

(148) 0x41ec1d MOV	%R9,%R11

(148) 0x41ec20 MOVAPD	0x7bec7(%RIP),%XMM12

(148) 0x41ec29 TEST	$0x1,%R14B

(148) 0x41ec2d MOV	-0x68(%RBP),%R9

(148) 0x41ec31 JE	41ec37

(148) 0x41ec33 MOVSD	(%RDI),%XMM7

(148) 0x41ec37 MOVAPD	%XMM9,%XMM0

(148) 0x41ec3c ANDPD	%XMM12,%XMM0

(148) 0x41ec41 TEST	$0x2,%R14B

(148) 0x41ec45 JE	41e470

(148) 0x41ec4b MOVHPD	(%RBX),%XMM7

(148) 0x41ec4f JMP	41e470

0x41ec54 ADD	$0x1f8,%RSP

0x41ec5b POP	%RBX

0x41ec5c POP	%R12

0x41ec5e POP	%R13

0x41ec60 POP	%R14

0x41ec62 POP	%R15

0x41ec64 POP	%RBP

0x41ec65 RET

0x41ec66 CMP	%R15,-0xb8(%RBP)

0x41ec6d JNE	41ec92

0x41ec6f MOV	$0x4b74b0,%EDI

0x41ec74 MOV	-0x4c(%RBP),%ESI

0x41ec77 ADD	$0x1f8,%RSP

0x41ec7e POP	%RBX

0x41ec7f POP	%R12

0x41ec81 POP	%R13

0x41ec83 POP	%R14

0x41ec85 POP	%R15

0x41ec87 POP	%RBP

0x41ec88 JMP	403050

0x41ec8d MOV	%R10,%RBX

0x41ec90 JMP	41ec95

0x41ec92 ADD	%R15,%RCX

0x41ec95 PXOR	%XMM0,%XMM0

0x41ec99 MOVSD	0x7bdf7(%RIP),%XMM2

0x41eca1 MOVSD	0x7c977(%RIP),%XMM3

0x41eca9 MOVAPD	0x7be3f(%RIP),%XMM5

0x41ecb1 MOVSD	0x7c96f(%RIP),%XMM6

0x41ecb9 JMP	41ecf7

0x41ecbb NOPL	(%RAX,%RAX,1)

(147) 0x41ecc0 ADDSD	%XMM9,%XMM11

(147) 0x41ecc5 MULSD	%XMM10,%XMM11

(147) 0x41ecca IMUL	-0x60(%RBP),%R14

(147) 0x41eccf ADD	%RDX,%R14

(147) 0x41ecd2 MOV	-0x78(%RBP),%RAX

(147) 0x41ecd6 MOVSD	%XMM11,(%RAX,%R14,8)

(147) 0x41ecdc INC	%RCX

(147) 0x41ecdf CMP	%RCX,-0xe0(%RBP)

(147) 0x41ece6 MOV	-0x38(%RBP),%RDI

(147) 0x41ecea MOV	-0x30(%RBP),%RBX

(147) 0x41ecee MOV	%R15,%R8

(147) 0x41ecf1 JE	41ec6f

(147) 0x41ecf7 MOV	%RCX,%RAX

(147) 0x41ecfa SHR	$0x20,%RAX

(147) 0x41ecfe JE	41ed10

(147) 0x41ed00 MOV	%RCX,%RAX

(147) 0x41ed03 XOR	%EDX,%EDX

(147) 0x41ed05 DIV	%R11

(147) 0x41ed08 JMP	41ed17

0x41ed0a NOPW	(%RAX,%RAX,1)

(147) 0x41ed10 MOV	%ECX,%EAX

(147) 0x41ed12 XOR	%EDX,%EDX

(147) 0x41ed14 DIV	%R11D

(147) 0x41ed17 MOV	-0x70(%RBP),%R10

(147) 0x41ed1b LEA	(%RAX,%R10,1),%ESI

(147) 0x41ed1f ADD	%R9D,%EDX

(147) 0x41ed22 MOVSXD	%EDX,%RDX

(147) 0x41ed25 MOVSXD	%ESI,%R14

(147) 0x41ed28 IMUL	%R14,%RDI

(147) 0x41ed2c ADD	%RDX,%RDI

(147) 0x41ed2f MOVSD	(%RBX,%RDI,8),%XMM9

(147) 0x41ed35 UCOMISD	%XMM0,%XMM9

(147) 0x41ed3a LEA	-0x1(%RAX,%R10,1),%EAX

(147) 0x41ed3f JBE	41ed60

(147) 0x41ed41 ADD	$-0x2,%ESI

(147) 0x41ed44 MOVSXD	%EAX,%R13

(147) 0x41ed47 MOVSXD	%ESI,%RDI

(147) 0x41ed4a MOV	%R14,%RAX

(147) 0x41ed4d MOV	%R13,%RSI

(147) 0x41ed50 JMP	41ed76

0x41ed52 NOPW	%CS:(%RAX,%RAX,1)

(147) 0x41ed60 INC	%ESI

(147) 0x41ed62 MOV	-0x40(%RBP),%RDI

(147) 0x41ed66 CMP	%ESI,%EDI

(147) 0x41ed68 CMOVL	%EDI,%ESI

(147) 0x41ed6b CLTQ

(147) 0x41ed6d MOVSXD	%ESI,%RDI

(147) 0x41ed70 MOV	%RDI,%R13

(147) 0x41ed73 MOV	%R14,%RSI

(147) 0x41ed76 MOV	-0x58(%RBP),%RBX

(147) 0x41ed7a MOVAPD	%XMM9,%XMM1

(147) 0x41ed7f ANDPD	0x7bd69(%RIP),%XMM1

(147) 0x41ed87 IMUL	%RSI,%RBX

(147) 0x41ed8b ADD	%RDX,%RBX

(147) 0x41ed8e MOV	-0x48(%RBP),%R10

(147) 0x41ed92 DIVSD	(%R10,%RBX,8),%XMM1

(147) 0x41ed98 MOVAPD	%XMM1,%XMM7

(147) 0x41ed9c ADDSD	%XMM2,%XMM7

(147) 0x41eda0 MOV	-0x90(%RBP),%R10

(147) 0x41eda7 MULSD	(%R10,%R14,8),%XMM7

(147) 0x41edad DIVSD	(%R10,%R13,8),%XMM7

(147) 0x41edb3 MOVAPD	%XMM3,%XMM8

(147) 0x41edb8 MOV	%R8,%R13

(147) 0x41edbb IMUL	%RSI,%R13

(147) 0x41edbf ADD	%RDX,%R13

(147) 0x41edc2 MOVSD	(%R12,%R13,8),%XMM12

(147) 0x41edc8 MOV	%R8,%R10

(147) 0x41edcb IMUL	%RDI,%R10

(147) 0x41edcf ADD	%RDX,%R10

(147) 0x41edd2 MOVAPD	%XMM12,%XMM14

(147) 0x41edd7 SUBSD	(%R12,%R10,8),%XMM14

(147) 0x41eddd SUBSD	%XMM1,%XMM8

(147) 0x41ede2 MOV	%R8,%R15

(147) 0x41ede5 MOV	%R8,%R10

(147) 0x41ede8 IMUL	%RAX,%R10

(147) 0x41edec ADD	%RDX,%R10

(147) 0x41edef MOVSD	(%R12,%R10,8),%XMM15

(147) 0x41edf5 SUBSD	%XMM12,%XMM15

(147) 0x41edfa MOVAPD	%XMM15,%XMM10

(147) 0x41edff MULSD	%XMM14,%XMM10

(147) 0x41ee04 PXOR	%XMM11,%XMM11

(147) 0x41ee09 UCOMISD	%XMM11,%XMM10

(147) 0x41ee0e XORPD	%XMM10,%XMM10

(147) 0x41ee13 JBE	41eeba

(147) 0x41ee19 MOVAPD	%XMM2,%XMM10

(147) 0x41ee1e SUBSD	%XMM1,%XMM10

(147) 0x41ee23 MOVAPD	%XMM15,%XMM1

(147) 0x41ee28 CMPSD	$0x6,%XMM0,%XMM1

(147) 0x41ee2d MOVAPD	%XMM1,%XMM13

(147) 0x41ee32 ANDPD	%XMM10,%XMM13

(147) 0x41ee37 XORPD	0x7c7d0(%RIP),%XMM10

(147) 0x41ee40 ANDNPD	%XMM10,%XMM1

(147) 0x41ee45 ORPD	%XMM13,%XMM1

(147) 0x41ee4a ANDPD	%XMM5,%XMM14

(147) 0x41ee4f ANDPD	%XMM5,%XMM15

(147) 0x41ee54 MOVAPD	%XMM14,%XMM10

(147) 0x41ee59 CMPSD	$0x3,%XMM14,%XMM10

(147) 0x41ee5f MOVAPD	%XMM10,%XMM4

(147) 0x41ee64 ANDPD	%XMM15,%XMM4

(147) 0x41ee69 MOVAPD	%XMM15,%XMM13

(147) 0x41ee6e MINSD	%XMM14,%XMM13

(147) 0x41ee73 ANDNPD	%XMM13,%XMM10

(147) 0x41ee78 ORPD	%XMM4,%XMM10

(147) 0x41ee7d MULSD	%XMM7,%XMM14

(147) 0x41ee82 MULSD	%XMM8,%XMM15

(147) 0x41ee87 ADDSD	%XMM14,%XMM15

(147) 0x41ee8c MULSD	%XMM6,%XMM15

(147) 0x41ee91 MOVAPD	%XMM15,%XMM4

(147) 0x41ee96 MINSD	%XMM10,%XMM4

(147) 0x41ee9b CMPSD	$0x3,%XMM10,%XMM10

(147) 0x41eea1 MOVAPD	%XMM10,%XMM13

(147) 0x41eea6 ANDNPD	%XMM4,%XMM13

(147) 0x41eeab ANDPD	%XMM15,%XMM10

(147) 0x41eeb0 ORPD	%XMM13,%XMM10

(147) 0x41eeb5 MULSD	%XMM1,%XMM10

(147) 0x41eeba ADDSD	%XMM12,%XMM10

(147) 0x41eebf MULSD	%XMM9,%XMM10

(147) 0x41eec4 MOV	-0xd8(%RBP),%R10

(147) 0x41eecb IMUL	%R14,%R10

(147) 0x41eecf ADD	%RDX,%R10

(147) 0x41eed2 MOV	-0x88(%RBP),%R8

(147) 0x41eed9 MOVSD	%XMM10,(%R8,%R10,8)

(147) 0x41eedf MOV	-0xd0(%RBP),%R8

(147) 0x41eee6 IMUL	%R8,%RSI

(147) 0x41eeea ADD	%RDX,%RSI

(147) 0x41eeed MOV	-0x80(%RBP),%R10

(147) 0x41eef1 MOVSD	(%R10,%RSI,8),%XMM9

(147) 0x41eef7 IMUL	%R8,%RDI

(147) 0x41eefb ADD	%RDX,%RDI

(147) 0x41eefe MOVAPD	%XMM9,%XMM13

(147) 0x41ef03 SUBSD	(%R10,%RDI,8),%XMM13

(147) 0x41ef09 IMUL	%R8,%RAX

(147) 0x41ef0d ADD	%RDX,%RAX

(147) 0x41ef10 MOVSD	(%R10,%RAX,8),%XMM12

(147) 0x41ef16 SUBSD	%XMM9,%XMM12

(147) 0x41ef1b MOVAPD	%XMM12,%XMM1

(147) 0x41ef20 MULSD	%XMM13,%XMM1

(147) 0x41ef25 UCOMISD	%XMM11,%XMM1

(147) 0x41ef2a JBE	41ecc0

(147) 0x41ef30 MOVAPD	%XMM10,%XMM1

(147) 0x41ef35 ANDPD	%XMM5,%XMM1

(147) 0x41ef39 MOV	-0x48(%RBP),%RAX

(147) 0x41ef3d MOVSD	(%RAX,%RBX,8),%XMM4

(147) 0x41ef42 MULSD	(%R12,%R13,8),%XMM4

(147) 0x41ef48 DIVSD	%XMM4,%XMM1

(147) 0x41ef4c MOVAPD	%XMM2,%XMM4

(147) 0x41ef50 SUBSD	%XMM1,%XMM4

(147) 0x41ef54 MOVAPD	%XMM12,%XMM14

(147) 0x41ef59 CMPSD	$0x6,%XMM0,%XMM14

(147) 0x41ef5f MOVAPD	%XMM14,%XMM1

(147) 0x41ef64 ANDPD	%XMM4,%XMM1

(147) 0x41ef68 XORPD	0x7c6a0(%RIP),%XMM4

(147) 0x41ef70 ANDNPD	%XMM4,%XMM14

(147) 0x41ef75 ORPD	%XMM1,%XMM14

(147) 0x41ef7a ANDPD	%XMM5,%XMM13

(147) 0x41ef7f ANDPD	%XMM5,%XMM12

(147) 0x41ef84 MOVAPD	%XMM13,%XMM11

(147) 0x41ef89 CMPSD	$0x3,%XMM13,%XMM11

(147) 0x41ef8f MOVAPD	%XMM11,%XMM1

(147) 0x41ef94 ANDPD	%XMM12,%XMM1

(147) 0x41ef99 MOVAPD	%XMM12,%XMM4

(147) 0x41ef9e MINSD	%XMM13,%XMM4

(147) 0x41efa3 ANDNPD	%XMM4,%XMM11

(147) 0x41efa8 ORPD	%XMM1,%XMM11

(147) 0x41efad MULSD	%XMM7,%XMM13

(147) 0x41efb2 MULSD	%XMM8,%XMM12

(147) 0x41efb7 ADDSD	%XMM13,%XMM12

(147) 0x41efbc MULSD	%XMM6,%XMM12

(147) 0x41efc1 MOVAPD	%XMM12,%XMM1

(147) 0x41efc6 MINSD	%XMM11,%XMM1

(147) 0x41efcb CMPSD	$0x3,%XMM11,%XMM11

(147) 0x41efd1 MOVAPD	%XMM11,%XMM4

(147) 0x41efd6 ANDNPD	%XMM1,%XMM4

(147) 0x41efda ANDPD	%XMM12,%XMM11

(147) 0x41efdf ORPD	%XMM4,%XMM11

(147) 0x41efe4 MULSD	%XMM14,%XMM11

(147) 0x41efe9 JMP	41ecc0

0x41efee XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_cell.cpp:157-202
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:157-202
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 28.17 to 12.00 cycles (2.35x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 28.17 to 3.37 cycles (8.35x speedup).

Details

31% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

17% of SSE/AVX loads are used in vector version.
30% of SSE/AVX stores are used in vector version.
11% of SSE/AVX addition or subtraction instructions are used in vector version.
45% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:157

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 320 bytes. The binary function is storing 400 bytes.

General properties

nb instructions	168
nb uops	169
loop length	802
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	44

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	28.17 cycles
front end	28.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.40	12.00	17.33	17.33	24.50	12.00	7.40	24.50	24.50	24.50	7.20	17.33
cycles	7.40	12.00	17.33	17.33	24.50	12.00	7.40	24.50	24.50	24.50	7.20	17.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	28.17
Dispatch	24.50
Overall L1	28.17

Vectorization ratios

INT

all	31%
load	8%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
other	45%

all	40%
load	40%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	31%
load	17%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

Vector efficiency ratios

INT

all	15%
load	11%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
other	17%

all	17%
load	17%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	15%
load	13%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.17 cycles. At this rate:

5% of peak load performance is reached (11.36 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (14.20 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 28.17 to 24.50 cycles (1.15x speedup).

ASM code

In the binary file, the address of the function is: 41e1d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x1f8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x40(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x28(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVL $0,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 41ec54 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0xa84>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xe8(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x50(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0xa0(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x98(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b7490,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x4c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x68(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0xa0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x98(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 41ec6f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0xa9f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R12,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %R9D,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%R15),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R15),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R13),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R13),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RAX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R14),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R14),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV $-0x2,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %RDX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 41ec8d <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0xabd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %R11D,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVD -0x70(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x1a0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R9,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x190(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RDI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVD %EAX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x170(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RSI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x160(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R8,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x150(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R13,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R14,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ %RAX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RCX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x7d027(%RIP),%XMM3	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOVQ %XMM1,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM1,-0x1b0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
PXOR %XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVDQA %XMM2,-0x180(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSRLQ $0x20,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM2,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R10,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVAPD 0x7c693(%RIP),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
JMP 41e5a6 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0x3d6>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x1f8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
CMP %R15,-0xb8(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 41ec92 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0xac2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b74b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x4c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x1f8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %R10,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 41ec95 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0xac5>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
ADD %R15,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PXOR %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD 0x7bdf7(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSD 0x7c977(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVAPD 0x7be3f(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVSD 0x7c96f(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 41ecf7 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0xb27>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_cell.cpp:157-202
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:157-202
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

31% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

17% of SSE/AVX loads are used in vector version.
30% of SSE/AVX stores are used in vector version.
11% of SSE/AVX addition or subtraction instructions are used in vector version.
45% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:157

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 320 bytes. The binary function is storing 400 bytes.

General properties

nb instructions	168
nb uops	169
loop length	802
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	44

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	28.17 cycles
front end	28.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.40	12.00	17.33	17.33	24.50	12.00	7.40	24.50	24.50	24.50	7.20	17.33
cycles	7.40	12.00	17.33	17.33	24.50	12.00	7.40	24.50	24.50	24.50	7.20	17.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	28.17
Dispatch	24.50
Overall L1	28.17

Vectorization ratios

INT

all	31%
load	8%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
other	45%

all	40%
load	40%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	31%
load	17%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

Vector efficiency ratios

INT

all	15%
load	11%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
other	17%

all	17%
load	17%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	15%
load	13%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.17 cycles. At this rate:

5% of peak load performance is reached (11.36 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (14.20 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 41e1d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x1f8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x40(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x28(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVL $0,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 41ec54 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0xa84>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xe8(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x50(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0xa0(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x98(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4b7490,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x4c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4031f0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x68(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0xa0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x98(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 41ec6f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0xa9f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R12,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %R9D,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%R15),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R15),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R13),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%R13),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RAX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R14),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R14),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV $-0x2,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %RDX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 41ec8d <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0xabd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVD %R11D,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVD -0x70(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x1a0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R9,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x190(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RDI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVD %EAX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x170(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RSI,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x160(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R8,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x150(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R13,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R14,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ %RAX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %RCX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
PADDQ 0x7d027(%RIP),%XMM3	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOVQ %XMM1,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM1,-0x1b0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVQ %XMM0,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
PXOR %XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVDQA %XMM2,-0x180(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
PSRLQ $0x20,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1-2	0.50	vect (25.0%)
MOVDQA %XMM2,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ %R10,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM0,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVAPD 0x7c693(%RIP),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
JMP 41e5a6 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0x3d6>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x1f8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
CMP %R15,-0xb8(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 41ec92 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0xac2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x4b74b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x4c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x1f8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %R10,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 41ec95 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0xac5>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
ADD %R15,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PXOR %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD 0x7bdf7(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSD 0x7c977(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVAPD 0x7be3f(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOVSD 0x7c96f(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 41ecf7 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0xb27>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	4.57	1.81
○Loop 148 - advec_cell.cpp:158-202 - exec	4.57	1.80
○Loop 147 - advec_cell.cpp:158-202 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code