OV - exec - Loop 629

	Loop Id: 629	Module: exec	Source: viscosity.cpp:37-66 [...]	Coverage: 3.29%

0x457300 IMUL	-0x80(%RBP),%RDX    [8]

0x457305 ADD	%R8,%RDX

0x457308 MOV	-0x78(%RBP),%RAX    [8]

0x45730c VMOVSD	%XMM11,(%RAX,%RDX,8)    [1]

0x457311 INC	%RCX

0x457314 CMP	%RCX,-0x38(%RBP)    [8]

0x457318 MOV	-0x40(%RBP),%R12    [8]

0x45731c JE	4571c0

0x457322 MOV	%RCX,%R8

0x457325 SHR	$0x20,%R8

0x457329 JE	457380

0x45732b MOV	%RCX,%RAX

0x45732e CQTO

0x457330 IDIV	%R12

0x457333 MOV	%RDX,%RSI

0x457336 TEST	%R8,%R8

0x457339 JE	45738e

0x45733b MOV	%RCX,%RAX

0x45733e XOR	%EDX,%EDX

0x457340 DIV	%R12

0x457343 JMP	457395

0x457380 MOV	%ECX,%EAX

0x457382 XOR	%EDX,%EDX

0x457384 DIV	%R12D

0x457387 MOV	%EDX,%ESI

0x457389 TEST	%R8,%R8

0x45738c JNE	45733b

0x45738e MOV	%ECX,%EAX

0x457390 XOR	%EDX,%EDX

0x457392 DIV	%R12D

0x457395 MOV	-0x70(%RBP),%RDX    [8]

0x457399 ADD	%ESI,%EDX

0x45739b MOVSXD	%EDX,%R8

0x45739e LEA	(%R13,%RAX,1),%EDX

0x4573a3 MOVSXD	%EDX,%RDX

0x4573a6 MOV	-0xa0(%RBP),%R10    [8]

0x4573ad MOV	%R10,%RBX

0x4573b0 IMUL	%RDX,%RBX

0x4573b4 LEA	(%R8,%RBX,1),%R14

0x4573b8 VMOVSD	(%R9,%R14,8),%XMM6    [4]

0x4573be LEA	0x1(%R13,%RAX,1),%R14D

0x4573c3 MOVSXD	%R14D,%R14

0x4573c6 IMUL	%R14,%R10

0x4573ca ADD	%R10,%R8

0x4573cd VMOVSD	(%R9,%R8,8),%XMM7    [4]

0x4573d3 LEA	(%RDI,%RSI,1),%R8D

0x4573d7 MOVSXD	%R8D,%R8

0x4573da ADD	%R8,%RBX

0x4573dd VMOVSD	(%R9,%RBX,8),%XMM9    [4]

0x4573e3 ADD	%R8,%R10

0x4573e6 VMOVSD	(%R9,%R10,8),%XMM8    [4]

0x4573ec MOV	-0x98(%RBP),%R12    [8]

0x4573f3 MOV	%R12,%R10

0x4573f6 IMUL	%R14,%R10

0x4573fa LEA	(%R10,%R8,1),%RBX

0x4573fe VMOVSD	(%R11,%RBX,8),%XMM10    [6]

0x457404 LEA	0x1(%RDI,%RSI,1),%EBX

0x457408 MOVSXD	%EBX,%RBX

0x45740b ADD	%RBX,%R10

0x45740e VMOVSD	(%R11,%R10,8),%XMM11    [6]

0x457414 MOV	%R12,%R10

0x457417 IMUL	%RDX,%R10

0x45741b LEA	(%R10,%R8,1),%R12

0x45741f VMOVSD	(%R11,%R12,8),%XMM13    [6]

0x457425 ADD	%RBX,%R10

0x457428 VMOVSD	(%R11,%R10,8),%XMM12    [6]

0x45742e MOV	-0x88(%RBP),%R12    [8]

0x457435 IMUL	%R12,%R14

0x457439 ADD	%R8,%R14

0x45743c VMOVSD	(%R15,%R14,8),%XMM14    [9]

0x457442 MOV	%R12,%R10

0x457445 IMUL	%RDX,%R10

0x457449 LEA	-0x1(%RDI,%RSI,1),%ESI

0x45744d MOVSXD	%ESI,%RSI

0x457450 ADD	%R10,%RSI

0x457453 ADD	%RBX,%R10

0x457456 VMOVHPD	(%R15,%R10,8),%XMM14,%XMM16    [9]

0x45745d LEA	-0x1(%R13,%RAX,1),%R10D

0x457462 MOVSXD	%R10D,%R10

0x457465 IMUL	%R12,%R10

0x457469 ADD	%R8,%R10

0x45746c VMOVSD	(%R15,%R10,8),%XMM14    [9]

0x457472 VMOVHPD	(%R15,%RSI,8),%XMM14,%XMM17    [9]

0x457479 LEA	0x2(%R13,%RAX,1),%EAX

0x45747e CLTQ

0x457480 MOV	-0x90(%RBP),%RSI    [8]

0x457487 VMOVSD	(%RSI,%RAX,8),%XMM14    [7]

0x45748c MOV	-0x30(%RBP),%RAX    [8]

0x457490 VMOVHPD	(%RAX,%RBX,8),%XMM14,%XMM18    [3]

0x457497 VADDSD	%XMM6,%XMM7,%XMM14

0x45749b VADDSD	%XMM8,%XMM9,%XMM15

0x4574a0 VSUBSD	%XMM15,%XMM14,%XMM15

0x4574a5 VADDSD	%XMM10,%XMM11,%XMM14

0x4574aa VADDSD	%XMM12,%XMM13,%XMM19

0x4574b0 VSUBSD	%XMM19,%XMM14,%XMM14

0x4574b6 VPUNPCKLQDQ	%XMM10,%XMM6,%XMM6

0x4574bb VPUNPCKLQDQ	%XMM13,%XMM9,%XMM10

0x4574c0 VMOVSD	(%RAX,%R8,8),%XMM9    [3]

0x4574c6 VADDPD	%XMM6,%XMM10,%XMM10

0x4574ca VMOVSD	(%RSI,%RDX,8),%XMM6    [7]

0x4574cf VPUNPCKLQDQ	%XMM11,%XMM7,%XMM7

0x4574d4 VSUBPD	%XMM10,%XMM7,%XMM7

0x4574d9 VPUNPCKLQDQ	%XMM12,%XMM8,%XMM8

0x4574de VADDPD	%XMM7,%XMM8,%XMM7

0x4574e2 VMULPD	%XMM0,%XMM7,%XMM7

0x4574e6 VPUNPCKLQDQ	%XMM9,%XMM6,%XMM8

0x4574eb VDIVPD	%XMM8,%XMM7,%XMM7

0x4574f0 VSHUFPD	$0x1,%XMM7,%XMM7,%XMM10

0x4574f5 VADDSD	%XMM7,%XMM10,%XMM7

0x4574f9 VSUBPD	%XMM17,%XMM16,%XMM10

0x4574ff VADDPD	%XMM8,%XMM18,%XMM8

0x457505 VDIVPD	%XMM8,%XMM10,%XMM8

0x45750a VMULPD	%XMM8,%XMM8,%XMM11

0x45750f VMULSD	%XMM1,%XMM15,%XMM10

0x457513 VSHUFPD	$0x1,%XMM11,%XMM11,%XMM12

0x457519 VMULSD	%XMM12,%XMM10,%XMM10

0x45751e VDIVSD	%XMM9,%XMM10,%XMM13

0x457523 VMULSD	%XMM1,%XMM14,%XMM10

0x457527 VMULSD	%XMM11,%XMM10,%XMM10

0x45752c VDIVSD	%XMM6,%XMM10,%XMM16

0x457532 VSHUFPD	$0x1,%XMM8,%XMM8,%XMM10

0x457538 VMULSD	%XMM7,%XMM10,%XMM7

0x45753c VFMADD213SD	%XMM13,%XMM8,%XMM7

0x457541 VADDSD	%XMM16,%XMM7,%XMM7

0x457547 VADDSD	%XMM12,%XMM11,%XMM11

0x45754c VMAXSD	%XMM2,%XMM11,%XMM11

0x457550 VDIVSD	%XMM11,%XMM7,%XMM7

0x457555 VXORPD	%XMM11,%XMM11,%XMM11

0x45755a VUCOMISD	%XMM11,%XMM7

0x45755f JA	457300

0x457565 VMULSD	%XMM15,%XMM9,%XMM12

0x45756a VFMADD213SD	%XMM12,%XMM6,%XMM14

0x45756f VUCOMISD	%XMM3,%XMM14

0x457573 JAE	457300

0x457579 VANDPD	%XMM4,%XMM10,%XMM11

0x45757d VMAXSD	%XMM2,%XMM11,%XMM11

0x457581 VXORPD	%XMM5,%XMM11,%XMM12

0x457585 VCMPSD	$0x1,%XMM3,%XMM10,%K1

0x45758c VMOVSD	%XMM12,%XMM11,%XMM11{%K1}

0x457592 VANDPD	%XMM4,%XMM8,%XMM8

0x457596 VMAXSD	%XMM2,%XMM8,%XMM8

0x45759a VXORPD	%XMM5,%XMM8,%XMM10

0x45759e VCMPSD	$0x1,%XMM3,%XMM11,%K1

0x4575a5 VMOVSD	%XMM10,%XMM8,%XMM8{%K1}

0x4575ab VMULSD	%XMM11,%XMM11,%XMM10

0x4575b0 VFMADD231SD	%XMM8,%XMM8,%XMM10

0x4575b5 VSQRTSD	%XMM10,%XMM10,%XMM10

0x4575ba VMULSD	%XMM9,%XMM10,%XMM9

0x4575bf VDIVSD	%XMM11,%XMM9,%XMM9

0x4575c4 VANDPD	%XMM4,%XMM9,%XMM9

0x4575c8 VMULSD	%XMM6,%XMM10,%XMM6

0x4575cc VDIVSD	%XMM8,%XMM6,%XMM6

0x4575d1 VANDPD	%XMM4,%XMM6,%XMM6

0x4575d5 VMINSD	%XMM9,%XMM6,%XMM8

0x4575da VCMPSD	$0x3,%XMM9,%XMM9,%K1

0x4575e1 VMOVSD	%XMM6,%XMM8,%XMM8{%K1}

0x4575e7 MOV	-0x68(%RBP),%RSI    [8]

0x4575eb MOV	0x10(%RSI),%RAX    [5]

0x4575ef VMULSD	%XMM7,%XMM8,%XMM6

0x4575f3 VMULSD	%XMM6,%XMM6,%XMM6

0x4575f7 MOV	(%RSI),%RSI    [5]

0x4575fa IMUL	%RDX,%RSI

0x4575fe ADD	%R8,%RSI

0x457601 VMOVSD	(%RAX,%RSI,8),%XMM7    [2]

0x457606 VADDSD	%XMM7,%XMM7,%XMM7

0x45760a VMULSD	%XMM7,%XMM6,%XMM11

0x45760e JMP	457300

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp: 37 - 66

--------------------------------------------------------------------------------

37:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

39:       double ugrad = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) - (xvel0(i, j) + xvel0(i + 0, j + 1));

40:       double vgrad = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) - (yvel0(i, j) + yvel0(i + 1, j + 0));

41:       double div = (celldx[i] * (ugrad) + celldy[j] * (vgrad));

42:       double strain2 = 0.5 * (xvel0(i + 0, j + 1) + xvel0(i + 1, j + 1) - xvel0(i, j) - xvel0(i + 1, j + 0)) / celldy[j] +

43:                        0.5 * (yvel0(i + 1, j + 0) + yvel0(i + 1, j + 1) - yvel0(i, j) - yvel0(i + 0, j + 1)) / celldx[i];

44:       double pgradx = (pressure(i + 1, j + 0) - pressure(i - 1, j + 0)) / (celldx[i] + celldx[i + 1]);

45:       double pgrady = (pressure(i + 0, j + 1) - pressure(i + 0, j - 1)) / (celldy[j] + celldy[j + 2]);

46:       double pgradx2 = pgradx * pgradx;

47:       double pgrady2 = pgrady * pgrady;

48:       double limiter = ((0.5 * (ugrad) / celldx[i]) * pgradx2 + (0.5 * (vgrad) / celldy[j]) * pgrady2 + strain2 * pgradx * pgrady) /

49:                        std::fmax(pgradx2 + pgrady2, g_small);

50:       if ((limiter > 0.0) || (div >= 0.0)) {

51:         viscosity(i, j) = 0.0;

52:       } else {

53:         double dirx = 1.0;

54:         if (pgradx < 0.0) dirx = -1.0;

55:         pgradx = dirx * std::fmax(g_small, std::fabs(pgradx));

56:         double diry = 1.0;

57:         if (pgradx < 0.0) diry = -1.0;

58:         pgrady = diry * std::fmax(g_small, std::fabs(pgrady));

59:         double pgrad = std::sqrt(pgradx * pgradx + pgrady * pgrady);

60:         double xgrad = std::fabs(celldx[i] * pgrad / pgradx);

61:         double ygrad = std::fabs(celldy[j] * pgrad / pgrady);

62:         double grad = std::fmin(xgrad, ygrad);

63:         double grad2 = grad * grad;

64:         viscosity(i, j) = 2.0 * density0(i, j) * grad2 * limiter * limiter;

65:       }

66:     }

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.98
CQA speedup if FP arith vectorized	1.23
CQA speedup if fully vectorized	1.94
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P0,
Function	viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source	viscosity.cpp:37-66,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	64.50
CQA cycles if no scalar integer	32.50
CQA cycles if FP arith vectorized	52.25
CQA cycles if fully vectorized	33.25
Front-end cycles	30.67
P0 cycles	31.83
P1 cycles	32.23
P2 cycles	10.00
P3 cycles	10.00
P4 cycles	0.50
P5 cycles	32.17
P6 cycles	16.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	16.00
P11 cycles	10.00
DIV/SQRT cycles	64.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	167.00
Nb uops	181.00
Nb loads	30.00
Nb stores	1.00
Nb stack references	11.00
FLOP/cycle	0.81
Nb FLOP add-sub	20.00
Nb FLOP mul	16.00
Nb FLOP fma	3.00
Nb FLOP div	9.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.84
Bytes prefetched	0.00
Bytes loaded	240.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	20.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	14.29
Vectorization ratio add_sub	31.25
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	16.67
Vectorization ratio other	31.25
Vector-efficiency ratio all	14.87
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	14.29
Vector-efficiency ratio add_sub	16.41
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	13.54
Vector-efficiency ratio other	16.41

Metric	Value
CQA speedup if no scalar integer	1.98
CQA speedup if FP arith vectorized	1.23
CQA speedup if fully vectorized	1.94
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P0,
Function	viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source	viscosity.cpp:37-66,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	64.50
CQA cycles if no scalar integer	32.50
CQA cycles if FP arith vectorized	52.25
CQA cycles if fully vectorized	33.25
Front-end cycles	30.67
P0 cycles	31.83
P1 cycles	32.23
P2 cycles	10.00
P3 cycles	10.00
P4 cycles	0.50
P5 cycles	32.17
P6 cycles	16.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	16.00
P11 cycles	10.00
DIV/SQRT cycles	64.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	167.00
Nb uops	181.00
Nb loads	30.00
Nb stores	1.00
Nb stack references	11.00
FLOP/cycle	0.81
Nb FLOP add-sub	20.00
Nb FLOP mul	16.00
Nb FLOP fma	3.00
Nb FLOP div	9.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.84
Bytes prefetched	0.00
Bytes loaded	240.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	20.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	14.29
Vectorization ratio add_sub	31.25
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	16.67
Vectorization ratio other	31.25
Vector-efficiency ratio all	14.87
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	14.29
Vector-efficiency ratio add_sub	16.41
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	13.54
Vector-efficiency ratio other	16.41

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source file and lines	viscosity.cpp:37-66
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:37-66
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=12
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 12 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 64.50 to 32.50 cycles (1.98x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 64.50 to 33.25 cycles (1.94x speedup).

Details

20% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
31% of SSE/AVX addition or subtraction instructions are used in vector version.
14% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
16% of SSE/AVX divide and square root instructions are used in vector version.
31% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 64.50 to 32.23 cycles (2.00x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 64.50 to 30.00 cycles (2.15x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 3 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:39
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:37
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:39
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:37

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:45
CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:37

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

40 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 9 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 52 FP arithmetical operations:

23: addition or subtraction (3 inside FMA instructions)
19: multiply (3 inside FMA instructions)
9: divide
1: square root

The binary loop is loading 240 bytes (30 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.21 FP operations per loaded or stored byte.

General properties

nb instructions	167
nb uops	181
loop length	728
used x86 registers	15
used mmx registers	0
used xmm registers	20
used ymm registers	0
used zmm registers	0
nb stack references	11
ADD-SUB / MUL ratio	1.07

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	30.67 cycles
front end	30.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	31.83	32.00	10.00	10.00	0.50	32.17	16.00	0.50	0.50	0.50	16.00	10.00
cycles	31.83	32.23	10.00	10.00	0.50	32.17	16.00	0.50	0.50	0.50	16.00	10.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

64.50

Cycles summary

Front-end	30.67
Dispatch	32.23
DIV/SQRT	64.50
Overall L1	64.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	23%
load	0%
store	0%
mul	14%
add-sub	33%
fma	0%
div/sqrt	25%
other	45%

INT+FP

all	20%
load	0%
store	0%
mul	14%
add-sub	31%
fma	0%
div/sqrt	16%
other	31%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	15%
load	12%
store	12%
mul	14%
add-sub	16%
fma	12%
div/sqrt	15%
other	18%

INT+FP

all	14%
load	12%
store	12%
mul	14%
add-sub	16%
fma	12%
div/sqrt	13%
other	16%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 64.50 cycles. At this rate:

1% of peak load performance is reached (3.72 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 457322

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
IMUL -0x80(%RBP),%RDX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
ADD %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x78(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM11,(%RAX,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RCX,-0x38(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 4571c0 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.extracted+0xb0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x20,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 457380 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.extracted+0x270>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %R12	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %R8,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 45738e <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.extracted+0x27e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
JMP 457395 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.extracted+0x285>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %R8,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 45733b <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.extracted+0x22b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV -0x70(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %ESI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EDX,%R8	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (%R13,%RAX,1),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %EDX,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV -0xa0(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RBX,1),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD (%R9,%R14,8),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%R13,%RAX,1),%R14D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOVSXD %R14D,%R14	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %R14,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R10,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R9,%R8,8),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%RDI,%RSI,1),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %R8D,%R8	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD %R8,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R9,%RBX,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R9,%R10,8),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x98(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R12,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R14,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R10,%R8,1),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD (%R11,%RBX,8),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RDI,%RSI,1),%EBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOVSXD %EBX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD %RBX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R11,%R10,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R12,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R10,%R8,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD (%R11,%R12,8),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RBX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R11,%R10,8),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x88(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R12,%R14	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R8,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R15,%R14,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R12,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA -0x1(%RDI,%RSI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOVSXD %ESI,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD %R10,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RBX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVHPD (%R15,%R10,8),%XMM14,%XMM16	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
LEA -0x1(%R13,%RAX,1),%R10D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOVSXD %R10D,%R10	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %R12,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R15,%R10,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVHPD (%R15,%RSI,8),%XMM14,%XMM17	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
LEA 0x2(%R13,%RAX,1),%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV -0x90(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RSI,%RAX,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVHPD (%RAX,%RBX,8),%XMM14,%XMM18	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
VADDSD %XMM6,%XMM7,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM8,%XMM9,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM15,%XMM14,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM10,%XMM11,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM12,%XMM13,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM19,%XMM14,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VPUNPCKLQDQ %XMM10,%XMM6,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPUNPCKLQDQ %XMM13,%XMM9,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX,%R8,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDPD %XMM6,%XMM10,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%RSI,%RDX,8),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPUNPCKLQDQ %XMM11,%XMM7,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBPD %XMM10,%XMM7,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPUNPCKLQDQ %XMM12,%XMM8,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDPD %XMM7,%XMM8,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMULPD %XMM0,%XMM7,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VPUNPCKLQDQ %XMM9,%XMM6,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VDIVPD %XMM8,%XMM7,%XMM7	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	vect (25.0%)
VSHUFPD $0x1,%XMM7,%XMM7,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM7,%XMM10,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBPD %XMM17,%XMM16,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM8,%XMM18,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VDIVPD %XMM8,%XMM10,%XMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	vect (25.0%)
VMULPD %XMM8,%XMM8,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMULSD %XMM1,%XMM15,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM11,%XMM11,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMULSD %XMM12,%XMM10,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM9,%XMM10,%XMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMULSD %XMM1,%XMM14,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM11,%XMM10,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM6,%XMM10,%XMM16	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VSHUFPD $0x1,%XMM8,%XMM8,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMULSD %XMM7,%XMM10,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM13,%XMM8,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM16,%XMM7,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM12,%XMM11,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMAXSD %XMM2,%XMM11,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM11,%XMM7,%XMM7	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VXORPD %XMM11,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VUCOMISD %XMM11,%XMM7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JA 457300 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.extracted+0x1f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMULSD %XMM15,%XMM9,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM12,%XMM6,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VUCOMISD %XMM3,%XMM14	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JAE 457300 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.extracted+0x1f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VANDPD %XMM4,%XMM10,%XMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMAXSD %XMM2,%XMM11,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VXORPD %XMM5,%XMM11,%XMM12	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VCMPSD $0x1,%XMM3,%XMM10,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM12,%XMM11,%XMM11{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VANDPD %XMM4,%XMM8,%XMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMAXSD %XMM2,%XMM8,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VXORPD %XMM5,%XMM8,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VCMPSD $0x1,%XMM3,%XMM11,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM10,%XMM8,%XMM8{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMULSD %XMM11,%XMM11,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM8,%XMM8,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSQRTSD %XMM10,%XMM10,%XMM10	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VMULSD %XMM9,%XMM10,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM11,%XMM9,%XMM9	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VANDPD %XMM4,%XMM9,%XMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMULSD %XMM6,%XMM10,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM8,%XMM6,%XMM6	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VANDPD %XMM4,%XMM6,%XMM6	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMINSD %XMM9,%XMM6,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x3,%XMM9,%XMM9,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM6,%XMM8,%XMM8{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV -0x68(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD %XMM7,%XMM8,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM6,%XMM6,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RSI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R8,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%RAX,%RSI,8),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD %XMM7,%XMM7,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM7,%XMM6,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 457300 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.extracted+0x1f0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .extracted]
Source file and lines	viscosity.cpp:37-66
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:37-66
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=12
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

20% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
31% of SSE/AVX addition or subtraction instructions are used in vector version.
14% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
16% of SSE/AVX divide and square root instructions are used in vector version.
31% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 64.50 to 30.00 cycles (2.15x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 3 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:39
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:37
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:39
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:37

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:45
CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:37

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 52 FP arithmetical operations:

23: addition or subtraction (3 inside FMA instructions)
19: multiply (3 inside FMA instructions)
9: divide
1: square root

The binary loop is loading 240 bytes (30 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.21 FP operations per loaded or stored byte.

General properties

nb instructions	167
nb uops	181
loop length	728
used x86 registers	15
used mmx registers	0
used xmm registers	20
used ymm registers	0
used zmm registers	0
nb stack references	11
ADD-SUB / MUL ratio	1.07

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	30.67 cycles
front end	30.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	31.83	32.00	10.00	10.00	0.50	32.17	16.00	0.50	0.50	0.50	16.00	10.00
cycles	31.83	32.23	10.00	10.00	0.50	32.17	16.00	0.50	0.50	0.50	16.00	10.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

64.50

Cycles summary

Front-end	30.67
Dispatch	32.23
DIV/SQRT	64.50
Overall L1	64.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	23%
load	0%
store	0%
mul	14%
add-sub	33%
fma	0%
div/sqrt	25%
other	45%

INT+FP

all	20%
load	0%
store	0%
mul	14%
add-sub	31%
fma	0%
div/sqrt	16%
other	31%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	15%
load	12%
store	12%
mul	14%
add-sub	16%
fma	12%
div/sqrt	15%
other	18%

INT+FP

all	14%
load	12%
store	12%
mul	14%
add-sub	16%
fma	12%
div/sqrt	13%
other	16%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 64.50 cycles. At this rate:

1% of peak load performance is reached (3.72 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 457322

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
IMUL -0x80(%RBP),%RDX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
ADD %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x78(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM11,(%RAX,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RCX,-0x38(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 4571c0 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.extracted+0xb0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x20,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 457380 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.extracted+0x270>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %R12	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %R8,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 45738e <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.extracted+0x27e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
JMP 457395 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.extracted+0x285>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %R8,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 45733b <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.extracted+0x22b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV -0x70(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %ESI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %EDX,%R8	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (%R13,%RAX,1),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %EDX,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV -0xa0(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RBX,1),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD (%R9,%R14,8),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%R13,%RAX,1),%R14D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOVSXD %R14D,%R14	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %R14,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R10,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R9,%R8,8),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%RDI,%RSI,1),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD %R8D,%R8	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD %R8,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R9,%RBX,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R9,%R10,8),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x98(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R12,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R14,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R10,%R8,1),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD (%R11,%RBX,8),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RDI,%RSI,1),%EBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOVSXD %EBX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD %RBX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R11,%R10,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R12,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R10,%R8,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD (%R11,%R12,8),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RBX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R11,%R10,8),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x88(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R12,%R14	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R8,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R15,%R14,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R12,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDX,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA -0x1(%RDI,%RSI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOVSXD %ESI,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD %R10,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RBX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVHPD (%R15,%R10,8),%XMM14,%XMM16	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
LEA -0x1(%R13,%RAX,1),%R10D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOVSXD %R10D,%R10	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
IMUL %R12,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R15,%R10,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVHPD (%R15,%RSI,8),%XMM14,%XMM17	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
LEA 0x2(%R13,%RAX,1),%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV -0x90(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RSI,%RAX,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVHPD (%RAX,%RBX,8),%XMM14,%XMM18	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1	scal (12.5%)
VADDSD %XMM6,%XMM7,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM8,%XMM9,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM15,%XMM14,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM10,%XMM11,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM12,%XMM13,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM19,%XMM14,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VPUNPCKLQDQ %XMM10,%XMM6,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPUNPCKLQDQ %XMM13,%XMM9,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX,%R8,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDPD %XMM6,%XMM10,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%RSI,%RDX,8),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPUNPCKLQDQ %XMM11,%XMM7,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBPD %XMM10,%XMM7,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPUNPCKLQDQ %XMM12,%XMM8,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDPD %XMM7,%XMM8,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMULPD %XMM0,%XMM7,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VPUNPCKLQDQ %XMM9,%XMM6,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VDIVPD %XMM8,%XMM7,%XMM7	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	vect (25.0%)
VSHUFPD $0x1,%XMM7,%XMM7,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM7,%XMM10,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBPD %XMM17,%XMM16,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM8,%XMM18,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VDIVPD %XMM8,%XMM10,%XMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	vect (25.0%)
VMULPD %XMM8,%XMM8,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMULSD %XMM1,%XMM15,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM11,%XMM11,%XMM12	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMULSD %XMM12,%XMM10,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM9,%XMM10,%XMM13	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VMULSD %XMM1,%XMM14,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM11,%XMM10,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM6,%XMM10,%XMM16	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VSHUFPD $0x1,%XMM8,%XMM8,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMULSD %XMM7,%XMM10,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM13,%XMM8,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM16,%XMM7,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM12,%XMM11,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMAXSD %XMM2,%XMM11,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM11,%XMM7,%XMM7	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VXORPD %XMM11,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VUCOMISD %XMM11,%XMM7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JA 457300 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.extracted+0x1f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMULSD %XMM15,%XMM9,%XMM12	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM12,%XMM6,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VUCOMISD %XMM3,%XMM14	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JAE 457300 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.extracted+0x1f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VANDPD %XMM4,%XMM10,%XMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMAXSD %XMM2,%XMM11,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VXORPD %XMM5,%XMM11,%XMM12	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VCMPSD $0x1,%XMM3,%XMM10,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM12,%XMM11,%XMM11{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VANDPD %XMM4,%XMM8,%XMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMAXSD %XMM2,%XMM8,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VXORPD %XMM5,%XMM8,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VCMPSD $0x1,%XMM3,%XMM11,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM10,%XMM8,%XMM8{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMULSD %XMM11,%XMM11,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM8,%XMM8,%XMM10	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSQRTSD %XMM10,%XMM10,%XMM10	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VMULSD %XMM9,%XMM10,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM11,%XMM9,%XMM9	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VANDPD %XMM4,%XMM9,%XMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMULSD %XMM6,%XMM10,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM8,%XMM6,%XMM6	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VANDPD %XMM4,%XMM6,%XMM6	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMINSD %XMM9,%XMM6,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x3,%XMM9,%XMM9,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM6,%XMM8,%XMM8{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV -0x68(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD %XMM7,%XMM8,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM6,%XMM6,%XMM6	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RSI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R8,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%RAX,%RSI,8),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD %XMM7,%XMM7,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM7,%XMM6,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 457300 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.extracted+0x1f0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code